diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/Makefile | 2 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7343.c | 211 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 33 |
3 files changed, 213 insertions, 33 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 02a0b17347b..f4415f9ebac 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile | |||
@@ -24,7 +24,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o | |||
24 | clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o | 24 | clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o |
25 | clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o | 25 | clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o |
26 | clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o | 26 | clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o |
27 | clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o | 27 | clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o |
28 | clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o | 28 | clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o |
29 | clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o | 29 | clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o |
30 | clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o | 30 | clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c new file mode 100644 index 00000000000..0ee3ee86125 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c | |||
@@ -0,0 +1,211 @@ | |||
1 | /* | ||
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7343.c | ||
3 | * | ||
4 | * SH7343 clock framework support | ||
5 | * | ||
6 | * Copyright (C) 2009 Magnus Damm | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/io.h> | ||
24 | #include <asm/clock.h> | ||
25 | |||
26 | /* SH7343 registers */ | ||
27 | #define FRQCR 0xa4150000 | ||
28 | #define VCLKCR 0xa4150004 | ||
29 | #define SCLKACR 0xa4150008 | ||
30 | #define SCLKBCR 0xa415000c | ||
31 | #define PLLCR 0xa4150024 | ||
32 | #define MSTPCR0 0xa4150030 | ||
33 | #define MSTPCR1 0xa4150034 | ||
34 | #define MSTPCR2 0xa4150038 | ||
35 | #define DLLFRQ 0xa4150050 | ||
36 | |||
37 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | ||
38 | static struct clk r_clk = { | ||
39 | .name = "rclk", | ||
40 | .id = -1, | ||
41 | .rate = 32768, | ||
42 | }; | ||
43 | |||
44 | /* | ||
45 | * Default rate for the root input clock, reset this with clk_set_rate() | ||
46 | * from the platform code. | ||
47 | */ | ||
48 | struct clk extal_clk = { | ||
49 | .name = "extal", | ||
50 | .id = -1, | ||
51 | .rate = 33333333, | ||
52 | }; | ||
53 | |||
54 | /* The dll block multiplies the 32khz r_clk, may be used instead of extal */ | ||
55 | static unsigned long dll_recalc(struct clk *clk) | ||
56 | { | ||
57 | unsigned long mult; | ||
58 | |||
59 | if (__raw_readl(PLLCR) & 0x1000) | ||
60 | mult = __raw_readl(DLLFRQ); | ||
61 | else | ||
62 | mult = 0; | ||
63 | |||
64 | return clk->parent->rate * mult; | ||
65 | } | ||
66 | |||
67 | static struct clk_ops dll_clk_ops = { | ||
68 | .recalc = dll_recalc, | ||
69 | }; | ||
70 | |||
71 | static struct clk dll_clk = { | ||
72 | .name = "dll_clk", | ||
73 | .id = -1, | ||
74 | .ops = &dll_clk_ops, | ||
75 | .parent = &r_clk, | ||
76 | .flags = CLK_ENABLE_ON_INIT, | ||
77 | }; | ||
78 | |||
79 | static unsigned long pll_recalc(struct clk *clk) | ||
80 | { | ||
81 | unsigned long mult = 1; | ||
82 | |||
83 | if (__raw_readl(PLLCR) & 0x4000) | ||
84 | mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); | ||
85 | |||
86 | return clk->parent->rate * mult; | ||
87 | } | ||
88 | |||
89 | static struct clk_ops pll_clk_ops = { | ||
90 | .recalc = pll_recalc, | ||
91 | }; | ||
92 | |||
93 | static struct clk pll_clk = { | ||
94 | .name = "pll_clk", | ||
95 | .id = -1, | ||
96 | .ops = &pll_clk_ops, | ||
97 | .flags = CLK_ENABLE_ON_INIT, | ||
98 | }; | ||
99 | |||
100 | struct clk *main_clks[] = { | ||
101 | &r_clk, | ||
102 | &extal_clk, | ||
103 | &dll_clk, | ||
104 | &pll_clk, | ||
105 | }; | ||
106 | |||
107 | static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; | ||
108 | static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; | ||
109 | |||
110 | static struct clk_div_mult_table div4_table = { | ||
111 | .divisors = divisors, | ||
112 | .nr_divisors = ARRAY_SIZE(divisors), | ||
113 | .multipliers = multipliers, | ||
114 | .nr_multipliers = ARRAY_SIZE(multipliers), | ||
115 | }; | ||
116 | |||
117 | enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, | ||
118 | DIV4_SIUA, DIV4_SIUB, DIV4_NR }; | ||
119 | |||
120 | #define DIV4(_str, _reg, _bit, _mask, _flags) \ | ||
121 | SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) | ||
122 | |||
123 | struct clk div4_clks[DIV4_NR] = { | ||
124 | [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), | ||
125 | [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), | ||
126 | [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), | ||
127 | [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), | ||
128 | [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), | ||
129 | [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), | ||
130 | [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), | ||
131 | [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), | ||
132 | }; | ||
133 | |||
134 | struct clk div6_clks[] = { | ||
135 | SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), | ||
136 | }; | ||
137 | |||
138 | #define MSTP(_str, _parent, _reg, _bit, _flags) \ | ||
139 | SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) | ||
140 | |||
141 | static struct clk mstp_clks[] = { | ||
142 | MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), | ||
143 | MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), | ||
144 | MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), | ||
145 | MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), | ||
146 | MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), | ||
147 | MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), | ||
148 | MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), | ||
149 | MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), | ||
150 | MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), | ||
151 | MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), | ||
152 | MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), | ||
153 | MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), | ||
154 | MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), | ||
155 | MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), | ||
156 | MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), | ||
157 | MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), | ||
158 | MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), | ||
159 | MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), | ||
160 | MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), | ||
161 | MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), | ||
162 | MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), | ||
163 | MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), | ||
164 | MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), | ||
165 | |||
166 | MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), | ||
167 | MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), | ||
168 | |||
169 | MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), | ||
170 | MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), | ||
171 | MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), | ||
172 | MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), | ||
173 | MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), | ||
174 | MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), | ||
175 | MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), | ||
176 | MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), | ||
177 | MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), | ||
178 | MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), | ||
179 | MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), | ||
180 | MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), | ||
181 | MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), | ||
182 | MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), | ||
183 | MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), | ||
184 | MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), | ||
185 | MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), | ||
186 | }; | ||
187 | |||
188 | int __init arch_clk_init(void) | ||
189 | { | ||
190 | int k, ret = 0; | ||
191 | |||
192 | /* autodetect extal or dll configuration */ | ||
193 | if (__raw_readl(PLLCR) & 0x1000) | ||
194 | pll_clk.parent = &dll_clk; | ||
195 | else | ||
196 | pll_clk.parent = &extal_clk; | ||
197 | |||
198 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | ||
199 | ret = clk_register(main_clks[k]); | ||
200 | |||
201 | if (!ret) | ||
202 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | ||
203 | |||
204 | if (!ret) | ||
205 | ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); | ||
206 | |||
207 | if (!ret) | ||
208 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | ||
209 | |||
210 | return ret; | ||
211 | } | ||
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 5e08504da3a..8aaaac240ad 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 2 | * arch/sh/kernel/cpu/sh4a/clock-sh7722.c |
3 | * | 3 | * |
4 | * SH7343, SH7722 & SH7366 support for the clock framework | 4 | * SH7722 & SH7366 support for the clock framework |
5 | * | 5 | * |
6 | * Copyright (c) 2006-2007 Nomad Global Solutions Inc | 6 | * Copyright (c) 2006-2007 Nomad Global Solutions Inc |
7 | * Based on code for sh7343 by Paul Mundt | 7 | * Based on code for sh7343 by Paul Mundt |
@@ -417,7 +417,6 @@ static struct clk_ops sh7722_frqcr_clk_ops = { | |||
417 | /* | 417 | /* |
418 | * clock ops methods for SIU A/B and IrDA clock | 418 | * clock ops methods for SIU A/B and IrDA clock |
419 | */ | 419 | */ |
420 | #ifndef CONFIG_CPU_SUBTYPE_SH7343 | ||
421 | static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) | 420 | static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) |
422 | { | 421 | { |
423 | unsigned long r; | 422 | unsigned long r; |
@@ -469,8 +468,6 @@ static struct clk_ops sh7722_siu_clk_ops = { | |||
469 | .disable = sh7722_siu_disable, | 468 | .disable = sh7722_siu_disable, |
470 | }; | 469 | }; |
471 | 470 | ||
472 | #endif /* CONFIG_CPU_SUBTYPE_SH7343 */ | ||
473 | |||
474 | static int sh7722_video_enable(struct clk *clk) | 471 | static int sh7722_video_enable(struct clk *clk) |
475 | { | 472 | { |
476 | unsigned long r; | 473 | unsigned long r; |
@@ -542,7 +539,6 @@ static struct clk sh7722_r_clock = { | |||
542 | .rate = 32768, | 539 | .rate = 32768, |
543 | }; | 540 | }; |
544 | 541 | ||
545 | #if !defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
546 | /* | 542 | /* |
547 | * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops | 543 | * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops |
548 | * methods of clk_ops determine which register they should access by | 544 | * methods of clk_ops determine which register they should access by |
@@ -559,7 +555,6 @@ static struct clk sh7722_siu_b_clock = { | |||
559 | .arch_flags = SCLKBCR, | 555 | .arch_flags = SCLKBCR, |
560 | .ops = &sh7722_siu_clk_ops, | 556 | .ops = &sh7722_siu_clk_ops, |
561 | }; | 557 | }; |
562 | #endif /* CONFIG_CPU_SUBTYPE_SH7343 */ | ||
563 | 558 | ||
564 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) | 559 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
565 | static struct clk sh7722_irda_clock = { | 560 | static struct clk sh7722_irda_clock = { |
@@ -659,30 +654,6 @@ static struct clk sh7722_mstpcr_clocks[] = { | |||
659 | MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), | 654 | MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), |
660 | MSTPCR("lcdc0", "bus_clk", 2, 0, 0), | 655 | MSTPCR("lcdc0", "bus_clk", 2, 0, 0), |
661 | #endif | 656 | #endif |
662 | #if defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
663 | MSTPCR("uram0", "umem_clk", 0, 28, CLK_ENABLE_ON_INIT), | ||
664 | MSTPCR("xymem0", "bus_clk", 0, 26, CLK_ENABLE_ON_INIT), | ||
665 | MSTPCR("tmu0", "peripheral_clk", 0, 15, 0), | ||
666 | MSTPCR("cmt0", "r_clk", 0, 14, 0), | ||
667 | MSTPCR("rwdt0", "r_clk", 0, 13, 0), | ||
668 | MSTPCR("scif0", "peripheral_clk", 0, 7, 0), | ||
669 | MSTPCR("scif1", "peripheral_clk", 0, 6, 0), | ||
670 | MSTPCR("scif2", "peripheral_clk", 0, 5, 0), | ||
671 | MSTPCR("scif3", "peripheral_clk", 0, 4, 0), | ||
672 | MSTPCR("i2c0", "peripheral_clk", 1, 9, 0), | ||
673 | MSTPCR("i2c1", "peripheral_clk", 1, 8, 0), | ||
674 | MSTPCR("sdhi0", "peripheral_clk", 2, 18, 0), | ||
675 | MSTPCR("keysc0", "r_clk", 2, 14, 0), | ||
676 | MSTPCR("usbf0", "peripheral_clk", 2, 11, 0), | ||
677 | MSTPCR("siu0", "bus_clk", 2, 8, 0), | ||
678 | MSTPCR("jpu0", "bus_clk", 2, 6, CLK_ENABLE_ON_INIT), | ||
679 | MSTPCR("vou0", "bus_clk", 2, 5, 0), | ||
680 | MSTPCR("beu0", "bus_clk", 2, 4, 0), | ||
681 | MSTPCR("ceu0", "bus_clk", 2, 3, 0), | ||
682 | MSTPCR("veu0", "bus_clk", 2, 2, CLK_ENABLE_ON_INIT), | ||
683 | MSTPCR("vpu0", "bus_clk", 2, 1, CLK_ENABLE_ON_INIT), | ||
684 | MSTPCR("lcdc0", "bus_clk", 2, 0, 0), | ||
685 | #endif | ||
686 | #if defined(CONFIG_CPU_SUBTYPE_SH7366) | 657 | #if defined(CONFIG_CPU_SUBTYPE_SH7366) |
687 | /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ | 658 | /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ |
688 | MSTPCR("tlb0", "cpu_clk", 0, 31, 0), | 659 | MSTPCR("tlb0", "cpu_clk", 0, 31, 0), |
@@ -730,10 +701,8 @@ static struct clk *sh7722_clocks[] = { | |||
730 | &sh7722_sh_clock, | 701 | &sh7722_sh_clock, |
731 | &sh7722_peripheral_clock, | 702 | &sh7722_peripheral_clock, |
732 | &sh7722_sdram_clock, | 703 | &sh7722_sdram_clock, |
733 | #if !defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
734 | &sh7722_siu_a_clock, | 704 | &sh7722_siu_a_clock, |
735 | &sh7722_siu_b_clock, | 705 | &sh7722_siu_b_clock, |
736 | #endif | ||
737 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) | 706 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
738 | &sh7722_irda_clock, | 707 | &sh7722_irda_clock, |
739 | #endif | 708 | #endif |