diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7722.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 310 |
1 files changed, 212 insertions, 98 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index db913855c2f..0e174af2187 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |||
@@ -229,7 +229,7 @@ struct frqcr_context sh7722_get_clk_context(const char *name) | |||
229 | } | 229 | } |
230 | 230 | ||
231 | /** | 231 | /** |
232 | * sh7722_find_divisors - find divisor for setting rate | 232 | * sh7722_find_div_index - find divisor for setting rate |
233 | * | 233 | * |
234 | * All sh7722 clocks use the same set of multipliers/divisors. This function | 234 | * All sh7722 clocks use the same set of multipliers/divisors. This function |
235 | * chooses correct divisor to set the rate of clock with parent clock that | 235 | * chooses correct divisor to set the rate of clock with parent clock that |
@@ -238,7 +238,7 @@ struct frqcr_context sh7722_get_clk_context(const char *name) | |||
238 | * @parent_rate: rate of parent clock | 238 | * @parent_rate: rate of parent clock |
239 | * @rate: requested rate to be set | 239 | * @rate: requested rate to be set |
240 | */ | 240 | */ |
241 | static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate) | 241 | static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate) |
242 | { | 242 | { |
243 | unsigned div2 = parent_rate * 2 / rate; | 243 | unsigned div2 = parent_rate * 2 / rate; |
244 | int index; | 244 | int index; |
@@ -247,12 +247,12 @@ static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate) | |||
247 | return -EINVAL; | 247 | return -EINVAL; |
248 | 248 | ||
249 | for (index = 1; index < ARRAY_SIZE(divisors2); index++) { | 249 | for (index = 1; index < ARRAY_SIZE(divisors2); index++) { |
250 | if (div2 > divisors2[index] && div2 <= divisors2[index]) | 250 | if (div2 > divisors2[index - 1] && div2 <= divisors2[index]) |
251 | break; | 251 | break; |
252 | } | 252 | } |
253 | if (index >= ARRAY_SIZE(divisors2)) | 253 | if (index >= ARRAY_SIZE(divisors2)) |
254 | index = ARRAY_SIZE(divisors2) - 1; | 254 | index = ARRAY_SIZE(divisors2) - 1; |
255 | return divisors2[index]; | 255 | return index; |
256 | } | 256 | } |
257 | 257 | ||
258 | static void sh7722_frqcr_recalc(struct clk *clk) | 258 | static void sh7722_frqcr_recalc(struct clk *clk) |
@@ -279,12 +279,12 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, | |||
279 | return -EINVAL; | 279 | return -EINVAL; |
280 | 280 | ||
281 | /* look for multiplier/divisor pair */ | 281 | /* look for multiplier/divisor pair */ |
282 | div = sh7722_find_divisors(parent_rate, rate); | 282 | div = sh7722_find_div_index(parent_rate, rate); |
283 | if (div<0) | 283 | if (div<0) |
284 | return div; | 284 | return div; |
285 | 285 | ||
286 | /* calculate new value of clock rate */ | 286 | /* calculate new value of clock rate */ |
287 | clk->rate = parent_rate * 2 / div; | 287 | clk->rate = parent_rate * 2 / divisors2[div]; |
288 | frqcr = ctrl_inl(FRQCR); | 288 | frqcr = ctrl_inl(FRQCR); |
289 | 289 | ||
290 | /* FIXME: adjust as algo_id specifies */ | 290 | /* FIXME: adjust as algo_id specifies */ |
@@ -353,7 +353,7 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, | |||
353 | int part_div; | 353 | int part_div; |
354 | 354 | ||
355 | if (likely(!err)) { | 355 | if (likely(!err)) { |
356 | part_div = sh7722_find_divisors(parent_rate, | 356 | part_div = sh7722_find_div_index(parent_rate, |
357 | rate); | 357 | rate); |
358 | if (part_div > 0) { | 358 | if (part_div > 0) { |
359 | part_ctx = sh7722_get_clk_context( | 359 | part_ctx = sh7722_get_clk_context( |
@@ -394,12 +394,12 @@ static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate) | |||
394 | int div; | 394 | int div; |
395 | 395 | ||
396 | /* look for multiplier/divisor pair */ | 396 | /* look for multiplier/divisor pair */ |
397 | div = sh7722_find_divisors(parent_rate, rate); | 397 | div = sh7722_find_div_index(parent_rate, rate); |
398 | if (div < 0) | 398 | if (div < 0) |
399 | return clk->rate; | 399 | return clk->rate; |
400 | 400 | ||
401 | /* calculate new value of clock rate */ | 401 | /* calculate new value of clock rate */ |
402 | return parent_rate * 2 / div; | 402 | return parent_rate * 2 / divisors2[div]; |
403 | } | 403 | } |
404 | 404 | ||
405 | static struct clk_ops sh7722_frqcr_clk_ops = { | 405 | static struct clk_ops sh7722_frqcr_clk_ops = { |
@@ -421,7 +421,7 @@ static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) | |||
421 | int div; | 421 | int div; |
422 | 422 | ||
423 | r = ctrl_inl(clk->arch_flags); | 423 | r = ctrl_inl(clk->arch_flags); |
424 | div = sh7722_find_divisors(clk->parent->rate, rate); | 424 | div = sh7722_find_div_index(clk->parent->rate, rate); |
425 | if (div < 0) | 425 | if (div < 0) |
426 | return div; | 426 | return div; |
427 | r = (r & ~0xF) | div; | 427 | r = (r & ~0xF) | div; |
@@ -516,16 +516,19 @@ static struct clk_ops sh7722_video_clk_ops = { | |||
516 | static struct clk sh7722_umem_clock = { | 516 | static struct clk sh7722_umem_clock = { |
517 | .name = "umem_clk", | 517 | .name = "umem_clk", |
518 | .ops = &sh7722_frqcr_clk_ops, | 518 | .ops = &sh7722_frqcr_clk_ops, |
519 | .flags = CLK_RATE_PROPAGATES, | ||
519 | }; | 520 | }; |
520 | 521 | ||
521 | static struct clk sh7722_sh_clock = { | 522 | static struct clk sh7722_sh_clock = { |
522 | .name = "sh_clk", | 523 | .name = "sh_clk", |
523 | .ops = &sh7722_frqcr_clk_ops, | 524 | .ops = &sh7722_frqcr_clk_ops, |
525 | .flags = CLK_RATE_PROPAGATES, | ||
524 | }; | 526 | }; |
525 | 527 | ||
526 | static struct clk sh7722_peripheral_clock = { | 528 | static struct clk sh7722_peripheral_clock = { |
527 | .name = "peripheral_clk", | 529 | .name = "peripheral_clk", |
528 | .ops = &sh7722_frqcr_clk_ops, | 530 | .ops = &sh7722_frqcr_clk_ops, |
531 | .flags = CLK_RATE_PROPAGATES, | ||
529 | }; | 532 | }; |
530 | 533 | ||
531 | static struct clk sh7722_sdram_clock = { | 534 | static struct clk sh7722_sdram_clock = { |
@@ -533,6 +536,11 @@ static struct clk sh7722_sdram_clock = { | |||
533 | .ops = &sh7722_frqcr_clk_ops, | 536 | .ops = &sh7722_frqcr_clk_ops, |
534 | }; | 537 | }; |
535 | 538 | ||
539 | static struct clk sh7722_r_clock = { | ||
540 | .name = "r_clk", | ||
541 | .rate = 32768, | ||
542 | .flags = CLK_RATE_PROPAGATES, | ||
543 | }; | ||
536 | 544 | ||
537 | #ifndef CONFIG_CPU_SUBTYPE_SH7343 | 545 | #ifndef CONFIG_CPU_SUBTYPE_SH7343 |
538 | 546 | ||
@@ -567,12 +575,30 @@ static struct clk sh7722_video_clock = { | |||
567 | .ops = &sh7722_video_clk_ops, | 575 | .ops = &sh7722_video_clk_ops, |
568 | }; | 576 | }; |
569 | 577 | ||
570 | static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg, | 578 | #define MSTPCR_ARCH_FLAGS(reg, bit) (((reg) << 8) | (bit)) |
571 | int enable) | 579 | #define MSTPCR_ARCH_FLAGS_REG(value) ((value) >> 8) |
580 | #define MSTPCR_ARCH_FLAGS_BIT(value) ((value) & 0xff) | ||
581 | |||
582 | static int sh7722_mstpcr_start_stop(struct clk *clk, int enable) | ||
572 | { | 583 | { |
573 | unsigned long bit = clk->arch_flags; | 584 | unsigned long bit = MSTPCR_ARCH_FLAGS_BIT(clk->arch_flags); |
585 | unsigned long reg; | ||
574 | unsigned long r; | 586 | unsigned long r; |
575 | 587 | ||
588 | switch(MSTPCR_ARCH_FLAGS_REG(clk->arch_flags)) { | ||
589 | case 0: | ||
590 | reg = MSTPCR0; | ||
591 | break; | ||
592 | case 1: | ||
593 | reg = MSTPCR1; | ||
594 | break; | ||
595 | case 2: | ||
596 | reg = MSTPCR2; | ||
597 | break; | ||
598 | default: | ||
599 | return -EINVAL; | ||
600 | } | ||
601 | |||
576 | r = ctrl_inl(reg); | 602 | r = ctrl_inl(reg); |
577 | 603 | ||
578 | if (enable) | 604 | if (enable) |
@@ -584,96 +610,175 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg, | |||
584 | return 0; | 610 | return 0; |
585 | } | 611 | } |
586 | 612 | ||
587 | static void sh7722_mstpcr0_enable(struct clk *clk) | 613 | static void sh7722_mstpcr_enable(struct clk *clk) |
588 | { | ||
589 | sh7722_mstpcr_start_stop(clk, MSTPCR0, 1); | ||
590 | } | ||
591 | |||
592 | static void sh7722_mstpcr0_disable(struct clk *clk) | ||
593 | { | ||
594 | sh7722_mstpcr_start_stop(clk, MSTPCR0, 0); | ||
595 | } | ||
596 | |||
597 | static void sh7722_mstpcr1_enable(struct clk *clk) | ||
598 | { | ||
599 | sh7722_mstpcr_start_stop(clk, MSTPCR1, 1); | ||
600 | } | ||
601 | |||
602 | static void sh7722_mstpcr1_disable(struct clk *clk) | ||
603 | { | 614 | { |
604 | sh7722_mstpcr_start_stop(clk, MSTPCR1, 0); | 615 | sh7722_mstpcr_start_stop(clk, 1); |
605 | } | 616 | } |
606 | 617 | ||
607 | static void sh7722_mstpcr2_enable(struct clk *clk) | 618 | static void sh7722_mstpcr_disable(struct clk *clk) |
608 | { | 619 | { |
609 | sh7722_mstpcr_start_stop(clk, MSTPCR2, 1); | 620 | sh7722_mstpcr_start_stop(clk, 0); |
610 | } | 621 | } |
611 | 622 | ||
612 | static void sh7722_mstpcr2_disable(struct clk *clk) | 623 | static void sh7722_mstpcr_recalc(struct clk *clk) |
613 | { | 624 | { |
614 | sh7722_mstpcr_start_stop(clk, MSTPCR2, 0); | 625 | if (clk->parent) |
626 | clk->rate = clk->parent->rate; | ||
615 | } | 627 | } |
616 | 628 | ||
617 | static struct clk_ops sh7722_mstpcr0_clk_ops = { | 629 | static struct clk_ops sh7722_mstpcr_clk_ops = { |
618 | .enable = sh7722_mstpcr0_enable, | 630 | .enable = sh7722_mstpcr_enable, |
619 | .disable = sh7722_mstpcr0_disable, | 631 | .disable = sh7722_mstpcr_disable, |
620 | }; | 632 | .recalc = sh7722_mstpcr_recalc, |
621 | |||
622 | static struct clk_ops sh7722_mstpcr1_clk_ops = { | ||
623 | .enable = sh7722_mstpcr1_enable, | ||
624 | .disable = sh7722_mstpcr1_disable, | ||
625 | }; | 633 | }; |
626 | 634 | ||
627 | static struct clk_ops sh7722_mstpcr2_clk_ops = { | 635 | #define MSTPCR(_name, _parent, regnr, bitnr) \ |
628 | .enable = sh7722_mstpcr2_enable, | 636 | { \ |
629 | .disable = sh7722_mstpcr2_disable, | 637 | .name = _name, \ |
630 | }; | 638 | .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \ |
631 | 639 | .ops = (void *)_parent, \ | |
632 | #define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \ | ||
633 | { \ | ||
634 | .name = "mstp" __stringify(regnr) bitstr, \ | ||
635 | .arch_flags = bitnr, \ | ||
636 | .ops = &sh7722_mstpcr ## regnr ## _clk_ops, \ | ||
637 | } | 640 | } |
638 | 641 | ||
639 | #define DECLARE_MSTPCR(regnr) \ | 642 | static struct clk sh7722_mstpcr_clocks[] = { |
640 | DECLARE_MSTPCRN(regnr, 31, "31"), \ | 643 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
641 | DECLARE_MSTPCRN(regnr, 30, "30"), \ | 644 | MSTPCR("uram0", "umem_clk", 0, 28), |
642 | DECLARE_MSTPCRN(regnr, 29, "29"), \ | 645 | MSTPCR("xymem0", "bus_clk", 0, 26), |
643 | DECLARE_MSTPCRN(regnr, 28, "28"), \ | 646 | MSTPCR("tmu0", "peripheral_clk", 0, 15), |
644 | DECLARE_MSTPCRN(regnr, 27, "27"), \ | 647 | MSTPCR("cmt0", "r_clk", 0, 14), |
645 | DECLARE_MSTPCRN(regnr, 26, "26"), \ | 648 | MSTPCR("rwdt0", "r_clk", 0, 13), |
646 | DECLARE_MSTPCRN(regnr, 25, "25"), \ | 649 | MSTPCR("flctl0", "peripheral_clk", 0, 10), |
647 | DECLARE_MSTPCRN(regnr, 24, "24"), \ | 650 | MSTPCR("scif0", "peripheral_clk", 0, 7), |
648 | DECLARE_MSTPCRN(regnr, 23, "23"), \ | 651 | MSTPCR("scif1", "peripheral_clk", 0, 6), |
649 | DECLARE_MSTPCRN(regnr, 22, "22"), \ | 652 | MSTPCR("scif2", "peripheral_clk", 0, 5), |
650 | DECLARE_MSTPCRN(regnr, 21, "21"), \ | 653 | MSTPCR("i2c0", "peripheral_clk", 1, 9), |
651 | DECLARE_MSTPCRN(regnr, 20, "20"), \ | 654 | MSTPCR("rtc0", "r_clk", 1, 8), |
652 | DECLARE_MSTPCRN(regnr, 19, "19"), \ | 655 | MSTPCR("sdhi0", "peripheral_clk", 2, 18), |
653 | DECLARE_MSTPCRN(regnr, 18, "18"), \ | 656 | MSTPCR("keysc0", "r_clk", 2, 14), |
654 | DECLARE_MSTPCRN(regnr, 17, "17"), \ | 657 | MSTPCR("usbf0", "peripheral_clk", 2, 11), |
655 | DECLARE_MSTPCRN(regnr, 16, "16"), \ | 658 | MSTPCR("2dg0", "bus_clk", 2, 9), |
656 | DECLARE_MSTPCRN(regnr, 15, "15"), \ | 659 | MSTPCR("siu0", "bus_clk", 2, 8), |
657 | DECLARE_MSTPCRN(regnr, 14, "14"), \ | 660 | MSTPCR("vou0", "bus_clk", 2, 5), |
658 | DECLARE_MSTPCRN(regnr, 13, "13"), \ | 661 | MSTPCR("jpu0", "bus_clk", 2, 6), |
659 | DECLARE_MSTPCRN(regnr, 12, "12"), \ | 662 | MSTPCR("beu0", "bus_clk", 2, 4), |
660 | DECLARE_MSTPCRN(regnr, 11, "11"), \ | 663 | MSTPCR("ceu0", "bus_clk", 2, 3), |
661 | DECLARE_MSTPCRN(regnr, 10, "10"), \ | 664 | MSTPCR("veu0", "bus_clk", 2, 2), |
662 | DECLARE_MSTPCRN(regnr, 9, "09"), \ | 665 | MSTPCR("vpu0", "bus_clk", 2, 1), |
663 | DECLARE_MSTPCRN(regnr, 8, "08"), \ | 666 | MSTPCR("lcdc0", "bus_clk", 2, 0), |
664 | DECLARE_MSTPCRN(regnr, 7, "07"), \ | 667 | #endif |
665 | DECLARE_MSTPCRN(regnr, 6, "06"), \ | 668 | #if defined(CONFIG_CPU_SUBTYPE_SH7723) |
666 | DECLARE_MSTPCRN(regnr, 5, "05"), \ | 669 | /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ |
667 | DECLARE_MSTPCRN(regnr, 4, "04"), \ | 670 | MSTPCR("tlb0", "cpu_clk", 0, 31), |
668 | DECLARE_MSTPCRN(regnr, 3, "03"), \ | 671 | MSTPCR("ic0", "cpu_clk", 0, 30), |
669 | DECLARE_MSTPCRN(regnr, 2, "02"), \ | 672 | MSTPCR("oc0", "cpu_clk", 0, 29), |
670 | DECLARE_MSTPCRN(regnr, 1, "01"), \ | 673 | MSTPCR("l2c0", "sh_clk", 0, 28), |
671 | DECLARE_MSTPCRN(regnr, 0, "00") | 674 | MSTPCR("ilmem0", "cpu_clk", 0, 27), |
672 | 675 | MSTPCR("fpu0", "cpu_clk", 0, 24), | |
673 | static struct clk sh7722_mstpcr[] = { | 676 | MSTPCR("intc0", "cpu_clk", 0, 22), |
674 | DECLARE_MSTPCR(0), | 677 | MSTPCR("dmac0", "bus_clk", 0, 21), |
675 | DECLARE_MSTPCR(1), | 678 | MSTPCR("sh0", "sh_clk", 0, 20), |
676 | DECLARE_MSTPCR(2), | 679 | MSTPCR("hudi0", "peripheral_clk", 0, 19), |
680 | MSTPCR("ubc0", "cpu_clk", 0, 17), | ||
681 | MSTPCR("tmu0", "peripheral_clk", 0, 15), | ||
682 | MSTPCR("cmt0", "r_clk", 0, 14), | ||
683 | MSTPCR("rwdt0", "r_clk", 0, 13), | ||
684 | MSTPCR("dmac1", "bus_clk", 0, 12), | ||
685 | MSTPCR("tmu1", "peripheral_clk", 0, 11), | ||
686 | MSTPCR("flctl0", "peripheral_clk", 0, 10), | ||
687 | MSTPCR("scif0", "peripheral_clk", 0, 9), | ||
688 | MSTPCR("scif1", "peripheral_clk", 0, 8), | ||
689 | MSTPCR("scif2", "peripheral_clk", 0, 7), | ||
690 | MSTPCR("scif3", "bus_clk", 0, 6), | ||
691 | MSTPCR("scif4", "bus_clk", 0, 5), | ||
692 | MSTPCR("scif5", "bus_clk", 0, 4), | ||
693 | MSTPCR("msiof0", "bus_clk", 0, 2), | ||
694 | MSTPCR("msiof1", "bus_clk", 0, 1), | ||
695 | MSTPCR("meram0", "sh_clk", 0, 0), | ||
696 | MSTPCR("i2c0", "peripheral_clk", 1, 9), | ||
697 | MSTPCR("rtc0", "r_clk", 1, 8), | ||
698 | MSTPCR("atapi0", "sh_clk", 2, 28), | ||
699 | MSTPCR("adc0", "peripheral_clk", 2, 28), | ||
700 | MSTPCR("tpu0", "bus_clk", 2, 25), | ||
701 | MSTPCR("irda0", "peripheral_clk", 2, 24), | ||
702 | MSTPCR("tsif0", "bus_clk", 2, 22), | ||
703 | MSTPCR("icb0", "bus_clk", 2, 21), | ||
704 | MSTPCR("sdhi0", "bus_clk", 2, 18), | ||
705 | MSTPCR("sdhi1", "bus_clk", 2, 17), | ||
706 | MSTPCR("keysc0", "r_clk", 2, 14), | ||
707 | MSTPCR("usb0", "bus_clk", 2, 11), | ||
708 | MSTPCR("2dg0", "bus_clk", 2, 10), | ||
709 | MSTPCR("siu0", "bus_clk", 2, 8), | ||
710 | MSTPCR("veu1", "bus_clk", 2, 6), | ||
711 | MSTPCR("vou0", "bus_clk", 2, 5), | ||
712 | MSTPCR("beu0", "bus_clk", 2, 4), | ||
713 | MSTPCR("ceu0", "bus_clk", 2, 3), | ||
714 | MSTPCR("veu0", "bus_clk", 2, 2), | ||
715 | MSTPCR("vpu0", "bus_clk", 2, 1), | ||
716 | MSTPCR("lcdc0", "bus_clk", 2, 0), | ||
717 | #endif | ||
718 | #if defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
719 | MSTPCR("uram0", "umem_clk", 0, 28), | ||
720 | MSTPCR("xymem0", "bus_clk", 0, 26), | ||
721 | MSTPCR("tmu0", "peripheral_clk", 0, 15), | ||
722 | MSTPCR("cmt0", "r_clk", 0, 14), | ||
723 | MSTPCR("rwdt0", "r_clk", 0, 13), | ||
724 | MSTPCR("scif0", "peripheral_clk", 0, 7), | ||
725 | MSTPCR("scif1", "peripheral_clk", 0, 6), | ||
726 | MSTPCR("scif2", "peripheral_clk", 0, 5), | ||
727 | MSTPCR("scif3", "peripheral_clk", 0, 4), | ||
728 | MSTPCR("i2c0", "peripheral_clk", 1, 9), | ||
729 | MSTPCR("i2c1", "peripheral_clk", 1, 8), | ||
730 | MSTPCR("sdhi0", "peripheral_clk", 2, 18), | ||
731 | MSTPCR("keysc0", "r_clk", 2, 14), | ||
732 | MSTPCR("usbf0", "peripheral_clk", 2, 11), | ||
733 | MSTPCR("siu0", "bus_clk", 2, 8), | ||
734 | MSTPCR("jpu0", "bus_clk", 2, 6), | ||
735 | MSTPCR("vou0", "bus_clk", 2, 5), | ||
736 | MSTPCR("beu0", "bus_clk", 2, 4), | ||
737 | MSTPCR("ceu0", "bus_clk", 2, 3), | ||
738 | MSTPCR("veu0", "bus_clk", 2, 2), | ||
739 | MSTPCR("vpu0", "bus_clk", 2, 1), | ||
740 | MSTPCR("lcdc0", "bus_clk", 2, 0), | ||
741 | #endif | ||
742 | #if defined(CONFIG_CPU_SUBTYPE_SH7366) | ||
743 | /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ | ||
744 | MSTPCR("tlb0", "cpu_clk", 0, 31), | ||
745 | MSTPCR("ic0", "cpu_clk", 0, 30), | ||
746 | MSTPCR("oc0", "cpu_clk", 0, 29), | ||
747 | MSTPCR("rsmem0", "sh_clk", 0, 28), | ||
748 | MSTPCR("xymem0", "cpu_clk", 0, 26), | ||
749 | MSTPCR("intc30", "peripheral_clk", 0, 23), | ||
750 | MSTPCR("intc0", "peripheral_clk", 0, 22), | ||
751 | MSTPCR("dmac0", "bus_clk", 0, 21), | ||
752 | MSTPCR("sh0", "sh_clk", 0, 20), | ||
753 | MSTPCR("hudi0", "peripheral_clk", 0, 19), | ||
754 | MSTPCR("ubc0", "cpu_clk", 0, 17), | ||
755 | MSTPCR("tmu0", "peripheral_clk", 0, 15), | ||
756 | MSTPCR("cmt0", "r_clk", 0, 14), | ||
757 | MSTPCR("rwdt0", "r_clk", 0, 13), | ||
758 | MSTPCR("flctl0", "peripheral_clk", 0, 10), | ||
759 | MSTPCR("scif0", "peripheral_clk", 0, 7), | ||
760 | MSTPCR("scif1", "bus_clk", 0, 6), | ||
761 | MSTPCR("scif2", "bus_clk", 0, 5), | ||
762 | MSTPCR("msiof0", "peripheral_clk", 0, 2), | ||
763 | MSTPCR("sbr0", "peripheral_clk", 0, 1), | ||
764 | MSTPCR("i2c0", "peripheral_clk", 1, 9), | ||
765 | MSTPCR("icb0", "bus_clk", 2, 27), | ||
766 | MSTPCR("meram0", "sh_clk", 2, 26), | ||
767 | MSTPCR("dacc0", "peripheral_clk", 2, 24), | ||
768 | MSTPCR("dacy0", "peripheral_clk", 2, 23), | ||
769 | MSTPCR("tsif0", "bus_clk", 2, 22), | ||
770 | MSTPCR("sdhi0", "bus_clk", 2, 18), | ||
771 | MSTPCR("mmcif0", "bus_clk", 2, 17), | ||
772 | MSTPCR("usb0", "bus_clk", 2, 11), | ||
773 | MSTPCR("siu0", "bus_clk", 2, 8), | ||
774 | MSTPCR("veu1", "bus_clk", 2, 7), | ||
775 | MSTPCR("vou0", "bus_clk", 2, 5), | ||
776 | MSTPCR("beu0", "bus_clk", 2, 4), | ||
777 | MSTPCR("ceu0", "bus_clk", 2, 3), | ||
778 | MSTPCR("veu0", "bus_clk", 2, 2), | ||
779 | MSTPCR("vpu0", "bus_clk", 2, 1), | ||
780 | MSTPCR("lcdc0", "bus_clk", 2, 0), | ||
781 | #endif | ||
677 | }; | 782 | }; |
678 | 783 | ||
679 | static struct clk *sh7722_clocks[] = { | 784 | static struct clk *sh7722_clocks[] = { |
@@ -710,21 +815,30 @@ arch_init_clk_ops(struct clk_ops **ops, int type) | |||
710 | 815 | ||
711 | int __init arch_clk_init(void) | 816 | int __init arch_clk_init(void) |
712 | { | 817 | { |
713 | struct clk *master; | 818 | struct clk *clk; |
714 | int i; | 819 | int i; |
715 | 820 | ||
716 | master = clk_get(NULL, "master_clk"); | 821 | clk = clk_get(NULL, "master_clk"); |
717 | for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { | 822 | for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { |
718 | pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); | 823 | pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); |
719 | sh7722_clocks[i]->parent = master; | 824 | sh7722_clocks[i]->parent = clk; |
720 | clk_register(sh7722_clocks[i]); | 825 | clk_register(sh7722_clocks[i]); |
721 | } | 826 | } |
722 | clk_put(master); | 827 | clk_put(clk); |
723 | 828 | ||
724 | for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) { | 829 | clk_register(&sh7722_r_clock); |
725 | pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name); | 830 | |
726 | clk_register(&sh7722_mstpcr[i]); | 831 | for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) { |
832 | pr_debug( "Registering mstpcr clock '%s'\n", | ||
833 | sh7722_mstpcr_clocks[i].name); | ||
834 | clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops); | ||
835 | sh7722_mstpcr_clocks[i].parent = clk; | ||
836 | sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops; | ||
837 | clk_register(&sh7722_mstpcr_clocks[i]); | ||
838 | clk_put(clk); | ||
727 | } | 839 | } |
728 | 840 | ||
841 | clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */ | ||
842 | |||
729 | return 0; | 843 | return 0; |
730 | } | 844 | } |