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-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c200
1 files changed, 145 insertions, 55 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 13228489337..84e5629fa84 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7710 Setup 2 * SH3 Setup code for SH7710, SH7712
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006, 2007 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -10,8 +10,140 @@
10 */ 10 */
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h>
13#include <linux/serial.h> 14#include <linux/serial.h>
14#include <asm/sci.h> 15#include <asm/sci.h>
16#include <asm/rtc.h>
17
18enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
26 DMAC_DEI4, DMAC_DEI5,
27 IPSEC,
28 EDMAC0, EDMAC1, EDMAC2,
29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
31 TMU0, TMU1, TMU2,
32 RTC_ATI, RTC_PRI, RTC_CUI,
33 WDT,
34 REF,
35
36 /* interrupt groups */
37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
38};
39
40static struct intc_vect vectors[] __initdata = {
41 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
49#ifdef CONFIG_CPU_SUBTYPE_SH7710
50 INTC_VECT(IPSEC, 0xbe0),
51#endif
52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
53 INTC_VECT(EDMAC2, 0xc40),
54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
59 INTC_VECT(TMU2, 0x440),
60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
61 INTC_VECT(RTC_CUI, 0x4c0),
62 INTC_VECT(WDT, 0x560),
63 INTC_VECT(REF, 0x580),
64};
65
66static struct intc_group groups[] __initdata = {
67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
74};
75
76static struct intc_prio priorities[] __initdata = {
77 INTC_PRIO(DMAC1, 7),
78 INTC_PRIO(DMAC2, 7),
79 INTC_PRIO(SCIF0, 3),
80 INTC_PRIO(SCIF1, 3),
81 INTC_PRIO(SIOF0, 3),
82 INTC_PRIO(SIOF1, 3),
83 INTC_PRIO(EDMAC0, 5),
84 INTC_PRIO(EDMAC1, 5),
85 INTC_PRIO(EDMAC2, 5),
86};
87
88static struct intc_prio_reg prio_registers[] __initdata = {
89 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
90 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
91 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
92 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
93 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
94 { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
95#ifdef CONFIG_CPU_SUBTYPE_SH7710
96 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
97#endif
98 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
99 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
100 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
101};
102
103static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
104 priorities, NULL, prio_registers, NULL);
105
106static struct intc_vect vectors_irq[] __initdata = {
107 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
108 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
109};
110
111static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
112 priorities, NULL, prio_registers, NULL);
113
114static struct resource rtc_resources[] = {
115 [0] = {
116 .start = 0xa413fec0,
117 .end = 0xa413fec0 + 0x1e,
118 .flags = IORESOURCE_IO,
119 },
120 [1] = {
121 .start = 20,
122 .flags = IORESOURCE_IRQ,
123 },
124 [2] = {
125 .start = 21,
126 .flags = IORESOURCE_IRQ,
127 },
128 [3] = {
129 .start = 22,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct sh_rtc_platform_info rtc_info = {
135 .capabilities = RTC_CAP_4_DIGIT_YEAR,
136};
137
138static struct platform_device rtc_device = {
139 .name = "sh-rtc",
140 .id = -1,
141 .num_resources = ARRAY_SIZE(rtc_resources),
142 .resource = rtc_resources,
143 .dev = {
144 .platform_data = &rtc_info,
145 },
146};
15 147
16static struct plat_sci_port sci_platform_data[] = { 148static struct plat_sci_port sci_platform_data[] = {
17 { 149 {
@@ -20,7 +152,7 @@ static struct plat_sci_port sci_platform_data[] = {
20 .type = PORT_SCIF, 152 .type = PORT_SCIF,
21 .irqs = { 52, 53, 55, 54 }, 153 .irqs = { 52, 53, 55, 54 },
22 }, { 154 }, {
23 .mapbase = 0xa4420000, 155 .mapbase = 0xa4410000,
24 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
25 .type = PORT_SCIF, 157 .type = PORT_SCIF,
26 .irqs = { 56, 57, 59, 58 }, 158 .irqs = { 56, 57, 59, 58 },
@@ -40,6 +172,7 @@ static struct platform_device sci_device = {
40 172
41static struct platform_device *sh7710_devices[] __initdata = { 173static struct platform_device *sh7710_devices[] __initdata = {
42 &sci_device, 174 &sci_device,
175 &rtc_device,
43}; 176};
44 177
45static int __init sh7710_devices_setup(void) 178static int __init sh7710_devices_setup(void)
@@ -49,59 +182,16 @@ static int __init sh7710_devices_setup(void)
49} 182}
50__initcall(sh7710_devices_setup); 183__initcall(sh7710_devices_setup);
51 184
52static struct ipr_data ipr_irq_table[] = { 185void __init plat_irq_setup_pins(int mode)
53 /* IRQ, IPR-idx, shift, priority */ 186{
54 { 16, 0, 12, 2 }, /* TMU0 TUNI*/ 187 if (mode == IRQ_MODE_IRQ) {
55 { 17, 0, 8, 2 }, /* TMU1 TUNI */ 188 register_intc_controller(&intc_desc_irq);
56 { 18, 0, 4, 2 }, /* TMU2 TUNI */ 189 return;
57 { 27, 1, 12, 2 }, /* WDT ITI */ 190 }
58 { 20, 0, 0, 2 }, /* RTC ATI (alarm) */ 191 BUG();
59 { 21, 0, 0, 2 }, /* RTC PRI (period) */ 192}
60 { 22, 0, 0, 2 }, /* RTC CUI (carry) */
61 { 48, 4, 12, 7 }, /* DMAC DMTE0 */
62 { 49, 4, 12, 7 }, /* DMAC DMTE1 */
63 { 50, 4, 12, 7 }, /* DMAC DMTE2 */
64 { 51, 4, 12, 7 }, /* DMAC DMTE3 */
65 { 52, 4, 8, 3 }, /* SCIF0 ERI */
66 { 53, 4, 8, 3 }, /* SCIF0 RXI */
67 { 54, 4, 8, 3 }, /* SCIF0 BRI */
68 { 55, 4, 8, 3 }, /* SCIF0 TXI */
69 { 56, 4, 4, 3 }, /* SCIF1 ERI */
70 { 57, 4, 4, 3 }, /* SCIF1 RXI */
71 { 58, 4, 4, 3 }, /* SCIF1 BRI */
72 { 59, 4, 4, 3 }, /* SCIF1 TXI */
73 { 76, 5, 8, 7 }, /* DMAC DMTE4 */
74 { 77, 5, 8, 7 }, /* DMAC DMTE5 */
75 { 80, 6, 12, 5 }, /* EDMAC EINT0 */
76 { 81, 6, 8, 5 }, /* EDMAC EINT1 */
77 { 82, 6, 4, 5 }, /* EDMAC EINT2 */
78};
79
80static unsigned long ipr_offsets[] = {
81 0xA414FEE2, /* 0: IPRA */
82 0xA414FEE4, /* 1: IPRB */
83 0xA4140016, /* 2: IPRC */
84 0xA4140018, /* 3: IPRD */
85 0xA414001A, /* 4: IPRE */
86 0xA4080000, /* 5: IPRF */
87 0xA4080002, /* 6: IPRG */
88 0xA4080004, /* 7: IPRH */
89 0xA4080006, /* 8: IPRI */
90};
91
92static struct ipr_desc ipr_irq_desc = {
93 .ipr_offsets = ipr_offsets,
94 .nr_offsets = ARRAY_SIZE(ipr_offsets),
95
96 .ipr_data = ipr_irq_table,
97 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
98
99 .chip = {
100 .name = "IPR-sh7710",
101 },
102};
103 193
104void __init plat_irq_setup(void) 194void __init plat_irq_setup(void)
105{ 195{
106 register_ipr_controller(&ipr_irq_desc); 196 register_intc_controller(&intc_desc);
107} 197}