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Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/dma-sh4a.h')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h62
1 files changed, 0 insertions, 62 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index e734ea47d8a..9647e681fd2 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -8,20 +8,12 @@
8#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 8#define DMAE0_IRQ 78 /* DMA Error IRQ*/
9#define SH_DMAC_BASE0 0xFE008020 9#define SH_DMAC_BASE0 0xFE008020
10#define SH_DMARS_BASE0 0xFE009000 10#define SH_DMARS_BASE0 0xFE009000
11#define CHCR_TS_LOW_MASK 0x00000018
12#define CHCR_TS_LOW_SHIFT 3
13#define CHCR_TS_HIGH_MASK 0
14#define CHCR_TS_HIGH_SHIFT 0
15#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 11#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
16#define DMTE0_IRQ 48 12#define DMTE0_IRQ 48
17#define DMTE4_IRQ 76 13#define DMTE4_IRQ 76
18#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 14#define DMAE0_IRQ 78 /* DMA Error IRQ*/
19#define SH_DMAC_BASE0 0xFE008020 15#define SH_DMAC_BASE0 0xFE008020
20#define SH_DMARS_BASE0 0xFE009000 16#define SH_DMARS_BASE0 0xFE009000
21#define CHCR_TS_LOW_MASK 0x00000018
22#define CHCR_TS_LOW_SHIFT 3
23#define CHCR_TS_HIGH_MASK 0x00300000
24#define CHCR_TS_HIGH_SHIFT 20
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 17#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7764) 18 defined(CONFIG_CPU_SUBTYPE_SH7764)
27#define DMTE0_IRQ 34 19#define DMTE0_IRQ 34
@@ -29,10 +21,6 @@
29#define DMAE0_IRQ 38 21#define DMAE0_IRQ 38
30#define SH_DMAC_BASE0 0xFF608020 22#define SH_DMAC_BASE0 0xFF608020
31#define SH_DMARS_BASE0 0xFF609000 23#define SH_DMARS_BASE0 0xFF609000
32#define CHCR_TS_LOW_MASK 0x00000018
33#define CHCR_TS_LOW_SHIFT 3
34#define CHCR_TS_HIGH_MASK 0
35#define CHCR_TS_HIGH_SHIFT 0
36#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 24#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
37#define DMTE0_IRQ 48 /* DMAC0A*/ 25#define DMTE0_IRQ 48 /* DMAC0A*/
38#define DMTE4_IRQ 76 /* DMAC0B */ 26#define DMTE4_IRQ 76 /* DMAC0B */
@@ -46,10 +34,6 @@
46#define SH_DMAC_BASE0 0xFE008020 34#define SH_DMAC_BASE0 0xFE008020
47#define SH_DMAC_BASE1 0xFDC08020 35#define SH_DMAC_BASE1 0xFDC08020
48#define SH_DMARS_BASE0 0xFDC09000 36#define SH_DMARS_BASE0 0xFDC09000
49#define CHCR_TS_LOW_MASK 0x00000018
50#define CHCR_TS_LOW_SHIFT 3
51#define CHCR_TS_HIGH_MASK 0
52#define CHCR_TS_HIGH_SHIFT 0
53#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 37#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
54#define DMTE0_IRQ 48 /* DMAC0A*/ 38#define DMTE0_IRQ 48 /* DMAC0A*/
55#define DMTE4_IRQ 76 /* DMAC0B */ 39#define DMTE4_IRQ 76 /* DMAC0B */
@@ -64,10 +48,6 @@
64#define SH_DMAC_BASE1 0xFDC08020 48#define SH_DMAC_BASE1 0xFDC08020
65#define SH_DMARS_BASE0 0xFE009000 49#define SH_DMARS_BASE0 0xFE009000
66#define SH_DMARS_BASE1 0xFDC09000 50#define SH_DMARS_BASE1 0xFDC09000
67#define CHCR_TS_LOW_MASK 0x00000018
68#define CHCR_TS_LOW_SHIFT 3
69#define CHCR_TS_HIGH_MASK 0x00600000
70#define CHCR_TS_HIGH_SHIFT 21
71#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 51#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
72#define DMTE0_IRQ 34 52#define DMTE0_IRQ 34
73#define DMTE4_IRQ 44 53#define DMTE4_IRQ 44
@@ -80,10 +60,6 @@
80#define SH_DMAC_BASE0 0xFC808020 60#define SH_DMAC_BASE0 0xFC808020
81#define SH_DMAC_BASE1 0xFC818020 61#define SH_DMAC_BASE1 0xFC818020
82#define SH_DMARS_BASE0 0xFC809000 62#define SH_DMARS_BASE0 0xFC809000
83#define CHCR_TS_LOW_MASK 0x00000018
84#define CHCR_TS_LOW_SHIFT 3
85#define CHCR_TS_HIGH_MASK 0
86#define CHCR_TS_HIGH_SHIFT 0
87#else /* SH7785 */ 63#else /* SH7785 */
88#define DMTE0_IRQ 33 64#define DMTE0_IRQ 33
89#define DMTE4_IRQ 37 65#define DMTE4_IRQ 37
@@ -97,10 +73,6 @@
97#define SH_DMAC_BASE0 0xFC808020 73#define SH_DMAC_BASE0 0xFC808020
98#define SH_DMAC_BASE1 0xFCC08020 74#define SH_DMAC_BASE1 0xFCC08020
99#define SH_DMARS_BASE0 0xFC809000 75#define SH_DMARS_BASE0 0xFC809000
100#define CHCR_TS_LOW_MASK 0x00000018
101#define CHCR_TS_LOW_SHIFT 3
102#define CHCR_TS_HIGH_MASK 0
103#define CHCR_TS_HIGH_SHIFT 0
104#endif 76#endif
105 77
106#define REQ_HE 0x000000C0 78#define REQ_HE 0x000000C0
@@ -108,38 +80,4 @@
108#define REQ_LE 0x00000040 80#define REQ_LE 0x00000040
109#define TM_BURST 0x00000020 81#define TM_BURST 0x00000020
110 82
111/*
112 * The SuperH DMAC supports a number of transmit sizes, we list them here,
113 * with their respective values as they appear in the CHCR registers.
114 *
115 * Defaults to a 64-bit transfer size.
116 */
117enum {
118 XMIT_SZ_8BIT = 0,
119 XMIT_SZ_16BIT = 1,
120 XMIT_SZ_32BIT = 2,
121 XMIT_SZ_64BIT = 7,
122 XMIT_SZ_128BIT = 3,
123 XMIT_SZ_256BIT = 4,
124 XMIT_SZ_128BIT_BLK = 0xb,
125 XMIT_SZ_256BIT_BLK = 0xc,
126};
127
128/*
129 * The DMA count is defined as the number of bytes to transfer.
130 */
131#define TS_SHIFT { \
132 [XMIT_SZ_8BIT] = 0, \
133 [XMIT_SZ_16BIT] = 1, \
134 [XMIT_SZ_32BIT] = 2, \
135 [XMIT_SZ_64BIT] = 3, \
136 [XMIT_SZ_128BIT] = 4, \
137 [XMIT_SZ_256BIT] = 5, \
138 [XMIT_SZ_128BIT_BLK] = 4, \
139 [XMIT_SZ_256BIT_BLK] = 5, \
140}
141
142#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
143 ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
144
145#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ 83#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 07:45:38 -0400