aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ppc/platforms
diff options
context:
space:
mode:
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/4xx/Kconfig23
-rw-r--r--arch/ppc/platforms/4xx/Makefile4
-rw-r--r--arch/ppc/platforms/4xx/virtex-ii_pro.c60
-rw-r--r--arch/ppc/platforms/4xx/virtex-ii_pro.h99
-rw-r--r--arch/ppc/platforms/4xx/virtex.c56
-rw-r--r--arch/ppc/platforms/4xx/virtex.h35
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.c74
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml300.h4
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml403.c177
-rw-r--r--arch/ppc/platforms/4xx/xilinx_ml403.h49
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters.h37
-rw-r--r--arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h243
-rw-r--r--arch/ppc/platforms/Makefile3
-rw-r--r--arch/ppc/platforms/fads.h2
-rw-r--r--arch/ppc/platforms/mpc8272ads_setup.c236
-rw-r--r--arch/ppc/platforms/mpc866ads_setup.c273
-rw-r--r--arch/ppc/platforms/mpc885ads_setup.c389
-rw-r--r--arch/ppc/platforms/pq2ads.h4
-rw-r--r--arch/ppc/platforms/pq2ads_pd.h114
19 files changed, 1690 insertions, 192 deletions
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index d8837911bbc..174ddbc9758 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -57,6 +57,10 @@ config XILINX_ML300
57 help 57 help
58 This option enables support for the Xilinx ML300 evaluation board. 58 This option enables support for the Xilinx ML300 evaluation board.
59 59
60config XILINX_ML403
61 bool "Xilinx-ML403"
62 help
63 This option enables support for the Xilinx ML403 evaluation board.
60endchoice 64endchoice
61 65
62choice 66choice
@@ -172,11 +176,6 @@ config IBM_OCP
172 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT 176 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
173 default y 177 default y
174 178
175config XILINX_OCP
176 bool
177 depends on XILINX_ML300
178 default y
179
180config IBM_EMAC4 179config IBM_EMAC4
181 bool 180 bool
182 depends on 440GX || 440SP || 440SPE 181 depends on 440GX || 440SP || 440SPE
@@ -208,11 +207,21 @@ config 405GPR
208 depends on SYCAMORE 207 depends on SYCAMORE
209 default y 208 default y
210 209
211config VIRTEX_II_PRO 210config XILINX_VIRTEX_II_PRO
212 bool 211 bool
213 depends on XILINX_ML300 212 depends on XILINX_ML300
214 default y 213 default y
215 214
215config XILINX_VIRTEX_4_FX
216 bool
217 depends on XILINX_ML403
218 default y
219
220config XILINX_VIRTEX
221 bool
222 depends on XILINX_VIRTEX_II_PRO || XILINX_VIRTEX_4_FX
223 default y
224
216config STB03xxx 225config STB03xxx
217 bool 226 bool
218 depends on REDWOOD_5 || REDWOOD_6 227 depends on REDWOOD_5 || REDWOOD_6
@@ -220,7 +229,7 @@ config STB03xxx
220 229
221config EMBEDDEDBOOT 230config EMBEDDEDBOOT
222 bool 231 bool
223 depends on EP405 || XILINX_ML300 232 depends on EP405 || XILINX_ML300 || XILINX_ML403
224 default y 233 default y
225 234
226config IBM_OPENBIOS 235config IBM_OPENBIOS
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index c9bb6117095..a04a0d0a0f5 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_REDWOOD_6) += redwood6.o
14obj-$(CONFIG_SYCAMORE) += sycamore.o 14obj-$(CONFIG_SYCAMORE) += sycamore.o
15obj-$(CONFIG_WALNUT) += walnut.o 15obj-$(CONFIG_WALNUT) += walnut.o
16obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o 16obj-$(CONFIG_XILINX_ML300) += xilinx_ml300.o
17obj-$(CONFIG_XILINX_ML403) += xilinx_ml403.o
17 18
18obj-$(CONFIG_405GP) += ibm405gp.o 19obj-$(CONFIG_405GP) += ibm405gp.o
19obj-$(CONFIG_REDWOOD_5) += ibmstb4.o 20obj-$(CONFIG_REDWOOD_5) += ibmstb4.o
@@ -26,4 +27,5 @@ obj-$(CONFIG_440SP) += ibm440sp.o
26obj-$(CONFIG_440SPE) += ppc440spe.o 27obj-$(CONFIG_440SPE) += ppc440spe.o
27obj-$(CONFIG_405EP) += ibm405ep.o 28obj-$(CONFIG_405EP) += ibm405ep.o
28obj-$(CONFIG_405GPR) += ibm405gpr.o 29obj-$(CONFIG_405GPR) += ibm405gpr.o
29obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o 30obj-$(CONFIG_XILINX_VIRTEX) += virtex.o
31
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c b/arch/ppc/platforms/4xx/virtex-ii_pro.c
deleted file mode 100644
index 097cc9d5aca..00000000000
--- a/arch/ppc/platforms/4xx/virtex-ii_pro.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/virtex-ii_pro.c
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is licensed
9 * "as is" without any warranty of any kind, whether express or implied.
10 */
11
12#include <linux/config.h>
13#include <linux/init.h>
14#include <asm/ocp.h>
15#include "virtex-ii_pro.h"
16
17/* Have OCP take care of the serial ports. */
18struct ocp_def core_ocp[] = {
19#ifdef XPAR_UARTNS550_0_BASEADDR
20 { .vendor = OCP_VENDOR_XILINX,
21 .function = OCP_FUNC_16550,
22 .index = 0,
23 .paddr = XPAR_UARTNS550_0_BASEADDR,
24 .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID,
25 .pm = OCP_CPM_NA
26 },
27#ifdef XPAR_UARTNS550_1_BASEADDR
28 { .vendor = OCP_VENDOR_XILINX,
29 .function = OCP_FUNC_16550,
30 .index = 1,
31 .paddr = XPAR_UARTNS550_1_BASEADDR,
32 .irq = XPAR_INTC_0_UARTNS550_1_VEC_ID,
33 .pm = OCP_CPM_NA
34 },
35#ifdef XPAR_UARTNS550_2_BASEADDR
36 { .vendor = OCP_VENDOR_XILINX,
37 .function = OCP_FUNC_16550,
38 .index = 2,
39 .paddr = XPAR_UARTNS550_2_BASEADDR,
40 .irq = XPAR_INTC_0_UARTNS550_2_VEC_ID,
41 .pm = OCP_CPM_NA
42 },
43#ifdef XPAR_UARTNS550_3_BASEADDR
44 { .vendor = OCP_VENDOR_XILINX,
45 .function = OCP_FUNC_16550,
46 .index = 3,
47 .paddr = XPAR_UARTNS550_3_BASEADDR,
48 .irq = XPAR_INTC_0_UARTNS550_3_VEC_ID,
49 .pm = OCP_CPM_NA
50 },
51#ifdef XPAR_UARTNS550_4_BASEADDR
52#error Edit this file to add more devices.
53#endif /* 4 */
54#endif /* 3 */
55#endif /* 2 */
56#endif /* 1 */
57#endif /* 0 */
58 { .vendor = OCP_VENDOR_INVALID
59 }
60};
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h
deleted file mode 100644
index 9014c488733..00000000000
--- a/arch/ppc/platforms/4xx/virtex-ii_pro.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * arch/ppc/platforms/4xx/virtex-ii_pro.h
3 *
4 * Include file that defines the Xilinx Virtex-II Pro processor
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_VIRTEXIIPRO_H__
16#define __ASM_VIRTEXIIPRO_H__
17
18#include <linux/config.h>
19#include <asm/xparameters.h>
20
21/* serial defines */
22
23#define RS_TABLE_SIZE 4 /* change this and add more devices below
24 if you have more then 4 16x50 UARTs */
25
26#define BASE_BAUD (XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16)
27
28/* The serial ports in the Virtex-II Pro have each I/O byte in the
29 * LSByte of a word. This means that iomem_reg_shift needs to be 2 to
30 * change the byte offsets into word offsets. In addition the base
31 * addresses need to have 3 added to them to get to the LSByte.
32 */
33#define STD_UART_OP(num) \
34 { 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \
35 ASYNC_BOOT_AUTOCONF, \
36 .iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \
37 .iomem_reg_shift = 2, \
38 .io_type = SERIAL_IO_MEM},
39
40#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
41#define ML300_UART0 STD_UART_OP(0)
42#else
43#define ML300_UART0
44#endif
45
46#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
47#define ML300_UART1 STD_UART_OP(1)
48#else
49#define ML300_UART1
50#endif
51
52#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
53#define ML300_UART2 STD_UART_OP(2)
54#else
55#define ML300_UART2
56#endif
57
58#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
59#define ML300_UART3 STD_UART_OP(3)
60#else
61#define ML300_UART3
62#endif
63
64#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID)
65#error Edit this file to add more devices.
66#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
67#define NR_SER_PORTS 4
68#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
69#define NR_SER_PORTS 3
70#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
71#define NR_SER_PORTS 2
72#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
73#define NR_SER_PORTS 1
74#else
75#define NR_SER_PORTS 0
76#endif
77
78#if defined(CONFIG_UART0_TTYS0)
79#define SERIAL_PORT_DFNS \
80 ML300_UART0 \
81 ML300_UART1 \
82 ML300_UART2 \
83 ML300_UART3
84#endif
85
86#if defined(CONFIG_UART0_TTYS1)
87#define SERIAL_PORT_DFNS \
88 ML300_UART1 \
89 ML300_UART0 \
90 ML300_UART2 \
91 ML300_UART3
92#endif
93
94#define DCRN_CPMFR_BASE 0
95
96#include <asm/ibm405.h>
97
98#endif /* __ASM_VIRTEXIIPRO_H__ */
99#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex.c b/arch/ppc/platforms/4xx/virtex.c
new file mode 100644
index 00000000000..133a8314719
--- /dev/null
+++ b/arch/ppc/platforms/4xx/virtex.c
@@ -0,0 +1,56 @@
1/*
2 * Virtex-II Pro & Virtex-4 FX common infrastructure
3 *
4 * Maintainer: Grant Likely <grant.likely@secretlab.ca>
5 *
6 * Copyright 2005 Secret Lab Technologies Ltd.
7 * Copyright 2005 General Dynamics Canada Ltd.
8 * Copyright 2005 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/device.h>
19#include <linux/serial_8250.h>
20#include <asm/ppc_sys.h>
21#include <platforms/4xx/virtex.h>
22#include <platforms/4xx/xparameters/xparameters.h>
23
24#define XPAR_UART(num) { \
25 .mapbase = XPAR_UARTNS550_##num##_BASEADDR + 3, \
26 .irq = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \
27 .iotype = UPIO_MEM, \
28 .uartclk = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \
29 .flags = UPF_BOOT_AUTOCONF, \
30 .regshift = 2, \
31 }
32
33struct plat_serial8250_port serial_platform_data[] = {
34#ifdef XPAR_UARTNS550_0_BASEADDR
35 XPAR_UART(0),
36#endif
37#ifdef XPAR_UARTNS550_1_BASEADDR
38 XPAR_UART(1),
39#endif
40#ifdef XPAR_UARTNS550_2_BASEADDR
41 XPAR_UART(2),
42#endif
43#ifdef XPAR_UARTNS550_3_BASEADDR
44 XPAR_UART(3),
45#endif
46 { }, /* terminated by empty record */
47};
48
49struct platform_device ppc_sys_platform_devices[] = {
50 [VIRTEX_UART] = {
51 .name = "serial8250",
52 .id = 0,
53 .dev.platform_data = serial_platform_data,
54 },
55};
56
diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h
new file mode 100644
index 00000000000..1a01b81cff1
--- /dev/null
+++ b/arch/ppc/platforms/4xx/virtex.h
@@ -0,0 +1,35 @@
1/*
2 * arch/ppc/platforms/4xx/virtex.h
3 *
4 * Include file that defines the Xilinx Virtex-II Pro processor
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_VIRTEX_H__
16#define __ASM_VIRTEX_H__
17
18/* serial defines */
19
20#include <asm/ibm405.h>
21
22/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */
23#if !defined(BASE_BAUD)
24 #define BASE_BAUD (0) /* dummy value; not used */
25#endif
26
27/* Device type enumeration for platform bus definitions */
28#ifndef __ASSEMBLY__
29enum ppc_sys_devices {
30 VIRTEX_UART,
31};
32#endif
33
34#endif /* __ASM_VIRTEX_H__ */
35#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
index 0b1b77d986b..267afb50607 100644
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.c
@@ -17,12 +17,14 @@
17#include <linux/tty.h> 17#include <linux/tty.h>
18#include <linux/serial.h> 18#include <linux/serial.h>
19#include <linux/serial_core.h> 19#include <linux/serial_core.h>
20#include <linux/serial_8250.h>
20#include <linux/serialP.h> 21#include <linux/serialP.h>
21#include <asm/io.h> 22#include <asm/io.h>
22#include <asm/machdep.h> 23#include <asm/machdep.h>
23#include <asm/ocp.h> 24#include <asm/ppc_sys.h>
24 25
25#include <platforms/4xx/virtex-ii_pro.h> /* for NR_SER_PORTS */ 26#include <syslib/gen550.h>
27#include <platforms/4xx/xparameters/xparameters.h>
26 28
27/* 29/*
28 * As an overview of how the following functions (platform_init, 30 * As an overview of how the following functions (platform_init,
@@ -54,6 +56,22 @@
54 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c 56 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
55 */ 57 */
56 58
59/* Board specifications structures */
60struct ppc_sys_spec *cur_ppc_sys_spec;
61struct ppc_sys_spec ppc_sys_specs[] = {
62 {
63 /* Only one entry, always assume the same design */
64 .ppc_sys_name = "Xilinx ML300 Reference Design",
65 .mask = 0x00000000,
66 .value = 0x00000000,
67 .num_devices = 1,
68 .device_list = (enum ppc_sys_devices[])
69 {
70 VIRTEX_UART,
71 },
72 },
73};
74
57#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR) 75#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
58 76
59static volatile unsigned *powerdown_base = 77static volatile unsigned *powerdown_base =
@@ -80,28 +98,39 @@ ml300_map_io(void)
80#endif 98#endif
81} 99}
82 100
101/* Early serial support functions */
83static void __init 102static void __init
103ml300_early_serial_init(int num, struct plat_serial8250_port *pdata)
104{
105#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
106 struct uart_port serial_req;
107
108 memset(&serial_req, 0, sizeof(serial_req));
109 serial_req.mapbase = pdata->mapbase;
110 serial_req.membase = pdata->membase;
111 serial_req.irq = pdata->irq;
112 serial_req.uartclk = pdata->uartclk;
113 serial_req.regshift = pdata->regshift;
114 serial_req.iotype = pdata->iotype;
115 serial_req.flags = pdata->flags;
116 gen550_init(num, &serial_req);
117#endif
118}
119
120void __init
84ml300_early_serial_map(void) 121ml300_early_serial_map(void)
85{ 122{
86#ifdef CONFIG_SERIAL_8250 123#ifdef CONFIG_SERIAL_8250
87 struct serial_state old_ports[] = { SERIAL_PORT_DFNS }; 124 struct plat_serial8250_port *pdata;
88 struct uart_port port; 125 int i = 0;
89 int i; 126
90 127 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART);
91 /* Setup ioremapped serial port access */ 128 while(pdata && pdata->flags)
92 for (i = 0; i < ARRAY_SIZE(old_ports); i++ ) { 129 {
93 memset(&port, 0, sizeof(port)); 130 pdata->membase = ioremap(pdata->mapbase, 0x100);
94 port.membase = ioremap((phys_addr_t)(old_ports[i].iomem_base), 16); 131 ml300_early_serial_init(i, pdata);
95 port.irq = old_ports[i].irq; 132 pdata++;
96 port.uartclk = old_ports[i].baud_base * 16; 133 i++;
97 port.regshift = old_ports[i].iomem_reg_shift;
98 port.iotype = SERIAL_IO_MEM;
99 port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
100 port.line = i;
101
102 if (early_serial_setup(&port) != 0) {
103 printk("Early serial init of port %d failed\n", i);
104 }
105 } 134 }
106#endif /* CONFIG_SERIAL_8250 */ 135#endif /* CONFIG_SERIAL_8250 */
107} 136}
@@ -109,9 +138,8 @@ ml300_early_serial_map(void)
109void __init 138void __init
110ml300_setup_arch(void) 139ml300_setup_arch(void)
111{ 140{
112 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
113
114 ml300_early_serial_map(); 141 ml300_early_serial_map();
142 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
115 143
116 /* Identify the system */ 144 /* Identify the system */
117 printk(KERN_INFO "Xilinx Virtex-II Pro port\n"); 145 printk(KERN_INFO "Xilinx Virtex-II Pro port\n");
@@ -131,6 +159,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
131{ 159{
132 ppc4xx_init(r3, r4, r5, r6, r7); 160 ppc4xx_init(r3, r4, r5, r6, r7);
133 161
162 identify_ppc_sys_by_id(mfspr(SPRN_PVR));
163
134 ppc_md.setup_arch = ml300_setup_arch; 164 ppc_md.setup_arch = ml300_setup_arch;
135 ppc_md.setup_io_mappings = ml300_map_io; 165 ppc_md.setup_io_mappings = ml300_map_io;
136 ppc_md.init_IRQ = ml300_init_irq; 166 ppc_md.init_IRQ = ml300_init_irq;
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h
index f8c58841233..ae8bf1353b0 100644
--- a/arch/ppc/platforms/4xx/xilinx_ml300.h
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.h
@@ -16,7 +16,7 @@
16#define __ASM_XILINX_ML300_H__ 16#define __ASM_XILINX_ML300_H__
17 17
18/* ML300 has a Xilinx Virtex-II Pro processor */ 18/* ML300 has a Xilinx Virtex-II Pro processor */
19#include <platforms/4xx/virtex-ii_pro.h> 19#include <platforms/4xx/virtex.h>
20 20
21#ifndef __ASSEMBLY__ 21#ifndef __ASSEMBLY__
22 22
@@ -41,7 +41,7 @@ typedef struct board_info {
41#define PPC4xx_ONB_IO_VADDR 0u 41#define PPC4xx_ONB_IO_VADDR 0u
42#define PPC4xx_ONB_IO_SIZE 0u 42#define PPC4xx_ONB_IO_SIZE 0u
43 43
44#define PPC4xx_MACHINE_NAME "Xilinx ML300" 44#define PPC4xx_MACHINE_NAME "Xilinx ML300 Reference System"
45 45
46#endif /* __ASM_XILINX_ML300_H__ */ 46#endif /* __ASM_XILINX_ML300_H__ */
47#endif /* __KERNEL__ */ 47#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c
new file mode 100644
index 00000000000..4c0c7e4c111
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml403.c
@@ -0,0 +1,177 @@
1/*
2 * arch/ppc/platforms/4xx/xilinx_ml403.c
3 *
4 * Xilinx ML403 evaluation board initialization
5 *
6 * Author: Grant Likely <grant.likely@secretlab.ca>
7 *
8 * 2005 (c) Secret Lab Technologies Ltd.
9 * 2002-2004 (c) MontaVista Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16#include <linux/config.h>
17#include <linux/init.h>
18#include <linux/irq.h>
19#include <linux/tty.h>
20#include <linux/serial.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23#include <linux/serialP.h>
24#include <asm/io.h>
25#include <asm/machdep.h>
26#include <asm/ppc_sys.h>
27
28#include <syslib/gen550.h>
29#include <platforms/4xx/xparameters/xparameters.h>
30
31/*
32 * As an overview of how the following functions (platform_init,
33 * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the
34 * kernel startup procedure, here's a call tree:
35 *
36 * start_here arch/ppc/kernel/head_4xx.S
37 * early_init arch/ppc/kernel/setup.c
38 * machine_init arch/ppc/kernel/setup.c
39 * platform_init this file
40 * ppc4xx_init arch/ppc/syslib/ppc4xx_setup.c
41 * parse_bootinfo
42 * find_bootinfo
43 * "setup some default ppc_md pointers"
44 * MMU_init arch/ppc/mm/init.c
45 * *ppc_md.setup_io_mappings == ml403_map_io this file
46 * ppc4xx_map_io arch/ppc/syslib/ppc4xx_setup.c
47 * start_kernel init/main.c
48 * setup_arch arch/ppc/kernel/setup.c
49 * #if defined(CONFIG_KGDB)
50 * *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
51 * #endif
52 * *ppc_md.setup_arch == ml403_setup_arch this file
53 * ppc4xx_setup_arch arch/ppc/syslib/ppc4xx_setup.c
54 * ppc4xx_find_bridges arch/ppc/syslib/ppc405_pci.c
55 * init_IRQ arch/ppc/kernel/irq.c
56 * *ppc_md.init_IRQ == ml403_init_IRQ this file
57 * ppc4xx_init_IRQ arch/ppc/syslib/ppc4xx_setup.c
58 * ppc4xx_pic_init arch/ppc/syslib/xilinx_pic.c
59 */
60
61/* Board specifications structures */
62struct ppc_sys_spec *cur_ppc_sys_spec;
63struct ppc_sys_spec ppc_sys_specs[] = {
64 {
65 /* Only one entry, always assume the same design */
66 .ppc_sys_name = "Xilinx ML403 Reference Design",
67 .mask = 0x00000000,
68 .value = 0x00000000,
69 .num_devices = 1,
70 .device_list = (enum ppc_sys_devices[])
71 {
72 VIRTEX_UART,
73 },
74 },
75};
76
77#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
78
79static volatile unsigned *powerdown_base =
80 (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
81
82static void
83xilinx_power_off(void)
84{
85 local_irq_disable();
86 out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
87 while (1) ;
88}
89#endif
90
91void __init
92ml403_map_io(void)
93{
94 ppc4xx_map_io();
95
96#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
97 powerdown_base = ioremap((unsigned long) powerdown_base,
98 XPAR_POWER_0_POWERDOWN_HIGHADDR -
99 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
100#endif
101}
102
103/* Early serial support functions */
104static void __init
105ml403_early_serial_init(int num, struct plat_serial8250_port *pdata)
106{
107#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
108 struct uart_port serial_req;
109
110 memset(&serial_req, 0, sizeof(serial_req));
111 serial_req.mapbase = pdata->mapbase;
112 serial_req.membase = pdata->membase;
113 serial_req.irq = pdata->irq;
114 serial_req.uartclk = pdata->uartclk;
115 serial_req.regshift = pdata->regshift;
116 serial_req.iotype = pdata->iotype;
117 serial_req.flags = pdata->flags;
118 gen550_init(num, &serial_req);
119#endif
120}
121
122void __init
123ml403_early_serial_map(void)
124{
125#ifdef CONFIG_SERIAL_8250
126 struct plat_serial8250_port *pdata;
127 int i = 0;
128
129 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART);
130 while(pdata && pdata->flags)
131 {
132 pdata->membase = ioremap(pdata->mapbase, 0x100);
133 ml403_early_serial_init(i, pdata);
134 pdata++;
135 i++;
136 }
137#endif /* CONFIG_SERIAL_8250 */
138}
139
140void __init
141ml403_setup_arch(void)
142{
143 ml403_early_serial_map();
144 ppc4xx_setup_arch(); /* calls ppc4xx_find_bridges() */
145
146 /* Identify the system */
147 printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n");
148}
149
150/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
151void __init
152ml403_init_irq(void)
153{
154 ppc4xx_init_IRQ();
155}
156
157void __init
158platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
159 unsigned long r6, unsigned long r7)
160{
161 ppc4xx_init(r3, r4, r5, r6, r7);
162
163 identify_ppc_sys_by_id(mfspr(SPRN_PVR));
164
165 ppc_md.setup_arch = ml403_setup_arch;
166 ppc_md.setup_io_mappings = ml403_map_io;
167 ppc_md.init_IRQ = ml403_init_irq;
168
169#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
170 ppc_md.power_off = xilinx_power_off;
171#endif
172
173#ifdef CONFIG_KGDB
174 ppc_md.early_serial_map = ml403_early_serial_map;
175#endif
176}
177
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.h b/arch/ppc/platforms/4xx/xilinx_ml403.h
new file mode 100644
index 00000000000..47359695990
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml403.h
@@ -0,0 +1,49 @@
1/*
2 * arch/ppc/platforms/4xx/xilinx_ml403.h
3 *
4 * Include file that defines the Xilinx ML403 reference design
5 *
6 * Author: Grant Likely <grant.likely@secretlab.ca>
7 *
8 * 2005 (c) Secret Lab Technologies Ltd.
9 * 2002-2004 (c) MontaVista Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_XILINX_ML403_H__
18#define __ASM_XILINX_ML403_H__
19
20/* ML403 has a Xilinx Virtex-4 FPGA with a PPC405 hard core */
21#include <platforms/4xx/virtex.h>
22
23#ifndef __ASSEMBLY__
24
25#include <linux/types.h>
26
27typedef struct board_info {
28 unsigned int bi_memsize; /* DRAM installed, in bytes */
29 unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */
30 unsigned int bi_intfreq; /* Processor speed, in Hz */
31 unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
32 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
33} bd_t;
34
35/* Some 4xx parts use a different timebase frequency from the internal clock.
36*/
37#define bi_tbfreq bi_intfreq
38
39#endif /* !__ASSEMBLY__ */
40
41/* We don't need anything mapped. Size of zero will accomplish that. */
42#define PPC4xx_ONB_IO_PADDR 0u
43#define PPC4xx_ONB_IO_VADDR 0u
44#define PPC4xx_ONB_IO_SIZE 0u
45
46#define PPC4xx_MACHINE_NAME "Xilinx ML403 Reference Design"
47
48#endif /* __ASM_XILINX_ML403_H__ */
49#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
new file mode 100644
index 00000000000..4cf21f25635
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-ppc/xparameters.h
3 *
4 * This file includes the correct xparameters.h for the CONFIG'ed board plus
5 * fixups to translate board specific XPAR values to a common set of names
6 *
7 * Author: MontaVista Software, Inc.
8 * source@mvista.com
9 *
10 * 2004 (c) MontaVista Software, Inc. This file is licensed under the terms
11 * of the GNU General Public License version 2. This program is licensed
12 * "as is" without any warranty of any kind, whether express or implied.
13 */
14
15#include <linux/config.h>
16
17#if defined(CONFIG_XILINX_ML300)
18 #include "xparameters_ml300.h"
19#elif defined(CONFIG_XILINX_ML403)
20 #include "xparameters_ml403.h"
21#else
22 /* Add other board xparameter includes here before the #else */
23 #error No xparameters_*.h file included
24#endif
25
26#ifndef SERIAL_PORT_DFNS
27 /* zImage serial port definitions */
28 #define RS_TABLE_SIZE 1
29 #define SERIAL_PORT_DFNS { \
30 .baud_base = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16, \
31 .irq = XPAR_INTC_0_UARTNS550_0_VEC_ID, \
32 .flags = ASYNC_BOOT_AUTOCONF, \
33 .iomem_base = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3, \
34 .iomem_reg_shift = 2, \
35 .io_type = SERIAL_IO_MEM, \
36 },
37#endif
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
new file mode 100644
index 00000000000..5cacdcb3964
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
@@ -0,0 +1,243 @@
1
2/*******************************************************************
3*
4* CAUTION: This file is automatically generated by libgen.
5* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
6* DO NOT EDIT.
7*
8* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
9*
10* Description: Driver parameters
11*
12*******************************************************************/
13
14#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
15#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
16
17/******************************************************************/
18
19#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
20#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
21#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
22#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
23#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
24#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
25#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
26#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
27#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
28#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
29
30/******************************************************************/
31
32#define XPAR_XEMAC_NUM_INSTANCES 1
33#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
34#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
35#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
36#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
37#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
38#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
39
40/******************************************************************/
41
42#define XPAR_XUARTNS550_NUM_INSTANCES 1
43#define XPAR_XUARTNS550_CLOCK_HZ 100000000
44#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
45#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
46#define XPAR_OPB_UART16550_0_DEVICE_ID 0
47
48/******************************************************************/
49
50#define XPAR_XGPIO_NUM_INSTANCES 3
51#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
52#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
53#define XPAR_OPB_GPIO_0_DEVICE_ID 0
54#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
55#define XPAR_OPB_GPIO_0_IS_DUAL 1
56#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
57#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
58#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
59#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
60#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
61#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
62#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
63#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
64#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
65#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
66
67/******************************************************************/
68
69#define XPAR_XPS2_NUM_INSTANCES 2
70#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
71#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
72#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
73#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
74#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
75#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
76
77/******************************************************************/
78
79#define XPAR_XIIC_NUM_INSTANCES 1
80#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
81#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
82#define XPAR_OPB_IIC_0_DEVICE_ID 0
83#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
84#define XPAR_OPB_IIC_0_GPO_WIDTH 1
85
86/******************************************************************/
87
88#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
89#define XPAR_XINTC_HAS_IPR 1
90#define XPAR_XINTC_USE_DCR 0
91#define XPAR_XINTC_NUM_INSTANCES 1
92#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
93#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
94#define XPAR_OPB_INTC_0_DEVICE_ID 0
95#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
96
97/******************************************************************/
98
99#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
100#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
101#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
102#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
103#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
104#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
105#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
106#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
107#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
108#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
109#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
110#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
111#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
112#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
113#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
114#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
115#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
116#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
117#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
118#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
119#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
120#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
121#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
122
123/******************************************************************/
124
125#define XPAR_XTFT_NUM_INSTANCES 1
126#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
127#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
128#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
129
130/******************************************************************/
131
132#define XPAR_XSYSACE_MEM_WIDTH 16
133#define XPAR_XSYSACE_NUM_INSTANCES 1
134#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
135#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
136#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
137#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
138
139/******************************************************************/
140
141#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
142
143/******************************************************************/
144
145
146/******************************************************************/
147
148/* Linux Redefines */
149
150/******************************************************************/
151
152#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
153#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
154#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
155#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
156
157/******************************************************************/
158
159#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
160#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
161#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
162#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
163
164/******************************************************************/
165
166#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
167#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
168#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
169#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
170#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
171#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
172
173/******************************************************************/
174
175#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
176
177/******************************************************************/
178
179#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
180#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
181#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
182#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
183#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
184#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
185
186/******************************************************************/
187
188#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
189#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
190#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
191#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
192#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
193#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
194#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
195#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
196#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
197#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
198#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
199#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
200#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
201#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
202#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
203
204/******************************************************************/
205
206#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
207#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
208#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
209#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
210#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
211#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
212
213/******************************************************************/
214
215#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
216#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
217#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
218
219/******************************************************************/
220
221#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
222#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
223#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
224#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
225
226/******************************************************************/
227
228#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
229#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
230#define XPAR_DDR_0_SIZE 0x4000000
231
232/******************************************************************/
233
234#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
235#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
236#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
237
238/******************************************************************/
239
240#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
241
242/******************************************************************/
243
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 51430e294b3..e8b91a33ce9 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
37obj-$(CONFIG_SPRUCE) += spruce.o 37obj-$(CONFIG_SPRUCE) += spruce.o
38obj-$(CONFIG_LITE5200) += lite5200.o 38obj-$(CONFIG_LITE5200) += lite5200.o
39obj-$(CONFIG_EV64360) += ev64360.o 39obj-$(CONFIG_EV64360) += ev64360.o
40obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
41obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
42obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
40 43
41ifeq ($(CONFIG_SMP),y) 44ifeq ($(CONFIG_SMP),y)
42obj-$(CONFIG_PPC_CHRP) += chrp_smp.o 45obj-$(CONFIG_PPC_CHRP) += chrp_smp.o
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
index a48fb8d723e..e1c0b1b6dcb 100644
--- a/arch/ppc/platforms/fads.h
+++ b/arch/ppc/platforms/fads.h
@@ -112,7 +112,7 @@
112 112
113/* CPM Ethernet through SCC1 or SCC2 */ 113/* CPM Ethernet through SCC1 or SCC2 */
114 114
115#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */ 115#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */
116/* Bits in parallel I/O port registers that have to be set/cleared 116/* Bits in parallel I/O port registers that have to be set/cleared
117 * to configure the pins for SCC1 use. 117 * to configure the pins for SCC1 use.
118 * TCLK - CLK1, RCLK - CLK2. 118 * TCLK - CLK1, RCLK - CLK2.
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c
new file mode 100644
index 00000000000..bc9b94f77e3
--- /dev/null
+++ b/arch/ppc/platforms/mpc8272ads_setup.c
@@ -0,0 +1,236 @@
1/*
2 * arch/ppc/platforms/82xx/pq2ads_pd.c
3 *
4 * MPC82xx Board-specific PlatformDevice descriptions
5 *
6 * 2005 (c) MontaVista Software, Inc.
7 * Vitaly Bordug <vbordug@ru.mvista.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/device.h>
18#include <linux/ioport.h>
19#include <linux/fs_enet_pd.h>
20#include <linux/platform_device.h>
21
22#include <asm/io.h>
23#include <asm/mpc8260.h>
24#include <asm/cpm2.h>
25#include <asm/immap_cpm2.h>
26#include <asm/irq.h>
27#include <asm/ppc_sys.h>
28#include <asm/ppcboot.h>
29
30#include "pq2ads_pd.h"
31
32static void init_fcc1_ioports(void);
33static void init_fcc2_ioports(void);
34
35static struct fs_mii_bus_info mii_bus_info = {
36 .method = fsmii_bitbang,
37 .id = 0,
38 .i.bitbang = {
39 .mdio_port = fsiop_portc,
40 .mdio_bit = 18,
41 .mdc_port = fsiop_portc,
42 .mdc_bit = 19,
43 .delay = 1,
44 },
45};
46
47static struct fs_platform_info mpc82xx_fcc1_pdata = {
48 .fs_no = fsid_fcc1,
49 .cp_page = CPM_CR_FCC1_PAGE,
50 .cp_block = CPM_CR_FCC1_SBLOCK,
51 .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
52 .clk_route = CMX1_CLK_ROUTE,
53 .clk_mask = CMX1_CLK_MASK,
54 .init_ioports = init_fcc1_ioports,
55
56 .phy_addr = 0,
57#ifdef PHY_INTERRUPT
58 .phy_irq = PHY_INTERRUPT,
59#else
60 .phy_irq = -1;
61#endif
62 .mem_offset = FCC1_MEM_OFFSET,
63 .bus_info = &mii_bus_info,
64 .rx_ring = 32,
65 .tx_ring = 32,
66 .rx_copybreak = 240,
67 .use_napi = 0,
68 .napi_weight = 17,
69};
70
71static struct fs_platform_info mpc82xx_fcc2_pdata = {
72 .fs_no = fsid_fcc2,
73 .cp_page = CPM_CR_FCC2_PAGE,
74 .cp_block = CPM_CR_FCC2_SBLOCK,
75 .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
76 .clk_route = CMX2_CLK_ROUTE,
77 .clk_mask = CMX2_CLK_MASK,
78 .init_ioports = init_fcc2_ioports,
79
80 .phy_addr = 3,
81#ifdef PHY_INTERRUPT
82 .phy_irq = PHY_INTERRUPT,
83#else
84 .phy_irq = -1;
85#endif
86 .mem_offset = FCC2_MEM_OFFSET,
87 .bus_info = &mii_bus_info,
88 .rx_ring = 32,
89 .tx_ring = 32,
90 .rx_copybreak = 240,
91 .use_napi = 0,
92 .napi_weight = 17,
93};
94
95static void init_fcc1_ioports(void)
96{
97 struct io_port *io;
98 u32 tempval;
99 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
100 u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
101
102 io = &immap->im_ioport;
103
104 /* Enable the PHY */
105 clrbits32(bcsr, BCSR1_FETHIEN);
106 setbits32(bcsr, BCSR1_FETH_RST);
107
108 /* FCC1 pins are on port A/C. */
109 /* Configure port A and C pins for FCC1 Ethernet. */
110
111 tempval = in_be32(&io->iop_pdira);
112 tempval &= ~PA1_DIRA0;
113 tempval |= PA1_DIRA1;
114 out_be32(&io->iop_pdira, tempval);
115
116 tempval = in_be32(&io->iop_psora);
117 tempval &= ~PA1_PSORA0;
118 tempval |= PA1_PSORA1;
119 out_be32(&io->iop_psora, tempval);
120
121 setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
122
123 /* Alter clocks */
124 tempval = PC_F1TXCLK|PC_F1RXCLK;
125
126 clrbits32(&io->iop_psorc, tempval);
127 clrbits32(&io->iop_pdirc, tempval);
128 setbits32(&io->iop_pparc, tempval);
129
130 clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
131 setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
132 iounmap(bcsr);
133 iounmap(immap);
134}
135
136static void init_fcc2_ioports(void)
137{
138 cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
139 u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
140
141 struct io_port *io;
142 u32 tempval;
143
144 immap = cpm2_immr;
145
146 io = &immap->im_ioport;
147
148 /* Enable the PHY */
149 clrbits32(bcsr, BCSR3_FETHIEN2);
150 setbits32(bcsr, BCSR3_FETH2_RST);
151
152 /* FCC2 are port B/C. */
153 /* Configure port A and C pins for FCC2 Ethernet. */
154
155 tempval = in_be32(&io->iop_pdirb);
156 tempval &= ~PB2_DIRB0;
157 tempval |= PB2_DIRB1;
158 out_be32(&io->iop_pdirb, tempval);
159
160 tempval = in_be32(&io->iop_psorb);
161 tempval &= ~PB2_PSORB0;
162 tempval |= PB2_PSORB1;
163 out_be32(&io->iop_psorb, tempval);
164
165 setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
166
167 tempval = PC_F2RXCLK|PC_F2TXCLK;
168
169 /* Alter clocks */
170 clrbits32(&io->iop_psorc,tempval);
171 clrbits32(&io->iop_pdirc,tempval);
172 setbits32(&io->iop_pparc,tempval);
173
174 clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
175 setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
176
177 iounmap(bcsr);
178 iounmap(immap);
179}
180
181
182static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
183 int idx)
184{
185 bd_t* bi = (void*)__res;
186 int fs_no = fsid_fcc1+pdev->id-1;
187
188 mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
189 mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
190
191 switch(fs_no) {
192 case fsid_fcc1:
193 memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
194 pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
195 break;
196 case fsid_fcc2:
197 memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
198 mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
199 pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
200 break;
201 }
202}
203
204static int mpc8272ads_platform_notify(struct device *dev)
205{
206 static const struct platform_notify_dev_map dev_map[] = {
207 {
208 .bus_id = "fsl-cpm-fcc",
209 .rtn = mpc8272ads_fixup_enet_pdata
210 },
211 {
212 .bus_id = NULL
213 }
214 };
215 platform_notify_map(dev_map,dev);
216
217 return 0;
218
219}
220
221int __init mpc8272ads_init(void)
222{
223 printk(KERN_NOTICE "mpc8272ads: Init\n");
224
225 platform_notify = mpc8272ads_platform_notify;
226
227 ppc_sys_device_initfunc();
228
229 ppc_sys_device_disable_all();
230 ppc_sys_device_enable(MPC82xx_CPM_FCC1);
231 ppc_sys_device_enable(MPC82xx_CPM_FCC2);
232
233 return 0;
234}
235
236arch_initcall(mpc8272ads_init);
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c
new file mode 100644
index 00000000000..ac8fcc68afe
--- /dev/null
+++ b/arch/ppc/platforms/mpc866ads_setup.c
@@ -0,0 +1,273 @@
1/*arch/ppc/platforms/mpc885ads-setup.c
2 *
3 * Platform setup for the Freescale mpc885ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/ioport.h>
20#include <linux/device.h>
21
22#include <linux/fs_enet_pd.h>
23#include <linux/mii.h>
24
25#include <asm/delay.h>
26#include <asm/io.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/processor.h>
30#include <asm/system.h>
31#include <asm/time.h>
32#include <asm/ppcboot.h>
33#include <asm/8xx_immap.h>
34#include <asm/commproc.h>
35#include <asm/ppc_sys.h>
36#include <asm/mpc8xx.h>
37
38extern unsigned char __res[];
39
40static struct fs_mii_bus_info fec_mii_bus_info = {
41 .method = fsmii_fec,
42 .id = 0,
43};
44
45static struct fs_mii_bus_info scc_mii_bus_info = {
46 .method = fsmii_fixed,
47 .id = 0,
48 .i.fixed.speed = 10,
49 .i.fixed.duplex = 0,
50};
51
52static struct fs_platform_info mpc8xx_fec_pdata[] = {
53 {
54 .rx_ring = 128,
55 .tx_ring = 16,
56 .rx_copybreak = 240,
57
58 .use_napi = 1,
59 .napi_weight = 17,
60
61 .phy_addr = 15,
62 .phy_irq = -1,
63
64 .use_rmii = 0,
65
66 .bus_info = &fec_mii_bus_info,
67 }
68};
69
70static struct fs_platform_info mpc8xx_scc_pdata = {
71 .rx_ring = 64,
72 .tx_ring = 8,
73 .rx_copybreak = 240,
74
75 .use_napi = 1,
76 .napi_weight = 17,
77
78 .phy_addr = -1,
79 .phy_irq = -1,
80
81 .bus_info = &scc_mii_bus_info,
82};
83
84void __init board_init(void)
85{
86 volatile cpm8xx_t *cp = cpmp;
87 unsigned *bcsr_io;
88
89 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
90
91 if (bcsr_io == NULL) {
92 printk(KERN_CRIT "Could not remap BCSR1\n");
93 return;
94 }
95#ifdef CONFIG_SERIAL_CPM_SMC1
96 cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
97 clrbits32(bcsr_io,(0x80000000 >> 7));
98#else
99 setbits32(bcsr_io,(0x80000000 >> 7));
100
101 cp->cp_pbpar &= ~(0x000000c0);
102 cp->cp_pbdir |= 0x000000c0;
103 cp->cp_smc[0].smc_smcmr = 0;
104 cp->cp_smc[0].smc_smce = 0;
105#endif
106
107#ifdef CONFIG_SERIAL_CPM_SMC2
108 cp->cp_simode &= ~(0xe0000000 >> 1);
109 cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
110 clrbits32(bcsr_io,(0x80000000 >> 13));
111#else
112 clrbits32(bcsr_io,(0x80000000 >> 13));
113 cp->cp_pbpar &= ~(0x00000c00);
114 cp->cp_pbdir |= 0x00000c00;
115 cp->cp_smc[1].smc_smcmr = 0;
116 cp->cp_smc[1].smc_smce = 0;
117#endif
118 iounmap(bcsr_io);
119}
120
121static void setup_fec1_ioports(void)
122{
123 immap_t *immap = (immap_t *) IMAP_ADDR;
124
125 setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
126 setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
127}
128
129static void setup_scc1_ioports(void)
130{
131 immap_t *immap = (immap_t *) IMAP_ADDR;
132 unsigned *bcsr_io;
133
134 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
135
136 if (bcsr_io == NULL) {
137 printk(KERN_CRIT "Could not remap BCSR1\n");
138 return;
139 }
140
141 /* Enable the PHY.
142 */
143 clrbits32(bcsr_io,BCSR1_ETHEN);
144
145 /* Configure port A pins for Txd and Rxd.
146 */
147 /* Disable receive and transmit in case EPPC-Bug started it.
148 */
149 setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
150 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
151 clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
152
153 /* Configure port C pins to enable CLSN and RENA.
154 */
155 clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
156 clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
157 setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
158 /* Configure port A for TCLK and RCLK.
159 */
160 setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
161 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
162 clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
163 clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
164
165 /* Configure Serial Interface clock routing.
166 * First, clear all SCC bits to zero, then set the ones we want.
167 */
168 clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
169 setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
170
171 /* In the original SCC enet driver the following code is placed at
172 the end of the initialization */
173 setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
174 setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
175
176}
177
178static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
179{
180 struct fs_platform_info *fpi = pdev->dev.platform_data;
181
182 volatile cpm8xx_t *cp;
183 bd_t *bd = (bd_t *) __res;
184 char *e;
185 int i;
186
187 /* Get pointer to Communication Processor */
188 cp = cpmp;
189 switch (fs_no) {
190 case fsid_fec1:
191 fpi = &mpc8xx_fec_pdata[0];
192 fpi->init_ioports = &setup_fec1_ioports;
193
194 break;
195 case fsid_scc1:
196 fpi = &mpc8xx_scc_pdata;
197 fpi->init_ioports = &setup_scc1_ioports;
198
199 break;
200 default:
201 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
202 return;
203 }
204
205 pdev->dev.platform_data = fpi;
206 fpi->fs_no = fs_no;
207
208 e = (unsigned char *)&bd->bi_enetaddr;
209 for (i = 0; i < 6; i++)
210 fpi->macaddr[i] = *e++;
211
212 fpi->macaddr[5 - pdev->id]++;
213
214}
215
216static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
217 int idx)
218{
219 /* This is for FEC devices only */
220 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
221 return;
222 mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
223}
224
225static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
226 int idx)
227{
228 /* This is for SCC devices only */
229 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
230 return;
231
232 mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
233}
234
235static int mpc866ads_platform_notify(struct device *dev)
236{
237 static const struct platform_notify_dev_map dev_map[] = {
238 {
239 .bus_id = "fsl-cpm-fec",
240 .rtn = mpc866ads_fixup_fec_enet_pdata,
241 },
242 {
243 .bus_id = "fsl-cpm-scc",
244 .rtn = mpc866ads_fixup_scc_enet_pdata,
245 },
246 {
247 .bus_id = NULL
248 }
249 };
250
251 platform_notify_map(dev_map,dev);
252
253 return 0;
254}
255
256int __init mpc866ads_init(void)
257{
258 printk(KERN_NOTICE "mpc866ads: Init\n");
259
260 platform_notify = mpc866ads_platform_notify;
261
262 ppc_sys_device_initfunc();
263 ppc_sys_device_disable_all();
264
265#ifdef MPC8xx_SECOND_ETH_SCC1
266 ppc_sys_device_enable(MPC8xx_CPM_SCC1);
267#endif
268 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
269
270 return 0;
271}
272
273arch_initcall(mpc866ads_init);
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
new file mode 100644
index 00000000000..50a99e5f7c6
--- /dev/null
+++ b/arch/ppc/platforms/mpc885ads_setup.c
@@ -0,0 +1,389 @@
1/*arch/ppc/platforms/mpc885ads-setup.c
2 *
3 * Platform setup for the Freescale mpc885ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/param.h>
18#include <linux/string.h>
19#include <linux/ioport.h>
20#include <linux/device.h>
21
22#include <linux/fs_enet_pd.h>
23#include <linux/mii.h>
24
25#include <asm/delay.h>
26#include <asm/io.h>
27#include <asm/machdep.h>
28#include <asm/page.h>
29#include <asm/processor.h>
30#include <asm/system.h>
31#include <asm/time.h>
32#include <asm/ppcboot.h>
33#include <asm/8xx_immap.h>
34#include <asm/commproc.h>
35#include <asm/ppc_sys.h>
36
37extern unsigned char __res[];
38
39static void __init mpc885ads_scc_phy_init(char);
40
41static struct fs_mii_bus_info fec_mii_bus_info = {
42 .method = fsmii_fec,
43 .id = 0,
44};
45
46static struct fs_mii_bus_info scc_mii_bus_info = {
47#ifdef CONFIG_SCC_ENET_8xx_FIXED
48 .method = fsmii_fixed,
49#else
50 .method = fsmii_fec,
51#endif
52
53 .id = 0,
54};
55
56static struct fs_platform_info mpc8xx_fec_pdata[] = {
57 {
58 .rx_ring = 128,
59 .tx_ring = 16,
60 .rx_copybreak = 240,
61
62 .use_napi = 1,
63 .napi_weight = 17,
64
65 .phy_addr = 0,
66 .phy_irq = SIU_IRQ7,
67
68 .bus_info = &fec_mii_bus_info,
69 }, {
70 .rx_ring = 128,
71 .tx_ring = 16,
72 .rx_copybreak = 240,
73
74 .use_napi = 1,
75 .napi_weight = 17,
76
77 .phy_addr = 1,
78 .phy_irq = SIU_IRQ7,
79
80 .bus_info = &fec_mii_bus_info,
81 }
82};
83
84static struct fs_platform_info mpc8xx_scc_pdata = {
85 .rx_ring = 64,
86 .tx_ring = 8,
87 .rx_copybreak = 240,
88
89 .use_napi = 1,
90 .napi_weight = 17,
91
92 .phy_addr = 2,
93#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED
94 .phy_irq = -1,
95#else
96 .phy_irq = SIU_IRQ7,
97#endif
98
99 .bus_info = &scc_mii_bus_info,
100};
101
102void __init board_init(void)
103{
104 volatile cpm8xx_t *cp = cpmp;
105 unsigned int *bcsr_io;
106
107#ifdef CONFIG_FS_ENET
108 immap_t *immap = (immap_t *) IMAP_ADDR;
109#endif
110 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
111
112 if (bcsr_io == NULL) {
113 printk(KERN_CRIT "Could not remap BCSR\n");
114 return;
115 }
116#ifdef CONFIG_SERIAL_CPM_SMC1
117 cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
118 clrbits32(bcsr_io, BCSR1_RS232EN_1);
119#else
120 setbits32(bcsr_io,BCSR1_RS232EN_1);
121 cp->cp_smc[0].smc_smcmr = 0;
122 cp->cp_smc[0].smc_smce = 0;
123#endif
124
125#ifdef CONFIG_SERIAL_CPM_SMC2
126 cp->cp_simode &= ~(0xe0000000 >> 1);
127 cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
128 clrbits32(bcsr_io,BCSR1_RS232EN_2);
129#else
130 setbits32(bcsr_io,BCSR1_RS232EN_2);
131 cp->cp_smc[1].smc_smcmr = 0;
132 cp->cp_smc[1].smc_smce = 0;
133#endif
134 iounmap(bcsr_io);
135
136#ifdef CONFIG_FS_ENET
137 /* use MDC for MII (common) */
138 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
139 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
140#endif
141}
142
143static void setup_fec1_ioports(void)
144{
145 immap_t *immap = (immap_t *) IMAP_ADDR;
146
147 /* configure FEC1 pins */
148 setbits16(&immap->im_ioport.iop_papar, 0xf830);
149 setbits16(&immap->im_ioport.iop_padir, 0x0830);
150 clrbits16(&immap->im_ioport.iop_padir, 0xf000);
151 setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
152
153 clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
154 setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
155 clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
156 setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
157
158 setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
159 clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
160 clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
161}
162
163static void setup_fec2_ioports(void)
164{
165 immap_t *immap = (immap_t *) IMAP_ADDR;
166
167 /* configure FEC2 pins */
168 setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
169 setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
170 setbits32(&immap->im_cpm.cp_peso, 0x00037800);
171 clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
172 clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
173}
174
175static void setup_scc3_ioports(void)
176{
177 immap_t *immap = (immap_t *) IMAP_ADDR;
178 unsigned *bcsr_io;
179
180 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
181
182 if (bcsr_io == NULL) {
183 printk(KERN_CRIT "Could not remap BCSR\n");
184 return;
185 }
186
187 /* Enable the PHY.
188 */
189 setbits32(bcsr_io+4, BCSR4_ETH10_RST);
190 /* Configure port A pins for Txd and Rxd.
191 */
192 setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
193 clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
194
195 /* Configure port C pins to enable CLSN and RENA.
196 */
197 clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
198 clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
199 setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
200
201 /* Configure port E for TCLK and RCLK.
202 */
203 setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
204 clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
205 clrbits32(&immap->im_cpm.cp_pedir,
206 PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
207 clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
208 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
209
210 /* Configure Serial Interface clock routing.
211 * First, clear all SCC bits to zero, then set the ones we want.
212 */
213 clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
214 setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
215
216 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
217 */
218 immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
219 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
220 * by H/W setting after reset. SCC ethernet controller support only half duplex.
221 * This discrepancy of modes causes a lot of carrier lost errors.
222 */
223
224 /* In the original SCC enet driver the following code is placed at
225 the end of the initialization */
226 setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
227 clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
228 setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
229
230 setbits32(bcsr_io+1, BCSR1_ETHEN);
231 iounmap(bcsr_io);
232}
233
234static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
235{
236 struct fs_platform_info *fpi = pdev->dev.platform_data;
237
238 volatile cpm8xx_t *cp;
239 bd_t *bd = (bd_t *) __res;
240 char *e;
241 int i;
242
243 /* Get pointer to Communication Processor */
244 cp = cpmp;
245 switch (fs_no) {
246 case fsid_fec1:
247 fpi = &mpc8xx_fec_pdata[0];
248 fpi->init_ioports = &setup_fec1_ioports;
249 break;
250 case fsid_fec2:
251 fpi = &mpc8xx_fec_pdata[1];
252 fpi->init_ioports = &setup_fec2_ioports;
253 break;
254 case fsid_scc3:
255 fpi = &mpc8xx_scc_pdata;
256 fpi->init_ioports = &setup_scc3_ioports;
257 mpc885ads_scc_phy_init(fpi->phy_addr);
258 break;
259 default:
260 printk(KERN_WARNING"Device %s is not supported!\n", pdev->name);
261 return;
262 }
263
264 pdev->dev.platform_data = fpi;
265 fpi->fs_no = fs_no;
266
267 e = (unsigned char *)&bd->bi_enetaddr;
268 for (i = 0; i < 6; i++)
269 fpi->macaddr[i] = *e++;
270
271 fpi->macaddr[5 - pdev->id]++;
272
273}
274
275static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
276 int idx)
277{
278 /* This is for FEC devices only */
279 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
280 return;
281 mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
282}
283
284static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
285 int idx)
286{
287 /* This is for SCC devices only */
288 if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
289 return;
290
291 mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
292}
293
294/* SCC ethernet controller does not have MII management channel. FEC1 MII
295 * channel is used to communicate with the 10Mbit PHY.
296 */
297
298#define MII_ECNTRL_PINMUX 0x4
299#define FEC_ECNTRL_PINMUX 0x00000004
300#define FEC_RCNTRL_MII_MODE 0x00000004
301
302/* Make MII read/write commands.
303 */
304#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \
305 ((VAL) & 0xffff) | ((PHY_ADDR) << 23))
306
307static void mpc885ads_scc_phy_init(char phy_addr)
308{
309 volatile immap_t *immap;
310 volatile fec_t *fecp;
311 bd_t *bd;
312
313 bd = (bd_t *) __res;
314 immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
315 fecp = &(immap->im_cpm.cp_fec);
316
317 /* Enable MII pins of the FEC1
318 */
319 setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
320 clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
321 /* Set MII speed to 2.5 MHz
322 */
323 out_be32(&fecp->fec_mii_speed,
324 ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
325
326 /* Enable FEC pin MUX
327 */
328 setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
329 setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
330
331 out_be32(&fecp->fec_mii_data,
332 mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
333 udelay(100);
334 out_be32(&fecp->fec_mii_data,
335 mk_mii_write(MII_ADVERTISE,
336 ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));
337 udelay(100);
338
339 /* Disable FEC MII settings
340 */
341 clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
342 clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
343 out_be32(&fecp->fec_mii_speed, 0);
344}
345
346static int mpc885ads_platform_notify(struct device *dev)
347{
348
349 static const struct platform_notify_dev_map dev_map[] = {
350 {
351 .bus_id = "fsl-cpm-fec",
352 .rtn = mpc885ads_fixup_fec_enet_pdata,
353 },
354 {
355 .bus_id = "fsl-cpm-scc",
356 .rtn = mpc885ads_fixup_scc_enet_pdata,
357 },
358 {
359 .bus_id = NULL
360 }
361 };
362
363 platform_notify_map(dev_map,dev);
364
365}
366
367int __init mpc885ads_init(void)
368{
369 printk(KERN_NOTICE "mpc885ads: Init\n");
370
371 platform_notify = mpc885ads_platform_notify;
372
373 ppc_sys_device_initfunc();
374 ppc_sys_device_disable_all();
375
376 ppc_sys_device_enable(MPC8xx_CPM_FEC1);
377
378#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
379 ppc_sys_device_enable(MPC8xx_CPM_SCC1);
380
381#endif
382#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
383 ppc_sys_device_enable(MPC8xx_CPM_FEC2);
384#endif
385
386 return 0;
387}
388
389arch_initcall(mpc885ads_init);
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
index 067d9a5aebc..6b26dd36c64 100644
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -13,6 +13,10 @@
13 13
14#include <asm/ppcboot.h> 14#include <asm/ppcboot.h>
15 15
16#if defined(CONFIG_ADS8272)
17#define BOARD_CHIP_NAME "8272"
18#endif
19
16/* Memory map is configured by the PROM startup. 20/* Memory map is configured by the PROM startup.
17 * We just map a few things we need. The CSR is actually 4 byte-wide 21 * We just map a few things we need. The CSR is actually 4 byte-wide
18 * registers that can be accessed as 8-, 16-, or 32-bit values. 22 * registers that can be accessed as 8-, 16-, or 32-bit values.
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h
new file mode 100644
index 00000000000..8f14a43eafe
--- /dev/null
+++ b/arch/ppc/platforms/pq2ads_pd.h
@@ -0,0 +1,114 @@
1#ifndef __PQ2ADS_PD_H
2#define __PQ2ADS_PD_H
3/*
4 * arch/ppc/platforms/82xx/pq2ads_pd.h
5 *
6 * Some defines for MPC82xx board-specific PlatformDevice descriptions
7 *
8 * 2005 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16/* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
17 Can only choose from CLK9-12 */
18
19#define F1_RXCLK 11
20#define F1_TXCLK 10
21
22/* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
23 Can only choose from CLK13-16 */
24#define F2_RXCLK 15
25#define F2_TXCLK 16
26
27/* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
28 Can only choose from CLK13-16 */
29#define F3_RXCLK 13
30#define F3_TXCLK 14
31
32/* Automatically generates register configurations */
33#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
34
35#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
36#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
37#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
38#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
39#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
40#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
41
42#define PC_F1RXCLK PC_CLK(F1_RXCLK)
43#define PC_F1TXCLK PC_CLK(F1_TXCLK)
44#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
45#define CMX1_CLK_MASK ((uint)0xff000000)
46
47#define PC_F2RXCLK PC_CLK(F2_RXCLK)
48#define PC_F2TXCLK PC_CLK(F2_TXCLK)
49#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
50#define CMX2_CLK_MASK ((uint)0x00ff0000)
51
52#define PC_F3RXCLK PC_CLK(F3_RXCLK)
53#define PC_F3TXCLK PC_CLK(F3_TXCLK)
54#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
55#define CMX3_CLK_MASK ((uint)0x0000ff00)
56
57/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
58 * but there is little variation among the choices.
59 */
60#define PA1_COL 0x00000001U
61#define PA1_CRS 0x00000002U
62#define PA1_TXER 0x00000004U
63#define PA1_TXEN 0x00000008U
64#define PA1_RXDV 0x00000010U
65#define PA1_RXER 0x00000020U
66#define PA1_TXDAT 0x00003c00U
67#define PA1_RXDAT 0x0003c000U
68#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
69#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
70 PA1_RXDV | PA1_RXER)
71#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
72#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
73
74
75/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
76 * but there is little variation among the choices.
77 */
78#define PB2_TXER 0x00000001U
79#define PB2_RXDV 0x00000002U
80#define PB2_TXEN 0x00000004U
81#define PB2_RXER 0x00000008U
82#define PB2_COL 0x00000010U
83#define PB2_CRS 0x00000020U
84#define PB2_TXDAT 0x000003c0U
85#define PB2_RXDAT 0x00003c00U
86#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
87 PB2_RXER | PB2_RXDV | PB2_TXER)
88#define PB2_PSORB1 (PB2_TXEN)
89#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
90#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
91
92
93/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
94 * but there is little variation among the choices.
95 */
96#define PB3_RXDV 0x00004000U
97#define PB3_RXER 0x00008000U
98#define PB3_TXER 0x00010000U
99#define PB3_TXEN 0x00020000U
100#define PB3_COL 0x00040000U
101#define PB3_CRS 0x00080000U
102#define PB3_TXDAT 0x0f000000U
103#define PB3_RXDAT 0x00f00000U
104#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
105 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
106#define PB3_PSORB1 0
107#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
108#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
109
110#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
111#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
112#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
113
114#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 19:36:32 -0400