diff options
Diffstat (limited to 'arch/ppc/8xx_io/fec.c')
-rw-r--r-- | arch/ppc/8xx_io/fec.c | 1983 |
1 files changed, 0 insertions, 1983 deletions
diff --git a/arch/ppc/8xx_io/fec.c b/arch/ppc/8xx_io/fec.c deleted file mode 100644 index 2c604d4f6e8..00000000000 --- a/arch/ppc/8xx_io/fec.c +++ /dev/null | |||
@@ -1,1983 +0,0 @@ | |||
1 | /* | ||
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | ||
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | ||
4 | * | ||
5 | * This version of the driver is specific to the FADS implementation, | ||
6 | * since the board contains control registers external to the processor | ||
7 | * for the control of the LevelOne LXT970 transceiver. The MPC860T manual | ||
8 | * describes connections using the internal parallel port I/O, which | ||
9 | * is basically all of Port D. | ||
10 | * | ||
11 | * Includes support for the following PHYs: QS6612, LXT970, LXT971/2. | ||
12 | * | ||
13 | * Right now, I am very wasteful with the buffers. I allocate memory | ||
14 | * pages and then divide them into 2K frame buffers. This way I know I | ||
15 | * have buffers large enough to hold one frame within one buffer descriptor. | ||
16 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | ||
17 | * will be much more memory efficient and will easily handle lots of | ||
18 | * small packets. | ||
19 | * | ||
20 | * Much better multiple PHY support by Magnus Damm. | ||
21 | * Copyright (c) 2000 Ericsson Radio Systems AB. | ||
22 | * | ||
23 | * Make use of MII for PHY control configurable. | ||
24 | * Some fixes. | ||
25 | * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering. | ||
26 | * | ||
27 | * Support for AMD AM79C874 added. | ||
28 | * Thomas Lange, thomas@corelatus.com | ||
29 | */ | ||
30 | |||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/sched.h> | ||
33 | #include <linux/string.h> | ||
34 | #include <linux/ptrace.h> | ||
35 | #include <linux/errno.h> | ||
36 | #include <linux/ioport.h> | ||
37 | #include <linux/slab.h> | ||
38 | #include <linux/interrupt.h> | ||
39 | #include <linux/pci.h> | ||
40 | #include <linux/init.h> | ||
41 | #include <linux/delay.h> | ||
42 | #include <linux/netdevice.h> | ||
43 | #include <linux/etherdevice.h> | ||
44 | #include <linux/skbuff.h> | ||
45 | #include <linux/spinlock.h> | ||
46 | #include <linux/bitops.h> | ||
47 | #ifdef CONFIG_FEC_PACKETHOOK | ||
48 | #include <linux/pkthook.h> | ||
49 | #endif | ||
50 | |||
51 | #include <asm/8xx_immap.h> | ||
52 | #include <asm/pgtable.h> | ||
53 | #include <asm/mpc8xx.h> | ||
54 | #include <asm/irq.h> | ||
55 | #include <asm/uaccess.h> | ||
56 | #include <asm/cpm1.h> | ||
57 | |||
58 | #ifdef CONFIG_USE_MDIO | ||
59 | /* Forward declarations of some structures to support different PHYs | ||
60 | */ | ||
61 | |||
62 | typedef struct { | ||
63 | uint mii_data; | ||
64 | void (*funct)(uint mii_reg, struct net_device *dev); | ||
65 | } phy_cmd_t; | ||
66 | |||
67 | typedef struct { | ||
68 | uint id; | ||
69 | char *name; | ||
70 | |||
71 | const phy_cmd_t *config; | ||
72 | const phy_cmd_t *startup; | ||
73 | const phy_cmd_t *ack_int; | ||
74 | const phy_cmd_t *shutdown; | ||
75 | } phy_info_t; | ||
76 | #endif /* CONFIG_USE_MDIO */ | ||
77 | |||
78 | /* The number of Tx and Rx buffers. These are allocated from the page | ||
79 | * pool. The code may assume these are power of two, so it is best | ||
80 | * to keep them that size. | ||
81 | * We don't need to allocate pages for the transmitter. We just use | ||
82 | * the skbuffer directly. | ||
83 | */ | ||
84 | #ifdef CONFIG_ENET_BIG_BUFFERS | ||
85 | #define FEC_ENET_RX_PAGES 16 | ||
86 | #define FEC_ENET_RX_FRSIZE 2048 | ||
87 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | ||
88 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | ||
89 | #define TX_RING_SIZE 16 /* Must be power of two */ | ||
90 | #define TX_RING_MOD_MASK 15 /* for this to work */ | ||
91 | #else | ||
92 | #define FEC_ENET_RX_PAGES 4 | ||
93 | #define FEC_ENET_RX_FRSIZE 2048 | ||
94 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | ||
95 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | ||
96 | #define TX_RING_SIZE 8 /* Must be power of two */ | ||
97 | #define TX_RING_MOD_MASK 7 /* for this to work */ | ||
98 | #endif | ||
99 | |||
100 | /* Interrupt events/masks. | ||
101 | */ | ||
102 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ | ||
103 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | ||
104 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | ||
105 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | ||
106 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | ||
107 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | ||
108 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | ||
109 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | ||
110 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | ||
111 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | ||
112 | |||
113 | /* | ||
114 | */ | ||
115 | #define FEC_ECNTRL_PINMUX 0x00000004 | ||
116 | #define FEC_ECNTRL_ETHER_EN 0x00000002 | ||
117 | #define FEC_ECNTRL_RESET 0x00000001 | ||
118 | |||
119 | #define FEC_RCNTRL_BC_REJ 0x00000010 | ||
120 | #define FEC_RCNTRL_PROM 0x00000008 | ||
121 | #define FEC_RCNTRL_MII_MODE 0x00000004 | ||
122 | #define FEC_RCNTRL_DRT 0x00000002 | ||
123 | #define FEC_RCNTRL_LOOP 0x00000001 | ||
124 | |||
125 | #define FEC_TCNTRL_FDEN 0x00000004 | ||
126 | #define FEC_TCNTRL_HBC 0x00000002 | ||
127 | #define FEC_TCNTRL_GTS 0x00000001 | ||
128 | |||
129 | /* Delay to wait for FEC reset command to complete (in us) | ||
130 | */ | ||
131 | #define FEC_RESET_DELAY 50 | ||
132 | |||
133 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | ||
134 | */ | ||
135 | #define PKT_MAXBUF_SIZE 1518 | ||
136 | #define PKT_MINBUF_SIZE 64 | ||
137 | #define PKT_MAXBLR_SIZE 1520 | ||
138 | |||
139 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | ||
140 | * tx_bd_base always point to the base of the buffer descriptors. The | ||
141 | * cur_rx and cur_tx point to the currently available buffer. | ||
142 | * The dirty_tx tracks the current buffer that is being sent by the | ||
143 | * controller. The cur_tx and dirty_tx are equal under both completely | ||
144 | * empty and completely full conditions. The empty/ready indicator in | ||
145 | * the buffer descriptor determines the actual condition. | ||
146 | */ | ||
147 | struct fec_enet_private { | ||
148 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ | ||
149 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | ||
150 | ushort skb_cur; | ||
151 | ushort skb_dirty; | ||
152 | |||
153 | /* CPM dual port RAM relative addresses. | ||
154 | */ | ||
155 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ | ||
156 | cbd_t *tx_bd_base; | ||
157 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ | ||
158 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ | ||
159 | |||
160 | /* Virtual addresses for the receive buffers because we can't | ||
161 | * do a __va() on them anymore. | ||
162 | */ | ||
163 | unsigned char *rx_vaddr[RX_RING_SIZE]; | ||
164 | |||
165 | struct net_device_stats stats; | ||
166 | uint tx_full; | ||
167 | spinlock_t lock; | ||
168 | |||
169 | #ifdef CONFIG_USE_MDIO | ||
170 | uint phy_id; | ||
171 | uint phy_id_done; | ||
172 | uint phy_status; | ||
173 | uint phy_speed; | ||
174 | phy_info_t *phy; | ||
175 | struct work_struct phy_task; | ||
176 | struct net_device *dev; | ||
177 | |||
178 | uint sequence_done; | ||
179 | |||
180 | uint phy_addr; | ||
181 | #endif /* CONFIG_USE_MDIO */ | ||
182 | |||
183 | int link; | ||
184 | int old_link; | ||
185 | int full_duplex; | ||
186 | |||
187 | #ifdef CONFIG_FEC_PACKETHOOK | ||
188 | unsigned long ph_lock; | ||
189 | fec_ph_func *ph_rxhandler; | ||
190 | fec_ph_func *ph_txhandler; | ||
191 | __u16 ph_proto; | ||
192 | volatile __u32 *ph_regaddr; | ||
193 | void *ph_priv; | ||
194 | #endif | ||
195 | }; | ||
196 | |||
197 | static int fec_enet_open(struct net_device *dev); | ||
198 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | ||
199 | #ifdef CONFIG_USE_MDIO | ||
200 | static void fec_enet_mii(struct net_device *dev); | ||
201 | #endif /* CONFIG_USE_MDIO */ | ||
202 | #ifdef CONFIG_FEC_PACKETHOOK | ||
203 | static void fec_enet_tx(struct net_device *dev, __u32 regval); | ||
204 | static void fec_enet_rx(struct net_device *dev, __u32 regval); | ||
205 | #else | ||
206 | static void fec_enet_tx(struct net_device *dev); | ||
207 | static void fec_enet_rx(struct net_device *dev); | ||
208 | #endif | ||
209 | static int fec_enet_close(struct net_device *dev); | ||
210 | static struct net_device_stats *fec_enet_get_stats(struct net_device *dev); | ||
211 | static void set_multicast_list(struct net_device *dev); | ||
212 | static void fec_restart(struct net_device *dev, int duplex); | ||
213 | static void fec_stop(struct net_device *dev); | ||
214 | static ushort my_enet_addr[3]; | ||
215 | |||
216 | #ifdef CONFIG_USE_MDIO | ||
217 | /* MII processing. We keep this as simple as possible. Requests are | ||
218 | * placed on the list (if there is room). When the request is finished | ||
219 | * by the MII, an optional function may be called. | ||
220 | */ | ||
221 | typedef struct mii_list { | ||
222 | uint mii_regval; | ||
223 | void (*mii_func)(uint val, struct net_device *dev); | ||
224 | struct mii_list *mii_next; | ||
225 | } mii_list_t; | ||
226 | |||
227 | #define NMII 20 | ||
228 | mii_list_t mii_cmds[NMII]; | ||
229 | mii_list_t *mii_free; | ||
230 | mii_list_t *mii_head; | ||
231 | mii_list_t *mii_tail; | ||
232 | |||
233 | static int mii_queue(struct net_device *dev, int request, | ||
234 | void (*func)(uint, struct net_device *)); | ||
235 | |||
236 | /* Make MII read/write commands for the FEC. | ||
237 | */ | ||
238 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | ||
239 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | ||
240 | (VAL & 0xffff)) | ||
241 | #define mk_mii_end 0 | ||
242 | #endif /* CONFIG_USE_MDIO */ | ||
243 | |||
244 | /* Transmitter timeout. | ||
245 | */ | ||
246 | #define TX_TIMEOUT (2*HZ) | ||
247 | |||
248 | #ifdef CONFIG_USE_MDIO | ||
249 | /* Register definitions for the PHY. | ||
250 | */ | ||
251 | |||
252 | #define MII_REG_CR 0 /* Control Register */ | ||
253 | #define MII_REG_SR 1 /* Status Register */ | ||
254 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | ||
255 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | ||
256 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ | ||
257 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ | ||
258 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | ||
259 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | ||
260 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | ||
261 | |||
262 | /* values for phy_status */ | ||
263 | |||
264 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | ||
265 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | ||
266 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | ||
267 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | ||
268 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ | ||
269 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ | ||
270 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ | ||
271 | |||
272 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | ||
273 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | ||
274 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | ||
275 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | ||
276 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | ||
277 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ | ||
278 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ | ||
279 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ | ||
280 | #endif /* CONFIG_USE_MDIO */ | ||
281 | |||
282 | #ifdef CONFIG_FEC_PACKETHOOK | ||
283 | int | ||
284 | fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun, | ||
285 | __u16 proto, volatile __u32 *regaddr, void *priv) | ||
286 | { | ||
287 | struct fec_enet_private *fep; | ||
288 | int retval = 0; | ||
289 | |||
290 | fep = dev->priv; | ||
291 | |||
292 | if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) { | ||
293 | /* Someone is messing with the packet hook */ | ||
294 | return -EAGAIN; | ||
295 | } | ||
296 | if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) { | ||
297 | retval = -EBUSY; | ||
298 | goto out; | ||
299 | } | ||
300 | fep->ph_rxhandler = rxfun; | ||
301 | fep->ph_txhandler = txfun; | ||
302 | fep->ph_proto = proto; | ||
303 | fep->ph_regaddr = regaddr; | ||
304 | fep->ph_priv = priv; | ||
305 | |||
306 | out: | ||
307 | fep->ph_lock = 0; | ||
308 | |||
309 | return retval; | ||
310 | } | ||
311 | |||
312 | |||
313 | int | ||
314 | fec_unregister_ph(struct net_device *dev) | ||
315 | { | ||
316 | struct fec_enet_private *fep; | ||
317 | int retval = 0; | ||
318 | |||
319 | fep = dev->priv; | ||
320 | |||
321 | if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) { | ||
322 | /* Someone is messing with the packet hook */ | ||
323 | return -EAGAIN; | ||
324 | } | ||
325 | |||
326 | fep->ph_rxhandler = fep->ph_txhandler = NULL; | ||
327 | fep->ph_proto = 0; | ||
328 | fep->ph_regaddr = NULL; | ||
329 | fep->ph_priv = NULL; | ||
330 | |||
331 | fep->ph_lock = 0; | ||
332 | |||
333 | return retval; | ||
334 | } | ||
335 | |||
336 | EXPORT_SYMBOL(fec_register_ph); | ||
337 | EXPORT_SYMBOL(fec_unregister_ph); | ||
338 | |||
339 | #endif /* CONFIG_FEC_PACKETHOOK */ | ||
340 | |||
341 | static int | ||
342 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | ||
343 | { | ||
344 | struct fec_enet_private *fep; | ||
345 | volatile fec_t *fecp; | ||
346 | volatile cbd_t *bdp; | ||
347 | |||
348 | fep = dev->priv; | ||
349 | fecp = (volatile fec_t*)dev->base_addr; | ||
350 | |||
351 | if (!fep->link) { | ||
352 | /* Link is down or autonegotiation is in progress. */ | ||
353 | return 1; | ||
354 | } | ||
355 | |||
356 | /* Fill in a Tx ring entry */ | ||
357 | bdp = fep->cur_tx; | ||
358 | |||
359 | #ifndef final_version | ||
360 | if (bdp->cbd_sc & BD_ENET_TX_READY) { | ||
361 | /* Ooops. All transmit buffers are full. Bail out. | ||
362 | * This should not happen, since dev->tbusy should be set. | ||
363 | */ | ||
364 | printk("%s: tx queue full!.\n", dev->name); | ||
365 | return 1; | ||
366 | } | ||
367 | #endif | ||
368 | |||
369 | /* Clear all of the status flags. | ||
370 | */ | ||
371 | bdp->cbd_sc &= ~BD_ENET_TX_STATS; | ||
372 | |||
373 | /* Set buffer length and buffer pointer. | ||
374 | */ | ||
375 | bdp->cbd_bufaddr = __pa(skb->data); | ||
376 | bdp->cbd_datlen = skb->len; | ||
377 | |||
378 | /* Save skb pointer. | ||
379 | */ | ||
380 | fep->tx_skbuff[fep->skb_cur] = skb; | ||
381 | |||
382 | fep->stats.tx_bytes += skb->len; | ||
383 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; | ||
384 | |||
385 | /* Push the data cache so the CPM does not get stale memory | ||
386 | * data. | ||
387 | */ | ||
388 | flush_dcache_range((unsigned long)skb->data, | ||
389 | (unsigned long)skb->data + skb->len); | ||
390 | |||
391 | /* disable interrupts while triggering transmit */ | ||
392 | spin_lock_irq(&fep->lock); | ||
393 | |||
394 | /* Send it on its way. Tell FEC its ready, interrupt when done, | ||
395 | * its the last BD of the frame, and to put the CRC on the end. | ||
396 | */ | ||
397 | |||
398 | bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | ||
399 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); | ||
400 | |||
401 | dev->trans_start = jiffies; | ||
402 | |||
403 | /* Trigger transmission start */ | ||
404 | fecp->fec_x_des_active = 0x01000000; | ||
405 | |||
406 | /* If this was the last BD in the ring, start at the beginning again. | ||
407 | */ | ||
408 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) { | ||
409 | bdp = fep->tx_bd_base; | ||
410 | } else { | ||
411 | bdp++; | ||
412 | } | ||
413 | |||
414 | if (bdp->cbd_sc & BD_ENET_TX_READY) { | ||
415 | netif_stop_queue(dev); | ||
416 | fep->tx_full = 1; | ||
417 | } | ||
418 | |||
419 | fep->cur_tx = (cbd_t *)bdp; | ||
420 | |||
421 | spin_unlock_irq(&fep->lock); | ||
422 | |||
423 | return 0; | ||
424 | } | ||
425 | |||
426 | static void | ||
427 | fec_timeout(struct net_device *dev) | ||
428 | { | ||
429 | struct fec_enet_private *fep = dev->priv; | ||
430 | |||
431 | printk("%s: transmit timed out.\n", dev->name); | ||
432 | fep->stats.tx_errors++; | ||
433 | #ifndef final_version | ||
434 | { | ||
435 | int i; | ||
436 | cbd_t *bdp; | ||
437 | |||
438 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | ||
439 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | ||
440 | (unsigned long)fep->dirty_tx, | ||
441 | (unsigned long)fep->cur_rx); | ||
442 | |||
443 | bdp = fep->tx_bd_base; | ||
444 | printk(" tx: %u buffers\n", TX_RING_SIZE); | ||
445 | for (i = 0 ; i < TX_RING_SIZE; i++) { | ||
446 | printk(" %08x: %04x %04x %08x\n", | ||
447 | (uint) bdp, | ||
448 | bdp->cbd_sc, | ||
449 | bdp->cbd_datlen, | ||
450 | bdp->cbd_bufaddr); | ||
451 | bdp++; | ||
452 | } | ||
453 | |||
454 | bdp = fep->rx_bd_base; | ||
455 | printk(" rx: %lu buffers\n", RX_RING_SIZE); | ||
456 | for (i = 0 ; i < RX_RING_SIZE; i++) { | ||
457 | printk(" %08x: %04x %04x %08x\n", | ||
458 | (uint) bdp, | ||
459 | bdp->cbd_sc, | ||
460 | bdp->cbd_datlen, | ||
461 | bdp->cbd_bufaddr); | ||
462 | bdp++; | ||
463 | } | ||
464 | } | ||
465 | #endif | ||
466 | if (!fep->tx_full) | ||
467 | netif_wake_queue(dev); | ||
468 | } | ||
469 | |||
470 | /* The interrupt handler. | ||
471 | * This is called from the MPC core interrupt. | ||
472 | */ | ||
473 | static irqreturn_t | ||
474 | fec_enet_interrupt(int irq, void *dev_id) | ||
475 | { | ||
476 | struct net_device *dev = dev_id; | ||
477 | volatile fec_t *fecp; | ||
478 | uint int_events; | ||
479 | #ifdef CONFIG_FEC_PACKETHOOK | ||
480 | struct fec_enet_private *fep = dev->priv; | ||
481 | __u32 regval; | ||
482 | |||
483 | if (fep->ph_regaddr) regval = *fep->ph_regaddr; | ||
484 | #endif | ||
485 | fecp = (volatile fec_t*)dev->base_addr; | ||
486 | |||
487 | /* Get the interrupt events that caused us to be here. | ||
488 | */ | ||
489 | while ((int_events = fecp->fec_ievent) != 0) { | ||
490 | fecp->fec_ievent = int_events; | ||
491 | if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR | | ||
492 | FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) { | ||
493 | printk("FEC ERROR %x\n", int_events); | ||
494 | } | ||
495 | |||
496 | /* Handle receive event in its own function. | ||
497 | */ | ||
498 | if (int_events & FEC_ENET_RXF) { | ||
499 | #ifdef CONFIG_FEC_PACKETHOOK | ||
500 | fec_enet_rx(dev, regval); | ||
501 | #else | ||
502 | fec_enet_rx(dev); | ||
503 | #endif | ||
504 | } | ||
505 | |||
506 | /* Transmit OK, or non-fatal error. Update the buffer | ||
507 | descriptors. FEC handles all errors, we just discover | ||
508 | them as part of the transmit process. | ||
509 | */ | ||
510 | if (int_events & FEC_ENET_TXF) { | ||
511 | #ifdef CONFIG_FEC_PACKETHOOK | ||
512 | fec_enet_tx(dev, regval); | ||
513 | #else | ||
514 | fec_enet_tx(dev); | ||
515 | #endif | ||
516 | } | ||
517 | |||
518 | if (int_events & FEC_ENET_MII) { | ||
519 | #ifdef CONFIG_USE_MDIO | ||
520 | fec_enet_mii(dev); | ||
521 | #else | ||
522 | printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__, __LINE__, __func__); | ||
523 | #endif /* CONFIG_USE_MDIO */ | ||
524 | } | ||
525 | |||
526 | } | ||
527 | return IRQ_RETVAL(IRQ_HANDLED); | ||
528 | } | ||
529 | |||
530 | |||
531 | static void | ||
532 | #ifdef CONFIG_FEC_PACKETHOOK | ||
533 | fec_enet_tx(struct net_device *dev, __u32 regval) | ||
534 | #else | ||
535 | fec_enet_tx(struct net_device *dev) | ||
536 | #endif | ||
537 | { | ||
538 | struct fec_enet_private *fep; | ||
539 | volatile cbd_t *bdp; | ||
540 | struct sk_buff *skb; | ||
541 | |||
542 | fep = dev->priv; | ||
543 | /* lock while transmitting */ | ||
544 | spin_lock(&fep->lock); | ||
545 | bdp = fep->dirty_tx; | ||
546 | |||
547 | while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) { | ||
548 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; | ||
549 | |||
550 | skb = fep->tx_skbuff[fep->skb_dirty]; | ||
551 | /* Check for errors. */ | ||
552 | if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC | | ||
553 | BD_ENET_TX_RL | BD_ENET_TX_UN | | ||
554 | BD_ENET_TX_CSL)) { | ||
555 | fep->stats.tx_errors++; | ||
556 | if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */ | ||
557 | fep->stats.tx_heartbeat_errors++; | ||
558 | if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */ | ||
559 | fep->stats.tx_window_errors++; | ||
560 | if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */ | ||
561 | fep->stats.tx_aborted_errors++; | ||
562 | if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */ | ||
563 | fep->stats.tx_fifo_errors++; | ||
564 | if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */ | ||
565 | fep->stats.tx_carrier_errors++; | ||
566 | } else { | ||
567 | #ifdef CONFIG_FEC_PACKETHOOK | ||
568 | /* Packet hook ... */ | ||
569 | if (fep->ph_txhandler && | ||
570 | ((struct ethhdr *)skb->data)->h_proto | ||
571 | == fep->ph_proto) { | ||
572 | fep->ph_txhandler((__u8*)skb->data, skb->len, | ||
573 | regval, fep->ph_priv); | ||
574 | } | ||
575 | #endif | ||
576 | fep->stats.tx_packets++; | ||
577 | } | ||
578 | |||
579 | #ifndef final_version | ||
580 | if (bdp->cbd_sc & BD_ENET_TX_READY) | ||
581 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); | ||
582 | #endif | ||
583 | /* Deferred means some collisions occurred during transmit, | ||
584 | * but we eventually sent the packet OK. | ||
585 | */ | ||
586 | if (bdp->cbd_sc & BD_ENET_TX_DEF) | ||
587 | fep->stats.collisions++; | ||
588 | |||
589 | /* Free the sk buffer associated with this last transmit. | ||
590 | */ | ||
591 | #if 0 | ||
592 | printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty); | ||
593 | #endif | ||
594 | dev_kfree_skb_irq (skb/*, FREE_WRITE*/); | ||
595 | fep->tx_skbuff[fep->skb_dirty] = NULL; | ||
596 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | ||
597 | |||
598 | /* Update pointer to next buffer descriptor to be transmitted. | ||
599 | */ | ||
600 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | ||
601 | bdp = fep->tx_bd_base; | ||
602 | else | ||
603 | bdp++; | ||
604 | |||
605 | /* Since we have freed up a buffer, the ring is no longer | ||
606 | * full. | ||
607 | */ | ||
608 | if (fep->tx_full) { | ||
609 | fep->tx_full = 0; | ||
610 | if (netif_queue_stopped(dev)) | ||
611 | netif_wake_queue(dev); | ||
612 | } | ||
613 | #ifdef CONFIG_FEC_PACKETHOOK | ||
614 | /* Re-read register. Not exactly guaranteed to be correct, | ||
615 | but... */ | ||
616 | if (fep->ph_regaddr) regval = *fep->ph_regaddr; | ||
617 | #endif | ||
618 | } | ||
619 | fep->dirty_tx = (cbd_t *)bdp; | ||
620 | spin_unlock(&fep->lock); | ||
621 | } | ||
622 | |||
623 | |||
624 | /* During a receive, the cur_rx points to the current incoming buffer. | ||
625 | * When we update through the ring, if the next incoming buffer has | ||
626 | * not been given to the system, we just set the empty indicator, | ||
627 | * effectively tossing the packet. | ||
628 | */ | ||
629 | static void | ||
630 | #ifdef CONFIG_FEC_PACKETHOOK | ||
631 | fec_enet_rx(struct net_device *dev, __u32 regval) | ||
632 | #else | ||
633 | fec_enet_rx(struct net_device *dev) | ||
634 | #endif | ||
635 | { | ||
636 | struct fec_enet_private *fep; | ||
637 | volatile fec_t *fecp; | ||
638 | volatile cbd_t *bdp; | ||
639 | struct sk_buff *skb; | ||
640 | ushort pkt_len; | ||
641 | __u8 *data; | ||
642 | |||
643 | fep = dev->priv; | ||
644 | fecp = (volatile fec_t*)dev->base_addr; | ||
645 | |||
646 | /* First, grab all of the stats for the incoming packet. | ||
647 | * These get messed up if we get called due to a busy condition. | ||
648 | */ | ||
649 | bdp = fep->cur_rx; | ||
650 | |||
651 | while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) { | ||
652 | |||
653 | #ifndef final_version | ||
654 | /* Since we have allocated space to hold a complete frame, | ||
655 | * the last indicator should be set. | ||
656 | */ | ||
657 | if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0) | ||
658 | printk("FEC ENET: rcv is not +last\n"); | ||
659 | #endif | ||
660 | |||
661 | /* Check for errors. */ | ||
662 | if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | ||
663 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { | ||
664 | fep->stats.rx_errors++; | ||
665 | if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { | ||
666 | /* Frame too long or too short. */ | ||
667 | fep->stats.rx_length_errors++; | ||
668 | } | ||
669 | if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */ | ||
670 | fep->stats.rx_frame_errors++; | ||
671 | if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */ | ||
672 | fep->stats.rx_crc_errors++; | ||
673 | if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */ | ||
674 | fep->stats.rx_crc_errors++; | ||
675 | } | ||
676 | |||
677 | /* Report late collisions as a frame error. | ||
678 | * On this error, the BD is closed, but we don't know what we | ||
679 | * have in the buffer. So, just drop this frame on the floor. | ||
680 | */ | ||
681 | if (bdp->cbd_sc & BD_ENET_RX_CL) { | ||
682 | fep->stats.rx_errors++; | ||
683 | fep->stats.rx_frame_errors++; | ||
684 | goto rx_processing_done; | ||
685 | } | ||
686 | |||
687 | /* Process the incoming frame. | ||
688 | */ | ||
689 | fep->stats.rx_packets++; | ||
690 | pkt_len = bdp->cbd_datlen; | ||
691 | fep->stats.rx_bytes += pkt_len; | ||
692 | data = fep->rx_vaddr[bdp - fep->rx_bd_base]; | ||
693 | |||
694 | #ifdef CONFIG_FEC_PACKETHOOK | ||
695 | /* Packet hook ... */ | ||
696 | if (fep->ph_rxhandler) { | ||
697 | if (((struct ethhdr *)data)->h_proto == fep->ph_proto) { | ||
698 | switch (fep->ph_rxhandler(data, pkt_len, regval, | ||
699 | fep->ph_priv)) { | ||
700 | case 1: | ||
701 | goto rx_processing_done; | ||
702 | break; | ||
703 | case 0: | ||
704 | break; | ||
705 | default: | ||
706 | fep->stats.rx_errors++; | ||
707 | goto rx_processing_done; | ||
708 | } | ||
709 | } | ||
710 | } | ||
711 | |||
712 | /* If it wasn't filtered - copy it to an sk buffer. */ | ||
713 | #endif | ||
714 | |||
715 | /* This does 16 byte alignment, exactly what we need. | ||
716 | * The packet length includes FCS, but we don't want to | ||
717 | * include that when passing upstream as it messes up | ||
718 | * bridging applications. | ||
719 | */ | ||
720 | skb = dev_alloc_skb(pkt_len-4); | ||
721 | |||
722 | if (skb == NULL) { | ||
723 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | ||
724 | fep->stats.rx_dropped++; | ||
725 | } else { | ||
726 | skb_put(skb,pkt_len-4); /* Make room */ | ||
727 | skb_copy_to_linear_data(skb, data, pkt_len-4); | ||
728 | skb->protocol=eth_type_trans(skb,dev); | ||
729 | netif_rx(skb); | ||
730 | } | ||
731 | rx_processing_done: | ||
732 | |||
733 | /* Clear the status flags for this buffer. | ||
734 | */ | ||
735 | bdp->cbd_sc &= ~BD_ENET_RX_STATS; | ||
736 | |||
737 | /* Mark the buffer empty. | ||
738 | */ | ||
739 | bdp->cbd_sc |= BD_ENET_RX_EMPTY; | ||
740 | |||
741 | /* Update BD pointer to next entry. | ||
742 | */ | ||
743 | if (bdp->cbd_sc & BD_ENET_RX_WRAP) | ||
744 | bdp = fep->rx_bd_base; | ||
745 | else | ||
746 | bdp++; | ||
747 | |||
748 | #if 1 | ||
749 | /* Doing this here will keep the FEC running while we process | ||
750 | * incoming frames. On a heavily loaded network, we should be | ||
751 | * able to keep up at the expense of system resources. | ||
752 | */ | ||
753 | fecp->fec_r_des_active = 0x01000000; | ||
754 | #endif | ||
755 | #ifdef CONFIG_FEC_PACKETHOOK | ||
756 | /* Re-read register. Not exactly guaranteed to be correct, | ||
757 | but... */ | ||
758 | if (fep->ph_regaddr) regval = *fep->ph_regaddr; | ||
759 | #endif | ||
760 | } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */ | ||
761 | fep->cur_rx = (cbd_t *)bdp; | ||
762 | |||
763 | #if 0 | ||
764 | /* Doing this here will allow us to process all frames in the | ||
765 | * ring before the FEC is allowed to put more there. On a heavily | ||
766 | * loaded network, some frames may be lost. Unfortunately, this | ||
767 | * increases the interrupt overhead since we can potentially work | ||
768 | * our way back to the interrupt return only to come right back | ||
769 | * here. | ||
770 | */ | ||
771 | fecp->fec_r_des_active = 0x01000000; | ||
772 | #endif | ||
773 | } | ||
774 | |||
775 | |||
776 | #ifdef CONFIG_USE_MDIO | ||
777 | static void | ||
778 | fec_enet_mii(struct net_device *dev) | ||
779 | { | ||
780 | struct fec_enet_private *fep; | ||
781 | volatile fec_t *ep; | ||
782 | mii_list_t *mip; | ||
783 | uint mii_reg; | ||
784 | |||
785 | fep = (struct fec_enet_private *)dev->priv; | ||
786 | ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec); | ||
787 | mii_reg = ep->fec_mii_data; | ||
788 | |||
789 | if ((mip = mii_head) == NULL) { | ||
790 | printk("MII and no head!\n"); | ||
791 | return; | ||
792 | } | ||
793 | |||
794 | if (mip->mii_func != NULL) | ||
795 | (*(mip->mii_func))(mii_reg, dev); | ||
796 | |||
797 | mii_head = mip->mii_next; | ||
798 | mip->mii_next = mii_free; | ||
799 | mii_free = mip; | ||
800 | |||
801 | if ((mip = mii_head) != NULL) { | ||
802 | ep->fec_mii_data = mip->mii_regval; | ||
803 | |||
804 | } | ||
805 | } | ||
806 | |||
807 | static int | ||
808 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | ||
809 | { | ||
810 | struct fec_enet_private *fep; | ||
811 | unsigned long flags; | ||
812 | mii_list_t *mip; | ||
813 | int retval; | ||
814 | |||
815 | /* Add PHY address to register command. | ||
816 | */ | ||
817 | fep = dev->priv; | ||
818 | regval |= fep->phy_addr << 23; | ||
819 | |||
820 | retval = 0; | ||
821 | |||
822 | /* lock while modifying mii_list */ | ||
823 | spin_lock_irqsave(&fep->lock, flags); | ||
824 | |||
825 | if ((mip = mii_free) != NULL) { | ||
826 | mii_free = mip->mii_next; | ||
827 | mip->mii_regval = regval; | ||
828 | mip->mii_func = func; | ||
829 | mip->mii_next = NULL; | ||
830 | if (mii_head) { | ||
831 | mii_tail->mii_next = mip; | ||
832 | mii_tail = mip; | ||
833 | } else { | ||
834 | mii_head = mii_tail = mip; | ||
835 | (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval; | ||
836 | } | ||
837 | } else { | ||
838 | retval = 1; | ||
839 | } | ||
840 | |||
841 | spin_unlock_irqrestore(&fep->lock, flags); | ||
842 | |||
843 | return(retval); | ||
844 | } | ||
845 | |||
846 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | ||
847 | { | ||
848 | int k; | ||
849 | |||
850 | if(!c) | ||
851 | return; | ||
852 | |||
853 | for(k = 0; (c+k)->mii_data != mk_mii_end; k++) | ||
854 | mii_queue(dev, (c+k)->mii_data, (c+k)->funct); | ||
855 | } | ||
856 | |||
857 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | ||
858 | { | ||
859 | struct fec_enet_private *fep = dev->priv; | ||
860 | volatile uint *s = &(fep->phy_status); | ||
861 | |||
862 | *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); | ||
863 | |||
864 | if (mii_reg & 0x0004) | ||
865 | *s |= PHY_STAT_LINK; | ||
866 | if (mii_reg & 0x0010) | ||
867 | *s |= PHY_STAT_FAULT; | ||
868 | if (mii_reg & 0x0020) | ||
869 | *s |= PHY_STAT_ANC; | ||
870 | |||
871 | fep->link = (*s & PHY_STAT_LINK) ? 1 : 0; | ||
872 | } | ||
873 | |||
874 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | ||
875 | { | ||
876 | struct fec_enet_private *fep = dev->priv; | ||
877 | volatile uint *s = &(fep->phy_status); | ||
878 | |||
879 | *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP); | ||
880 | |||
881 | if (mii_reg & 0x1000) | ||
882 | *s |= PHY_CONF_ANE; | ||
883 | if (mii_reg & 0x4000) | ||
884 | *s |= PHY_CONF_LOOP; | ||
885 | } | ||
886 | |||
887 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | ||
888 | { | ||
889 | struct fec_enet_private *fep = dev->priv; | ||
890 | volatile uint *s = &(fep->phy_status); | ||
891 | |||
892 | *s &= ~(PHY_CONF_SPMASK); | ||
893 | |||
894 | if (mii_reg & 0x0020) | ||
895 | *s |= PHY_CONF_10HDX; | ||
896 | if (mii_reg & 0x0040) | ||
897 | *s |= PHY_CONF_10FDX; | ||
898 | if (mii_reg & 0x0080) | ||
899 | *s |= PHY_CONF_100HDX; | ||
900 | if (mii_reg & 0x00100) | ||
901 | *s |= PHY_CONF_100FDX; | ||
902 | } | ||
903 | #if 0 | ||
904 | static void mii_disp_reg(uint mii_reg, struct net_device *dev) | ||
905 | { | ||
906 | printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff); | ||
907 | } | ||
908 | #endif | ||
909 | |||
910 | /* ------------------------------------------------------------------------- */ | ||
911 | /* The Level one LXT970 is used by many boards */ | ||
912 | |||
913 | #ifdef CONFIG_FEC_LXT970 | ||
914 | |||
915 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | ||
916 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | ||
917 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | ||
918 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | ||
919 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | ||
920 | |||
921 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | ||
922 | { | ||
923 | struct fec_enet_private *fep = dev->priv; | ||
924 | volatile uint *s = &(fep->phy_status); | ||
925 | |||
926 | *s &= ~(PHY_STAT_SPMASK); | ||
927 | |||
928 | if (mii_reg & 0x0800) { | ||
929 | if (mii_reg & 0x1000) | ||
930 | *s |= PHY_STAT_100FDX; | ||
931 | else | ||
932 | *s |= PHY_STAT_100HDX; | ||
933 | } | ||
934 | else { | ||
935 | if (mii_reg & 0x1000) | ||
936 | *s |= PHY_STAT_10FDX; | ||
937 | else | ||
938 | *s |= PHY_STAT_10HDX; | ||
939 | } | ||
940 | } | ||
941 | |||
942 | static phy_info_t phy_info_lxt970 = { | ||
943 | 0x07810000, | ||
944 | "LXT970", | ||
945 | |||
946 | (const phy_cmd_t []) { /* config */ | ||
947 | #if 0 | ||
948 | // { mk_mii_write(MII_REG_ANAR, 0x0021), NULL }, | ||
949 | |||
950 | /* Set default operation of 100-TX....for some reason | ||
951 | * some of these bits are set on power up, which is wrong. | ||
952 | */ | ||
953 | { mk_mii_write(MII_LXT970_CONFIG, 0), NULL }, | ||
954 | #endif | ||
955 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | ||
956 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | ||
957 | { mk_mii_end, } | ||
958 | }, | ||
959 | (const phy_cmd_t []) { /* startup - enable interrupts */ | ||
960 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, | ||
961 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | ||
962 | { mk_mii_end, } | ||
963 | }, | ||
964 | (const phy_cmd_t []) { /* ack_int */ | ||
965 | /* read SR and ISR to acknowledge */ | ||
966 | |||
967 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | ||
968 | { mk_mii_read(MII_LXT970_ISR), NULL }, | ||
969 | |||
970 | /* find out the current status */ | ||
971 | |||
972 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | ||
973 | { mk_mii_end, } | ||
974 | }, | ||
975 | (const phy_cmd_t []) { /* shutdown - disable interrupts */ | ||
976 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, | ||
977 | { mk_mii_end, } | ||
978 | }, | ||
979 | }; | ||
980 | |||
981 | #endif /* CONFIG_FEC_LXT970 */ | ||
982 | |||
983 | /* ------------------------------------------------------------------------- */ | ||
984 | /* The Level one LXT971 is used on some of my custom boards */ | ||
985 | |||
986 | #ifdef CONFIG_FEC_LXT971 | ||
987 | |||
988 | /* register definitions for the 971 */ | ||
989 | |||
990 | #define MII_LXT971_PCR 16 /* Port Control Register */ | ||
991 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | ||
992 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | ||
993 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | ||
994 | #define MII_LXT971_LCR 20 /* LED Control Register */ | ||
995 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | ||
996 | |||
997 | /* | ||
998 | * I had some nice ideas of running the MDIO faster... | ||
999 | * The 971 should support 8MHz and I tried it, but things acted really | ||
1000 | * weird, so 2.5 MHz ought to be enough for anyone... | ||
1001 | */ | ||
1002 | |||
1003 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | ||
1004 | { | ||
1005 | struct fec_enet_private *fep = dev->priv; | ||
1006 | volatile uint *s = &(fep->phy_status); | ||
1007 | |||
1008 | *s &= ~(PHY_STAT_SPMASK); | ||
1009 | |||
1010 | if (mii_reg & 0x4000) { | ||
1011 | if (mii_reg & 0x0200) | ||
1012 | *s |= PHY_STAT_100FDX; | ||
1013 | else | ||
1014 | *s |= PHY_STAT_100HDX; | ||
1015 | } | ||
1016 | else { | ||
1017 | if (mii_reg & 0x0200) | ||
1018 | *s |= PHY_STAT_10FDX; | ||
1019 | else | ||
1020 | *s |= PHY_STAT_10HDX; | ||
1021 | } | ||
1022 | if (mii_reg & 0x0008) | ||
1023 | *s |= PHY_STAT_FAULT; | ||
1024 | } | ||
1025 | |||
1026 | static phy_info_t phy_info_lxt971 = { | ||
1027 | 0x0001378e, | ||
1028 | "LXT971", | ||
1029 | |||
1030 | (const phy_cmd_t []) { /* config */ | ||
1031 | // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */ | ||
1032 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | ||
1033 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | ||
1034 | { mk_mii_end, } | ||
1035 | }, | ||
1036 | (const phy_cmd_t []) { /* startup - enable interrupts */ | ||
1037 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, | ||
1038 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | ||
1039 | |||
1040 | /* Somehow does the 971 tell me that the link is down | ||
1041 | * the first read after power-up. | ||
1042 | * read here to get a valid value in ack_int */ | ||
1043 | |||
1044 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | ||
1045 | { mk_mii_end, } | ||
1046 | }, | ||
1047 | (const phy_cmd_t []) { /* ack_int */ | ||
1048 | /* find out the current status */ | ||
1049 | |||
1050 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | ||
1051 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | ||
1052 | |||
1053 | /* we only need to read ISR to acknowledge */ | ||
1054 | |||
1055 | { mk_mii_read(MII_LXT971_ISR), NULL }, | ||
1056 | { mk_mii_end, } | ||
1057 | }, | ||
1058 | (const phy_cmd_t []) { /* shutdown - disable interrupts */ | ||
1059 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, | ||
1060 | { mk_mii_end, } | ||
1061 | }, | ||
1062 | }; | ||
1063 | |||
1064 | #endif /* CONFIG_FEC_LXT970 */ | ||
1065 | |||
1066 | |||
1067 | /* ------------------------------------------------------------------------- */ | ||
1068 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | ||
1069 | |||
1070 | #ifdef CONFIG_FEC_QS6612 | ||
1071 | |||
1072 | /* register definitions */ | ||
1073 | |||
1074 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | ||
1075 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | ||
1076 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | ||
1077 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | ||
1078 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | ||
1079 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | ||
1080 | |||
1081 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | ||
1082 | { | ||
1083 | struct fec_enet_private *fep = dev->priv; | ||
1084 | volatile uint *s = &(fep->phy_status); | ||
1085 | |||
1086 | *s &= ~(PHY_STAT_SPMASK); | ||
1087 | |||
1088 | switch((mii_reg >> 2) & 7) { | ||
1089 | case 1: *s |= PHY_STAT_10HDX; break; | ||
1090 | case 2: *s |= PHY_STAT_100HDX; break; | ||
1091 | case 5: *s |= PHY_STAT_10FDX; break; | ||
1092 | case 6: *s |= PHY_STAT_100FDX; break; | ||
1093 | } | ||
1094 | } | ||
1095 | |||
1096 | static phy_info_t phy_info_qs6612 = { | ||
1097 | 0x00181440, | ||
1098 | "QS6612", | ||
1099 | |||
1100 | (const phy_cmd_t []) { /* config */ | ||
1101 | // { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */ | ||
1102 | |||
1103 | /* The PHY powers up isolated on the RPX, | ||
1104 | * so send a command to allow operation. | ||
1105 | */ | ||
1106 | |||
1107 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | ||
1108 | |||
1109 | /* parse cr and anar to get some info */ | ||
1110 | |||
1111 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | ||
1112 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | ||
1113 | { mk_mii_end, } | ||
1114 | }, | ||
1115 | (const phy_cmd_t []) { /* startup - enable interrupts */ | ||
1116 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, | ||
1117 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | ||
1118 | { mk_mii_end, } | ||
1119 | }, | ||
1120 | (const phy_cmd_t []) { /* ack_int */ | ||
1121 | |||
1122 | /* we need to read ISR, SR and ANER to acknowledge */ | ||
1123 | |||
1124 | { mk_mii_read(MII_QS6612_ISR), NULL }, | ||
1125 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | ||
1126 | { mk_mii_read(MII_REG_ANER), NULL }, | ||
1127 | |||
1128 | /* read pcr to get info */ | ||
1129 | |||
1130 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | ||
1131 | { mk_mii_end, } | ||
1132 | }, | ||
1133 | (const phy_cmd_t []) { /* shutdown - disable interrupts */ | ||
1134 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, | ||
1135 | { mk_mii_end, } | ||
1136 | }, | ||
1137 | }; | ||
1138 | |||
1139 | #endif /* CONFIG_FEC_QS6612 */ | ||
1140 | |||
1141 | /* ------------------------------------------------------------------------- */ | ||
1142 | /* The Advanced Micro Devices AM79C874 is used on the ICU862 */ | ||
1143 | |||
1144 | #ifdef CONFIG_FEC_AM79C874 | ||
1145 | |||
1146 | /* register definitions for the 79C874 */ | ||
1147 | |||
1148 | #define MII_AM79C874_MFR 16 /* Miscellaneous Features Register */ | ||
1149 | #define MII_AM79C874_ICSR 17 /* Interrupt Control/Status Register */ | ||
1150 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | ||
1151 | #define MII_AM79C874_PMLR 19 /* Power Management & Loopback Register */ | ||
1152 | #define MII_AM79C874_MCR 21 /* Mode Control Register */ | ||
1153 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | ||
1154 | #define MII_AM79C874_REC 24 /* Receiver Error Counter */ | ||
1155 | |||
1156 | static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data) | ||
1157 | { | ||
1158 | volatile struct fec_enet_private *fep = dev->priv; | ||
1159 | uint s = fep->phy_status; | ||
1160 | |||
1161 | s &= ~(PHY_STAT_SPMASK); | ||
1162 | |||
1163 | /* Register 18: Bit 10 is data rate, 11 is Duplex */ | ||
1164 | switch ((mii_reg >> 10) & 3) { | ||
1165 | case 0: s |= PHY_STAT_10HDX; break; | ||
1166 | case 1: s |= PHY_STAT_100HDX; break; | ||
1167 | case 2: s |= PHY_STAT_10FDX; break; | ||
1168 | case 3: s |= PHY_STAT_100FDX; break; | ||
1169 | } | ||
1170 | |||
1171 | fep->phy_status = s; | ||
1172 | } | ||
1173 | |||
1174 | static phy_info_t phy_info_amd79c874 = { | ||
1175 | 0x00022561, | ||
1176 | "AM79C874", | ||
1177 | |||
1178 | (const phy_cmd_t []) { /* config */ | ||
1179 | // { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */ | ||
1180 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | ||
1181 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | ||
1182 | { mk_mii_end, } | ||
1183 | }, | ||
1184 | (const phy_cmd_t []) { /* startup - enable interrupts */ | ||
1185 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, | ||
1186 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | ||
1187 | { mk_mii_end, } | ||
1188 | }, | ||
1189 | (const phy_cmd_t []) { /* ack_int */ | ||
1190 | /* find out the current status */ | ||
1191 | |||
1192 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | ||
1193 | { mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr }, | ||
1194 | |||
1195 | /* we only need to read ICSR to acknowledge */ | ||
1196 | |||
1197 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | ||
1198 | { mk_mii_end, } | ||
1199 | }, | ||
1200 | (const phy_cmd_t []) { /* shutdown - disable interrupts */ | ||
1201 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, | ||
1202 | { mk_mii_end, } | ||
1203 | }, | ||
1204 | }; | ||
1205 | |||
1206 | #endif /* CONFIG_FEC_AM79C874 */ | ||
1207 | |||
1208 | static phy_info_t *phy_info[] = { | ||
1209 | |||
1210 | #ifdef CONFIG_FEC_LXT970 | ||
1211 | &phy_info_lxt970, | ||
1212 | #endif /* CONFIG_FEC_LXT970 */ | ||
1213 | |||
1214 | #ifdef CONFIG_FEC_LXT971 | ||
1215 | &phy_info_lxt971, | ||
1216 | #endif /* CONFIG_FEC_LXT971 */ | ||
1217 | |||
1218 | #ifdef CONFIG_FEC_QS6612 | ||
1219 | &phy_info_qs6612, | ||
1220 | #endif /* CONFIG_FEC_QS6612 */ | ||
1221 | |||
1222 | #ifdef CONFIG_FEC_AM79C874 | ||
1223 | &phy_info_amd79c874, | ||
1224 | #endif /* CONFIG_FEC_AM79C874 */ | ||
1225 | |||
1226 | NULL | ||
1227 | }; | ||
1228 | |||
1229 | static void mii_display_status(struct net_device *dev) | ||
1230 | { | ||
1231 | struct fec_enet_private *fep = dev->priv; | ||
1232 | volatile uint *s = &(fep->phy_status); | ||
1233 | |||
1234 | if (!fep->link && !fep->old_link) { | ||
1235 | /* Link is still down - don't print anything */ | ||
1236 | return; | ||
1237 | } | ||
1238 | |||
1239 | printk("%s: status: ", dev->name); | ||
1240 | |||
1241 | if (!fep->link) { | ||
1242 | printk("link down"); | ||
1243 | } else { | ||
1244 | printk("link up"); | ||
1245 | |||
1246 | switch(*s & PHY_STAT_SPMASK) { | ||
1247 | case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break; | ||
1248 | case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break; | ||
1249 | case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break; | ||
1250 | case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break; | ||
1251 | default: | ||
1252 | printk(", Unknown speed/duplex"); | ||
1253 | } | ||
1254 | |||
1255 | if (*s & PHY_STAT_ANC) | ||
1256 | printk(", auto-negotiation complete"); | ||
1257 | } | ||
1258 | |||
1259 | if (*s & PHY_STAT_FAULT) | ||
1260 | printk(", remote fault"); | ||
1261 | |||
1262 | printk(".\n"); | ||
1263 | } | ||
1264 | |||
1265 | static void mii_display_config(struct work_struct *work) | ||
1266 | { | ||
1267 | struct fec_enet_private *fep = | ||
1268 | container_of(work, struct fec_enet_private, phy_task); | ||
1269 | struct net_device *dev = fep->dev; | ||
1270 | volatile uint *s = &(fep->phy_status); | ||
1271 | |||
1272 | printk("%s: config: auto-negotiation ", dev->name); | ||
1273 | |||
1274 | if (*s & PHY_CONF_ANE) | ||
1275 | printk("on"); | ||
1276 | else | ||
1277 | printk("off"); | ||
1278 | |||
1279 | if (*s & PHY_CONF_100FDX) | ||
1280 | printk(", 100FDX"); | ||
1281 | if (*s & PHY_CONF_100HDX) | ||
1282 | printk(", 100HDX"); | ||
1283 | if (*s & PHY_CONF_10FDX) | ||
1284 | printk(", 10FDX"); | ||
1285 | if (*s & PHY_CONF_10HDX) | ||
1286 | printk(", 10HDX"); | ||
1287 | if (!(*s & PHY_CONF_SPMASK)) | ||
1288 | printk(", No speed/duplex selected?"); | ||
1289 | |||
1290 | if (*s & PHY_CONF_LOOP) | ||
1291 | printk(", loopback enabled"); | ||
1292 | |||
1293 | printk(".\n"); | ||
1294 | |||
1295 | fep->sequence_done = 1; | ||
1296 | } | ||
1297 | |||
1298 | static void mii_relink(struct work_struct *work) | ||
1299 | { | ||
1300 | struct fec_enet_private *fep = | ||
1301 | container_of(work, struct fec_enet_private, phy_task); | ||
1302 | struct net_device *dev = fep->dev; | ||
1303 | int duplex; | ||
1304 | |||
1305 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | ||
1306 | mii_display_status(dev); | ||
1307 | fep->old_link = fep->link; | ||
1308 | |||
1309 | if (fep->link) { | ||
1310 | duplex = 0; | ||
1311 | if (fep->phy_status | ||
1312 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) | ||
1313 | duplex = 1; | ||
1314 | fec_restart(dev, duplex); | ||
1315 | } | ||
1316 | else | ||
1317 | fec_stop(dev); | ||
1318 | |||
1319 | #if 0 | ||
1320 | enable_irq(fep->mii_irq); | ||
1321 | #endif | ||
1322 | |||
1323 | } | ||
1324 | |||
1325 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | ||
1326 | { | ||
1327 | struct fec_enet_private *fep = dev->priv; | ||
1328 | |||
1329 | fep->dev = dev; | ||
1330 | INIT_WORK(&fep->phy_task, mii_relink); | ||
1331 | schedule_work(&fep->phy_task); | ||
1332 | } | ||
1333 | |||
1334 | static void mii_queue_config(uint mii_reg, struct net_device *dev) | ||
1335 | { | ||
1336 | struct fec_enet_private *fep = dev->priv; | ||
1337 | |||
1338 | fep->dev = dev; | ||
1339 | INIT_WORK(&fep->phy_task, mii_display_config); | ||
1340 | schedule_work(&fep->phy_task); | ||
1341 | } | ||
1342 | |||
1343 | |||
1344 | |||
1345 | phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink }, | ||
1346 | { mk_mii_end, } }; | ||
1347 | phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config }, | ||
1348 | { mk_mii_end, } }; | ||
1349 | |||
1350 | |||
1351 | |||
1352 | /* Read remainder of PHY ID. | ||
1353 | */ | ||
1354 | static void | ||
1355 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | ||
1356 | { | ||
1357 | struct fec_enet_private *fep; | ||
1358 | int i; | ||
1359 | |||
1360 | fep = dev->priv; | ||
1361 | fep->phy_id |= (mii_reg & 0xffff); | ||
1362 | |||
1363 | for(i = 0; phy_info[i]; i++) | ||
1364 | if(phy_info[i]->id == (fep->phy_id >> 4)) | ||
1365 | break; | ||
1366 | |||
1367 | if(!phy_info[i]) | ||
1368 | panic("%s: PHY id 0x%08x is not supported!\n", | ||
1369 | dev->name, fep->phy_id); | ||
1370 | |||
1371 | fep->phy = phy_info[i]; | ||
1372 | fep->phy_id_done = 1; | ||
1373 | |||
1374 | printk("%s: Phy @ 0x%x, type %s (0x%08x)\n", | ||
1375 | dev->name, fep->phy_addr, fep->phy->name, fep->phy_id); | ||
1376 | } | ||
1377 | |||
1378 | /* Scan all of the MII PHY addresses looking for someone to respond | ||
1379 | * with a valid ID. This usually happens quickly. | ||
1380 | */ | ||
1381 | static void | ||
1382 | mii_discover_phy(uint mii_reg, struct net_device *dev) | ||
1383 | { | ||
1384 | struct fec_enet_private *fep; | ||
1385 | uint phytype; | ||
1386 | |||
1387 | fep = dev->priv; | ||
1388 | |||
1389 | if ((phytype = (mii_reg & 0xffff)) != 0xffff) { | ||
1390 | |||
1391 | /* Got first part of ID, now get remainder. | ||
1392 | */ | ||
1393 | fep->phy_id = phytype << 16; | ||
1394 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3); | ||
1395 | } else { | ||
1396 | fep->phy_addr++; | ||
1397 | if (fep->phy_addr < 32) { | ||
1398 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | ||
1399 | mii_discover_phy); | ||
1400 | } else { | ||
1401 | printk("fec: No PHY device found.\n"); | ||
1402 | } | ||
1403 | } | ||
1404 | } | ||
1405 | #endif /* CONFIG_USE_MDIO */ | ||
1406 | |||
1407 | /* This interrupt occurs when the PHY detects a link change. | ||
1408 | */ | ||
1409 | static | ||
1410 | #ifdef CONFIG_RPXCLASSIC | ||
1411 | void mii_link_interrupt(void *dev_id) | ||
1412 | #else | ||
1413 | irqreturn_t mii_link_interrupt(int irq, void * dev_id) | ||
1414 | #endif | ||
1415 | { | ||
1416 | #ifdef CONFIG_USE_MDIO | ||
1417 | struct net_device *dev = dev_id; | ||
1418 | struct fec_enet_private *fep = dev->priv; | ||
1419 | volatile immap_t *immap = (immap_t *)IMAP_ADDR; | ||
1420 | volatile fec_t *fecp = &(immap->im_cpm.cp_fec); | ||
1421 | unsigned int ecntrl = fecp->fec_ecntrl; | ||
1422 | |||
1423 | /* We need the FEC enabled to access the MII | ||
1424 | */ | ||
1425 | if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) { | ||
1426 | fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN; | ||
1427 | } | ||
1428 | #endif /* CONFIG_USE_MDIO */ | ||
1429 | |||
1430 | #if 0 | ||
1431 | disable_irq(fep->mii_irq); /* disable now, enable later */ | ||
1432 | #endif | ||
1433 | |||
1434 | |||
1435 | #ifdef CONFIG_USE_MDIO | ||
1436 | mii_do_cmd(dev, fep->phy->ack_int); | ||
1437 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | ||
1438 | |||
1439 | if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) { | ||
1440 | fecp->fec_ecntrl = ecntrl; /* restore old settings */ | ||
1441 | } | ||
1442 | #else | ||
1443 | printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__, __LINE__, __func__); | ||
1444 | #endif /* CONFIG_USE_MDIO */ | ||
1445 | |||
1446 | #ifndef CONFIG_RPXCLASSIC | ||
1447 | return IRQ_RETVAL(IRQ_HANDLED); | ||
1448 | #endif /* CONFIG_RPXCLASSIC */ | ||
1449 | } | ||
1450 | |||
1451 | static int | ||
1452 | fec_enet_open(struct net_device *dev) | ||
1453 | { | ||
1454 | struct fec_enet_private *fep = dev->priv; | ||
1455 | |||
1456 | /* I should reset the ring buffers here, but I don't yet know | ||
1457 | * a simple way to do that. | ||
1458 | */ | ||
1459 | |||
1460 | #ifdef CONFIG_USE_MDIO | ||
1461 | fep->sequence_done = 0; | ||
1462 | fep->link = 0; | ||
1463 | |||
1464 | if (fep->phy) { | ||
1465 | mii_do_cmd(dev, fep->phy->ack_int); | ||
1466 | mii_do_cmd(dev, fep->phy->config); | ||
1467 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | ||
1468 | while(!fep->sequence_done) | ||
1469 | schedule(); | ||
1470 | |||
1471 | mii_do_cmd(dev, fep->phy->startup); | ||
1472 | netif_start_queue(dev); | ||
1473 | return 0; /* Success */ | ||
1474 | } | ||
1475 | return -ENODEV; /* No PHY we understand */ | ||
1476 | #else | ||
1477 | fep->link = 1; | ||
1478 | netif_start_queue(dev); | ||
1479 | return 0; /* Success */ | ||
1480 | #endif /* CONFIG_USE_MDIO */ | ||
1481 | |||
1482 | } | ||
1483 | |||
1484 | static int | ||
1485 | fec_enet_close(struct net_device *dev) | ||
1486 | { | ||
1487 | /* Don't know what to do yet. | ||
1488 | */ | ||
1489 | netif_stop_queue(dev); | ||
1490 | fec_stop(dev); | ||
1491 | |||
1492 | return 0; | ||
1493 | } | ||
1494 | |||
1495 | static struct net_device_stats *fec_enet_get_stats(struct net_device *dev) | ||
1496 | { | ||
1497 | struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv; | ||
1498 | |||
1499 | return &fep->stats; | ||
1500 | } | ||
1501 | |||
1502 | /* Set or clear the multicast filter for this adaptor. | ||
1503 | * Skeleton taken from sunlance driver. | ||
1504 | * The CPM Ethernet implementation allows Multicast as well as individual | ||
1505 | * MAC address filtering. Some of the drivers check to make sure it is | ||
1506 | * a group multicast address, and discard those that are not. I guess I | ||
1507 | * will do the same for now, but just remove the test if you want | ||
1508 | * individual filtering as well (do the upper net layers want or support | ||
1509 | * this kind of feature?). | ||
1510 | */ | ||
1511 | |||
1512 | static void set_multicast_list(struct net_device *dev) | ||
1513 | { | ||
1514 | struct fec_enet_private *fep; | ||
1515 | volatile fec_t *ep; | ||
1516 | |||
1517 | fep = (struct fec_enet_private *)dev->priv; | ||
1518 | ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec); | ||
1519 | |||
1520 | if (dev->flags&IFF_PROMISC) { | ||
1521 | |||
1522 | /* Log any net taps. */ | ||
1523 | printk("%s: Promiscuous mode enabled.\n", dev->name); | ||
1524 | ep->fec_r_cntrl |= FEC_RCNTRL_PROM; | ||
1525 | } else { | ||
1526 | |||
1527 | ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM; | ||
1528 | |||
1529 | if (dev->flags & IFF_ALLMULTI) { | ||
1530 | /* Catch all multicast addresses, so set the | ||
1531 | * filter to all 1's. | ||
1532 | */ | ||
1533 | ep->fec_hash_table_high = 0xffffffff; | ||
1534 | ep->fec_hash_table_low = 0xffffffff; | ||
1535 | } | ||
1536 | #if 0 | ||
1537 | else { | ||
1538 | /* Clear filter and add the addresses in the list. | ||
1539 | */ | ||
1540 | ep->sen_gaddr1 = 0; | ||
1541 | ep->sen_gaddr2 = 0; | ||
1542 | ep->sen_gaddr3 = 0; | ||
1543 | ep->sen_gaddr4 = 0; | ||
1544 | |||
1545 | dmi = dev->mc_list; | ||
1546 | |||
1547 | for (i=0; i<dev->mc_count; i++) { | ||
1548 | |||
1549 | /* Only support group multicast for now. | ||
1550 | */ | ||
1551 | if (!(dmi->dmi_addr[0] & 1)) | ||
1552 | continue; | ||
1553 | |||
1554 | /* The address in dmi_addr is LSB first, | ||
1555 | * and taddr is MSB first. We have to | ||
1556 | * copy bytes MSB first from dmi_addr. | ||
1557 | */ | ||
1558 | mcptr = (u_char *)dmi->dmi_addr + 5; | ||
1559 | tdptr = (u_char *)&ep->sen_taddrh; | ||
1560 | for (j=0; j<6; j++) | ||
1561 | *tdptr++ = *mcptr--; | ||
1562 | |||
1563 | /* Ask CPM to run CRC and set bit in | ||
1564 | * filter mask. | ||
1565 | */ | ||
1566 | cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG; | ||
1567 | /* this delay is necessary here -- Cort */ | ||
1568 | udelay(10); | ||
1569 | while (cpmp->cp_cpcr & CPM_CR_FLG); | ||
1570 | } | ||
1571 | } | ||
1572 | #endif | ||
1573 | } | ||
1574 | } | ||
1575 | |||
1576 | /* Initialize the FEC Ethernet on 860T. | ||
1577 | */ | ||
1578 | static int __init fec_enet_init(void) | ||
1579 | { | ||
1580 | struct net_device *dev; | ||
1581 | struct fec_enet_private *fep; | ||
1582 | int i, j, k, err; | ||
1583 | unsigned char *eap, *iap, *ba; | ||
1584 | dma_addr_t mem_addr; | ||
1585 | volatile cbd_t *bdp; | ||
1586 | cbd_t *cbd_base; | ||
1587 | volatile immap_t *immap; | ||
1588 | volatile fec_t *fecp; | ||
1589 | bd_t *bd; | ||
1590 | #ifdef CONFIG_SCC_ENET | ||
1591 | unsigned char tmpaddr[6]; | ||
1592 | #endif | ||
1593 | |||
1594 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | ||
1595 | |||
1596 | bd = (bd_t *)__res; | ||
1597 | |||
1598 | dev = alloc_etherdev(sizeof(*fep)); | ||
1599 | if (!dev) | ||
1600 | return -ENOMEM; | ||
1601 | |||
1602 | fep = dev->priv; | ||
1603 | |||
1604 | fecp = &(immap->im_cpm.cp_fec); | ||
1605 | |||
1606 | /* Whack a reset. We should wait for this. | ||
1607 | */ | ||
1608 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; | ||
1609 | for (i = 0; | ||
1610 | (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); | ||
1611 | ++i) { | ||
1612 | udelay(1); | ||
1613 | } | ||
1614 | if (i == FEC_RESET_DELAY) { | ||
1615 | printk ("FEC Reset timeout!\n"); | ||
1616 | } | ||
1617 | |||
1618 | /* Set the Ethernet address. If using multiple Enets on the 8xx, | ||
1619 | * this needs some work to get unique addresses. | ||
1620 | */ | ||
1621 | eap = (unsigned char *)my_enet_addr; | ||
1622 | iap = bd->bi_enetaddr; | ||
1623 | |||
1624 | #ifdef CONFIG_SCC_ENET | ||
1625 | /* | ||
1626 | * If a board has Ethernet configured both on a SCC and the | ||
1627 | * FEC, it needs (at least) 2 MAC addresses (we know that Sun | ||
1628 | * disagrees, but anyway). For the FEC port, we create | ||
1629 | * another address by setting one of the address bits above | ||
1630 | * something that would have (up to now) been allocated. | ||
1631 | */ | ||
1632 | for (i=0; i<6; i++) | ||
1633 | tmpaddr[i] = *iap++; | ||
1634 | tmpaddr[3] |= 0x80; | ||
1635 | iap = tmpaddr; | ||
1636 | #endif | ||
1637 | |||
1638 | for (i=0; i<6; i++) { | ||
1639 | dev->dev_addr[i] = *eap++ = *iap++; | ||
1640 | } | ||
1641 | |||
1642 | /* Allocate memory for buffer descriptors. | ||
1643 | */ | ||
1644 | if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) { | ||
1645 | printk("FEC init error. Need more space.\n"); | ||
1646 | printk("FEC initialization failed.\n"); | ||
1647 | return 1; | ||
1648 | } | ||
1649 | cbd_base = (cbd_t *)dma_alloc_coherent(dev->class_dev.dev, PAGE_SIZE, | ||
1650 | &mem_addr, GFP_KERNEL); | ||
1651 | |||
1652 | /* Set receive and transmit descriptor base. | ||
1653 | */ | ||
1654 | fep->rx_bd_base = cbd_base; | ||
1655 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | ||
1656 | |||
1657 | fep->skb_cur = fep->skb_dirty = 0; | ||
1658 | |||
1659 | /* Initialize the receive buffer descriptors. | ||
1660 | */ | ||
1661 | bdp = fep->rx_bd_base; | ||
1662 | k = 0; | ||
1663 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | ||
1664 | |||
1665 | /* Allocate a page. | ||
1666 | */ | ||
1667 | ba = (unsigned char *)dma_alloc_coherent(dev->class_dev.dev, | ||
1668 | PAGE_SIZE, | ||
1669 | &mem_addr, | ||
1670 | GFP_KERNEL); | ||
1671 | /* BUG: no check for failure */ | ||
1672 | |||
1673 | /* Initialize the BD for every fragment in the page. | ||
1674 | */ | ||
1675 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { | ||
1676 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | ||
1677 | bdp->cbd_bufaddr = mem_addr; | ||
1678 | fep->rx_vaddr[k++] = ba; | ||
1679 | mem_addr += FEC_ENET_RX_FRSIZE; | ||
1680 | ba += FEC_ENET_RX_FRSIZE; | ||
1681 | bdp++; | ||
1682 | } | ||
1683 | } | ||
1684 | |||
1685 | /* Set the last buffer to wrap. | ||
1686 | */ | ||
1687 | bdp--; | ||
1688 | bdp->cbd_sc |= BD_SC_WRAP; | ||
1689 | |||
1690 | #ifdef CONFIG_FEC_PACKETHOOK | ||
1691 | fep->ph_lock = 0; | ||
1692 | fep->ph_rxhandler = fep->ph_txhandler = NULL; | ||
1693 | fep->ph_proto = 0; | ||
1694 | fep->ph_regaddr = NULL; | ||
1695 | fep->ph_priv = NULL; | ||
1696 | #endif | ||
1697 | |||
1698 | /* Install our interrupt handler. | ||
1699 | */ | ||
1700 | if (request_irq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0) | ||
1701 | panic("Could not allocate FEC IRQ!"); | ||
1702 | |||
1703 | #ifdef CONFIG_RPXCLASSIC | ||
1704 | /* Make Port C, bit 15 an input that causes interrupts. | ||
1705 | */ | ||
1706 | immap->im_ioport.iop_pcpar &= ~0x0001; | ||
1707 | immap->im_ioport.iop_pcdir &= ~0x0001; | ||
1708 | immap->im_ioport.iop_pcso &= ~0x0001; | ||
1709 | immap->im_ioport.iop_pcint |= 0x0001; | ||
1710 | cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev); | ||
1711 | |||
1712 | /* Make LEDS reflect Link status. | ||
1713 | */ | ||
1714 | *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE; | ||
1715 | #endif | ||
1716 | |||
1717 | #ifdef PHY_INTERRUPT | ||
1718 | ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |= | ||
1719 | (0x80000000 >> PHY_INTERRUPT); | ||
1720 | |||
1721 | if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0) | ||
1722 | panic("Could not allocate MII IRQ!"); | ||
1723 | #endif | ||
1724 | |||
1725 | dev->base_addr = (unsigned long)fecp; | ||
1726 | |||
1727 | /* The FEC Ethernet specific entries in the device structure. */ | ||
1728 | dev->open = fec_enet_open; | ||
1729 | dev->hard_start_xmit = fec_enet_start_xmit; | ||
1730 | dev->tx_timeout = fec_timeout; | ||
1731 | dev->watchdog_timeo = TX_TIMEOUT; | ||
1732 | dev->stop = fec_enet_close; | ||
1733 | dev->get_stats = fec_enet_get_stats; | ||
1734 | dev->set_multicast_list = set_multicast_list; | ||
1735 | |||
1736 | #ifdef CONFIG_USE_MDIO | ||
1737 | for (i=0; i<NMII-1; i++) | ||
1738 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | ||
1739 | mii_free = mii_cmds; | ||
1740 | #endif /* CONFIG_USE_MDIO */ | ||
1741 | |||
1742 | /* Configure all of port D for MII. | ||
1743 | */ | ||
1744 | immap->im_ioport.iop_pdpar = 0x1fff; | ||
1745 | |||
1746 | /* Bits moved from Rev. D onward. | ||
1747 | */ | ||
1748 | if ((mfspr(SPRN_IMMR) & 0xffff) < 0x0501) | ||
1749 | immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ | ||
1750 | else | ||
1751 | immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ | ||
1752 | |||
1753 | #ifdef CONFIG_USE_MDIO | ||
1754 | /* Set MII speed to 2.5 MHz | ||
1755 | */ | ||
1756 | fecp->fec_mii_speed = fep->phy_speed = | ||
1757 | (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1; | ||
1758 | #else | ||
1759 | fecp->fec_mii_speed = 0; /* turn off MDIO */ | ||
1760 | #endif /* CONFIG_USE_MDIO */ | ||
1761 | |||
1762 | err = register_netdev(dev); | ||
1763 | if (err) { | ||
1764 | free_netdev(dev); | ||
1765 | return err; | ||
1766 | } | ||
1767 | |||
1768 | printk ("%s: FEC ENET Version 0.2, FEC irq %d" | ||
1769 | #ifdef PHY_INTERRUPT | ||
1770 | ", MII irq %d" | ||
1771 | #endif | ||
1772 | ", addr ", | ||
1773 | dev->name, FEC_INTERRUPT | ||
1774 | #ifdef PHY_INTERRUPT | ||
1775 | , PHY_INTERRUPT | ||
1776 | #endif | ||
1777 | ); | ||
1778 | for (i=0; i<6; i++) | ||
1779 | printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':'); | ||
1780 | |||
1781 | #ifdef CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */ | ||
1782 | fec_restart (dev, 1); | ||
1783 | #else /* always use half duplex mode only */ | ||
1784 | fec_restart (dev, 0); | ||
1785 | #endif | ||
1786 | |||
1787 | #ifdef CONFIG_USE_MDIO | ||
1788 | /* Queue up command to detect the PHY and initialize the | ||
1789 | * remainder of the interface. | ||
1790 | */ | ||
1791 | fep->phy_id_done = 0; | ||
1792 | fep->phy_addr = 0; | ||
1793 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | ||
1794 | #endif /* CONFIG_USE_MDIO */ | ||
1795 | |||
1796 | return 0; | ||
1797 | } | ||
1798 | module_init(fec_enet_init); | ||
1799 | |||
1800 | /* This function is called to start or restart the FEC during a link | ||
1801 | * change. This only happens when switching between half and full | ||
1802 | * duplex. | ||
1803 | */ | ||
1804 | static void | ||
1805 | fec_restart(struct net_device *dev, int duplex) | ||
1806 | { | ||
1807 | struct fec_enet_private *fep; | ||
1808 | int i; | ||
1809 | volatile cbd_t *bdp; | ||
1810 | volatile immap_t *immap; | ||
1811 | volatile fec_t *fecp; | ||
1812 | |||
1813 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | ||
1814 | |||
1815 | fecp = &(immap->im_cpm.cp_fec); | ||
1816 | |||
1817 | fep = dev->priv; | ||
1818 | |||
1819 | /* Whack a reset. We should wait for this. | ||
1820 | */ | ||
1821 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; | ||
1822 | for (i = 0; | ||
1823 | (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); | ||
1824 | ++i) { | ||
1825 | udelay(1); | ||
1826 | } | ||
1827 | if (i == FEC_RESET_DELAY) { | ||
1828 | printk ("FEC Reset timeout!\n"); | ||
1829 | } | ||
1830 | |||
1831 | /* Set station address. | ||
1832 | */ | ||
1833 | fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1]; | ||
1834 | fecp->fec_addr_high = my_enet_addr[2]; | ||
1835 | |||
1836 | /* Reset all multicast. | ||
1837 | */ | ||
1838 | fecp->fec_hash_table_high = 0; | ||
1839 | fecp->fec_hash_table_low = 0; | ||
1840 | |||
1841 | /* Set maximum receive buffer size. | ||
1842 | */ | ||
1843 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | ||
1844 | fecp->fec_r_hash = PKT_MAXBUF_SIZE; | ||
1845 | |||
1846 | /* Set receive and transmit descriptor base. | ||
1847 | */ | ||
1848 | fecp->fec_r_des_start = iopa((uint)(fep->rx_bd_base)); | ||
1849 | fecp->fec_x_des_start = iopa((uint)(fep->tx_bd_base)); | ||
1850 | |||
1851 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | ||
1852 | fep->cur_rx = fep->rx_bd_base; | ||
1853 | |||
1854 | /* Reset SKB transmit buffers. | ||
1855 | */ | ||
1856 | fep->skb_cur = fep->skb_dirty = 0; | ||
1857 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | ||
1858 | if (fep->tx_skbuff[i] != NULL) { | ||
1859 | dev_kfree_skb(fep->tx_skbuff[i]); | ||
1860 | fep->tx_skbuff[i] = NULL; | ||
1861 | } | ||
1862 | } | ||
1863 | |||
1864 | /* Initialize the receive buffer descriptors. | ||
1865 | */ | ||
1866 | bdp = fep->rx_bd_base; | ||
1867 | for (i=0; i<RX_RING_SIZE; i++) { | ||
1868 | |||
1869 | /* Initialize the BD for every fragment in the page. | ||
1870 | */ | ||
1871 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | ||
1872 | bdp++; | ||
1873 | } | ||
1874 | |||
1875 | /* Set the last buffer to wrap. | ||
1876 | */ | ||
1877 | bdp--; | ||
1878 | bdp->cbd_sc |= BD_SC_WRAP; | ||
1879 | |||
1880 | /* ...and the same for transmit. | ||
1881 | */ | ||
1882 | bdp = fep->tx_bd_base; | ||
1883 | for (i=0; i<TX_RING_SIZE; i++) { | ||
1884 | |||
1885 | /* Initialize the BD for every fragment in the page. | ||
1886 | */ | ||
1887 | bdp->cbd_sc = 0; | ||
1888 | bdp->cbd_bufaddr = 0; | ||
1889 | bdp++; | ||
1890 | } | ||
1891 | |||
1892 | /* Set the last buffer to wrap. | ||
1893 | */ | ||
1894 | bdp--; | ||
1895 | bdp->cbd_sc |= BD_SC_WRAP; | ||
1896 | |||
1897 | /* Enable MII mode. | ||
1898 | */ | ||
1899 | if (duplex) { | ||
1900 | fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; /* MII enable */ | ||
1901 | fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; /* FD enable */ | ||
1902 | } | ||
1903 | else { | ||
1904 | fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; | ||
1905 | fecp->fec_x_cntrl = 0; | ||
1906 | } | ||
1907 | fep->full_duplex = duplex; | ||
1908 | |||
1909 | /* Enable big endian and don't care about SDMA FC. | ||
1910 | */ | ||
1911 | fecp->fec_fun_code = 0x78000000; | ||
1912 | |||
1913 | #ifdef CONFIG_USE_MDIO | ||
1914 | /* Set MII speed. | ||
1915 | */ | ||
1916 | fecp->fec_mii_speed = fep->phy_speed; | ||
1917 | #endif /* CONFIG_USE_MDIO */ | ||
1918 | |||
1919 | /* Clear any outstanding interrupt. | ||
1920 | */ | ||
1921 | fecp->fec_ievent = 0xffc0; | ||
1922 | |||
1923 | fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; | ||
1924 | |||
1925 | /* Enable interrupts we wish to service. | ||
1926 | */ | ||
1927 | fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB | | ||
1928 | FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII ); | ||
1929 | |||
1930 | /* And last, enable the transmit and receive processing. | ||
1931 | */ | ||
1932 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; | ||
1933 | fecp->fec_r_des_active = 0x01000000; | ||
1934 | } | ||
1935 | |||
1936 | static void | ||
1937 | fec_stop(struct net_device *dev) | ||
1938 | { | ||
1939 | volatile immap_t *immap; | ||
1940 | volatile fec_t *fecp; | ||
1941 | struct fec_enet_private *fep; | ||
1942 | int i; | ||
1943 | |||
1944 | immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */ | ||
1945 | |||
1946 | fecp = &(immap->im_cpm.cp_fec); | ||
1947 | |||
1948 | if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0) | ||
1949 | return; /* already down */ | ||
1950 | |||
1951 | fep = dev->priv; | ||
1952 | |||
1953 | |||
1954 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ | ||
1955 | |||
1956 | for (i = 0; | ||
1957 | ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY); | ||
1958 | ++i) { | ||
1959 | udelay(1); | ||
1960 | } | ||
1961 | if (i == FEC_RESET_DELAY) { | ||
1962 | printk ("FEC timeout on graceful transmit stop\n"); | ||
1963 | } | ||
1964 | |||
1965 | /* Clear outstanding MII command interrupts. | ||
1966 | */ | ||
1967 | fecp->fec_ievent = FEC_ENET_MII; | ||
1968 | |||
1969 | /* Enable MII command finished interrupt | ||
1970 | */ | ||
1971 | fecp->fec_ivec = (FEC_INTERRUPT/2) << 29; | ||
1972 | fecp->fec_imask = FEC_ENET_MII; | ||
1973 | |||
1974 | #ifdef CONFIG_USE_MDIO | ||
1975 | /* Set MII speed. | ||
1976 | */ | ||
1977 | fecp->fec_mii_speed = fep->phy_speed; | ||
1978 | #endif /* CONFIG_USE_MDIO */ | ||
1979 | |||
1980 | /* Disable FEC | ||
1981 | */ | ||
1982 | fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN); | ||
1983 | } | ||