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-rw-r--r--arch/powerpc/sysdev/mpc8xxx_gpio.c395
1 files changed, 395 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
new file mode 100644
index 00000000000..fb4963abdf5
--- /dev/null
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -0,0 +1,395 @@
1/*
2 * GPIOs on MPC512x/8349/8572/8610 and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/gpio.h>
18#include <linux/slab.h>
19#include <linux/irq.h>
20
21#define MPC8XXX_GPIO_PINS 32
22
23#define GPIO_DIR 0x00
24#define GPIO_ODR 0x04
25#define GPIO_DAT 0x08
26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14
29#define GPIO_ICR2 0x18
30
31struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
34
35 /*
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
38 */
39 u32 data;
40 struct irq_host *irq;
41 void *of_dev_id_data;
42};
43
44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
45{
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
47}
48
49static inline struct mpc8xxx_gpio_chip *
50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
51{
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
53}
54
55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
56{
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
58
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60}
61
62/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
66 */
67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68{
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
72
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
74
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
76}
77
78static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
79{
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
81
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
83}
84
85static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
89 unsigned long flags;
90
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
92
93 if (val)
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
95 else
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
97
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
99
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
101}
102
103static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
104{
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107 unsigned long flags;
108
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
110
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
112
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
114
115 return 0;
116}
117
118static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
119{
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122 unsigned long flags;
123
124 mpc8xxx_gpio_set(gc, gpio, val);
125
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
127
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
129
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131
132 return 0;
133}
134
135static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
136{
137 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
138 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
139
140 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
141 return irq_create_mapping(mpc8xxx_gc->irq, offset);
142 else
143 return -ENXIO;
144}
145
146static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
147{
148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
149 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
150 unsigned int mask;
151
152 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
153 if (mask)
154 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
155 32 - ffs(mask)));
156}
157
158static void mpc8xxx_irq_unmask(struct irq_data *d)
159{
160 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
161 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
162 unsigned long flags;
163
164 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
165
166 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
167
168 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
169}
170
171static void mpc8xxx_irq_mask(struct irq_data *d)
172{
173 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
174 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
175 unsigned long flags;
176
177 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
178
179 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
180
181 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
182}
183
184static void mpc8xxx_irq_ack(struct irq_data *d)
185{
186 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
187 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
188
189 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
190}
191
192static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
193{
194 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
195 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
196 unsigned long flags;
197
198 switch (flow_type) {
199 case IRQ_TYPE_EDGE_FALLING:
200 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
201 setbits32(mm->regs + GPIO_ICR,
202 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
203 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
204 break;
205
206 case IRQ_TYPE_EDGE_BOTH:
207 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
208 clrbits32(mm->regs + GPIO_ICR,
209 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
210 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
211 break;
212
213 default:
214 return -EINVAL;
215 }