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Diffstat (limited to 'arch/powerpc/platforms/powernv/pci.h')
-rw-r--r--arch/powerpc/platforms/powernv/pci.h21
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 8bc47963464..7cfb7c883de 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -17,9 +17,14 @@ enum pnv_phb_model {
17}; 17};
18 18
19#define PNV_PCI_DIAG_BUF_SIZE 4096 19#define PNV_PCI_DIAG_BUF_SIZE 4096
20#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
21#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
22#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
20 23
21/* Data associated with a PE, including IOMMU tracking etc.. */ 24/* Data associated with a PE, including IOMMU tracking etc.. */
22struct pnv_ioda_pe { 25struct pnv_ioda_pe {
26 unsigned long flags;
27
23 /* A PE can be associated with a single device or an 28 /* A PE can be associated with a single device or an
24 * entire bus (& children). In the former case, pdev 29 * entire bus (& children). In the former case, pdev
25 * is populated, in the later case, pbus is. 30 * is populated, in the later case, pbus is.
@@ -40,11 +45,6 @@ struct pnv_ioda_pe {
40 */ 45 */
41 unsigned int dma_weight; 46 unsigned int dma_weight;
42 47
43 /* This is a PCI-E -> PCI-X bridge, this points to the
44 * corresponding bus PE
45 */
46 struct pnv_ioda_pe *bus_pe;
47
48 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 48 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
49 int tce32_seg; 49 int tce32_seg;
50 int tce32_segcount; 50 int tce32_segcount;
@@ -59,7 +59,8 @@ struct pnv_ioda_pe {
59 int mve_number; 59 int mve_number;
60 60
61 /* Link in list of PE#s */ 61 /* Link in list of PE#s */
62 struct list_head link; 62 struct list_head dma_link;
63 struct list_head list;
63}; 64};
64 65
65struct pnv_phb { 66struct pnv_phb {
@@ -68,6 +69,7 @@ struct pnv_phb {
68 enum pnv_phb_model model; 69 enum pnv_phb_model model;
69 u64 opal_id; 70 u64 opal_id;
70 void __iomem *regs; 71 void __iomem *regs;
72 int initialized;
71 spinlock_t lock; 73 spinlock_t lock;
72 74
73#ifdef CONFIG_PCI_MSI 75#ifdef CONFIG_PCI_MSI
@@ -107,6 +109,11 @@ struct pnv_phb {
107 unsigned int *io_segmap; 109 unsigned int *io_segmap;
108 struct pnv_ioda_pe *pe_array; 110 struct pnv_ioda_pe *pe_array;
109 111
112 /* Sorted list of used PE's based
113 * on the sequence of creation
114 */
115 struct list_head pe_list;
116
110 /* Reverse map of PEs, will have to extend if 117 /* Reverse map of PEs, will have to extend if
111 * we are to support more than 256 PEs, indexed 118 * we are to support more than 256 PEs, indexed
112 * bus { bus, devfn } 119 * bus { bus, devfn }
@@ -125,7 +132,7 @@ struct pnv_phb {
125 /* Sorted list of used PE's, sorted at 132 /* Sorted list of used PE's, sorted at
126 * boot for resource allocation purposes 133 * boot for resource allocation purposes
127 */ 134 */
128 struct list_head pe_list; 135 struct list_head pe_dma_list;
129 } ioda; 136 } ioda;
130 }; 137 };
131 138