diff options
Diffstat (limited to 'arch/powerpc/platforms/85xx/mpc85xx_mds.c')
-rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_mds.c | 279 |
1 files changed, 162 insertions, 117 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 494513682d7..da64be19d09 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c | |||
@@ -158,51 +158,108 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev) | |||
158 | extern void __init mpc85xx_smp_init(void); | 158 | extern void __init mpc85xx_smp_init(void); |
159 | #endif | 159 | #endif |
160 | 160 | ||
161 | static void __init mpc85xx_mds_setup_arch(void) | 161 | #ifdef CONFIG_QUICC_ENGINE |
162 | static struct of_device_id mpc85xx_qe_ids[] __initdata = { | ||
163 | { .type = "qe", }, | ||
164 | { .compatible = "fsl,qe", }, | ||
165 | { }, | ||
166 | }; | ||
167 | |||
168 | static void __init mpc85xx_publish_qe_devices(void) | ||
162 | { | 169 | { |
163 | struct device_node *np; | 170 | struct device_node *np; |
164 | static u8 __iomem *bcsr_regs = NULL; | ||
165 | #ifdef CONFIG_PCI | ||
166 | struct pci_controller *hose; | ||
167 | #endif | ||
168 | dma_addr_t max = 0xffffffff; | ||
169 | 171 | ||
170 | if (ppc_md.progress) | 172 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); |
171 | ppc_md.progress("mpc85xx_mds_setup_arch()", 0); | 173 | if (!of_device_is_available(np)) { |
174 | of_node_put(np); | ||
175 | return; | ||
176 | } | ||
177 | |||
178 | of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL); | ||
179 | } | ||
180 | |||
181 | static void __init mpc85xx_mds_reset_ucc_phys(void) | ||
182 | { | ||
183 | struct device_node *np; | ||
184 | static u8 __iomem *bcsr_regs; | ||
172 | 185 | ||
173 | /* Map BCSR area */ | 186 | /* Map BCSR area */ |
174 | np = of_find_node_by_name(NULL, "bcsr"); | 187 | np = of_find_node_by_name(NULL, "bcsr"); |
175 | if (np != NULL) { | 188 | if (!np) |
176 | struct resource res; | 189 | return; |
177 | 190 | ||
178 | of_address_to_resource(np, 0, &res); | 191 | bcsr_regs = of_iomap(np, 0); |
179 | bcsr_regs = ioremap(res.start, res.end - res.start +1); | 192 | of_node_put(np); |
180 | of_node_put(np); | 193 | if (!bcsr_regs) |
181 | } | 194 | return; |
182 | 195 | ||
183 | #ifdef CONFIG_PCI | 196 | if (machine_is(mpc8568_mds)) { |
184 | for_each_node_by_type(np, "pci") { | 197 | #define BCSR_UCC1_GETH_EN (0x1 << 7) |
185 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | 198 | #define BCSR_UCC2_GETH_EN (0x1 << 7) |
186 | of_device_is_compatible(np, "fsl,mpc8548-pcie")) { | 199 | #define BCSR_UCC1_MODE_MSK (0x3 << 4) |
187 | struct resource rsrc; | 200 | #define BCSR_UCC2_MODE_MSK (0x3 << 0) |
188 | of_address_to_resource(np, 0, &rsrc); | ||
189 | if ((rsrc.start & 0xfffff) == 0x8000) | ||
190 | fsl_add_bridge(np, 1); | ||
191 | else | ||
192 | fsl_add_bridge(np, 0); | ||
193 | 201 | ||
194 | hose = pci_find_hose_for_OF_device(np); | 202 | /* Turn off UCC1 & UCC2 */ |
195 | max = min(max, hose->dma_window_base_cur + | 203 | clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); |
196 | hose->dma_window_size); | 204 | clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); |
205 | |||
206 | /* Mode is RGMII, all bits clear */ | ||
207 | clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | | ||
208 | BCSR_UCC2_MODE_MSK); | ||
209 | |||
210 | /* Turn UCC1 & UCC2 on */ | ||
211 | setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | ||
212 | setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | ||
213 | } else if (machine_is(mpc8569_mds)) { | ||
214 | #define BCSR7_UCC12_GETHnRST (0x1 << 2) | ||
215 | #define BCSR8_UEM_MARVELL_RST (0x1 << 1) | ||
216 | #define BCSR_UCC_RGMII (0x1 << 6) | ||
217 | #define BCSR_UCC_RTBI (0x1 << 5) | ||
218 | /* | ||
219 | * U-Boot mangles interrupt polarity for Marvell PHYs, | ||
220 | * so reset built-in and UEM Marvell PHYs, this puts | ||
221 | * the PHYs into their normal state. | ||
222 | */ | ||
223 | clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); | ||
224 | setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); | ||
225 | |||
226 | setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); | ||
227 | clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); | ||
228 | |||
229 | for (np = NULL; (np = of_find_compatible_node(np, | ||
230 | "network", | ||
231 | "ucc_geth")) != NULL;) { | ||
232 | const unsigned int *prop; | ||
233 | int ucc_num; | ||
234 | |||
235 | prop = of_get_property(np, "cell-index", NULL); | ||
236 | if (prop == NULL) | ||
237 | continue; | ||
238 | |||
239 | ucc_num = *prop - 1; | ||
240 | |||
241 | prop = of_get_property(np, "phy-connection-type", NULL); | ||
242 | if (prop == NULL) | ||
243 | continue; | ||
244 | |||
245 | if (strcmp("rtbi", (const char *)prop) == 0) | ||
246 | clrsetbits_8(&bcsr_regs[7 + ucc_num], | ||
247 | BCSR_UCC_RGMII, BCSR_UCC_RTBI); | ||
197 | } | 248 | } |
249 | } else if (machine_is(p1021_mds)) { | ||
250 | #define BCSR11_ENET_MICRST (0x1 << 5) | ||
251 | /* Reset Micrel PHY */ | ||
252 | clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); | ||
253 | setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); | ||
198 | } | 254 | } |
199 | #endif | ||
200 | 255 | ||
201 | #ifdef CONFIG_SMP | 256 | iounmap(bcsr_regs); |
202 | mpc85xx_smp_init(); | 257 | } |
203 | #endif | 258 | |
259 | static void __init mpc85xx_mds_qe_init(void) | ||
260 | { | ||
261 | struct device_node *np; | ||
204 | 262 | ||
205 | #ifdef CONFIG_QUICC_ENGINE | ||
206 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); | 263 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); |
207 | if (!np) { | 264 | if (!np) { |
208 | np = of_find_node_by_name(NULL, "qe"); | 265 | np = of_find_node_by_name(NULL, "qe"); |
@@ -210,6 +267,11 @@ static void __init mpc85xx_mds_setup_arch(void) | |||
210 | return; | 267 | return; |
211 | } | 268 | } |
212 | 269 | ||
270 | if (!of_device_is_available(np)) { | ||
271 | of_node_put(np); | ||
272 | return; | ||
273 | } | ||
274 | |||
213 | qe_reset(); | 275 | qe_reset(); |
214 | of_node_put(np); | 276 | of_node_put(np); |
215 | 277 | ||
@@ -224,70 +286,7 @@ static void __init mpc85xx_mds_setup_arch(void) | |||
224 | par_io_of_config(ucc); | 286 | par_io_of_config(ucc); |
225 | } | 287 | } |
226 | 288 | ||
227 | if (bcsr_regs) { | 289 | mpc85xx_mds_reset_ucc_phys(); |
228 | if (machine_is(mpc8568_mds)) { | ||
229 | #define BCSR_UCC1_GETH_EN (0x1 << 7) | ||
230 | #define BCSR_UCC2_GETH_EN (0x1 << 7) | ||
231 | #define BCSR_UCC1_MODE_MSK (0x3 << 4) | ||
232 | #define BCSR_UCC2_MODE_MSK (0x3 << 0) | ||
233 | |||
234 | /* Turn off UCC1 & UCC2 */ | ||
235 | clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | ||
236 | clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | ||
237 | |||
238 | /* Mode is RGMII, all bits clear */ | ||
239 | clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | | ||
240 | BCSR_UCC2_MODE_MSK); | ||
241 | |||
242 | /* Turn UCC1 & UCC2 on */ | ||
243 | setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); | ||
244 | setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); | ||
245 | } else if (machine_is(mpc8569_mds)) { | ||
246 | #define BCSR7_UCC12_GETHnRST (0x1 << 2) | ||
247 | #define BCSR8_UEM_MARVELL_RST (0x1 << 1) | ||
248 | #define BCSR_UCC_RGMII (0x1 << 6) | ||
249 | #define BCSR_UCC_RTBI (0x1 << 5) | ||
250 | /* | ||
251 | * U-Boot mangles interrupt polarity for Marvell PHYs, | ||
252 | * so reset built-in and UEM Marvell PHYs, this puts | ||
253 | * the PHYs into their normal state. | ||
254 | */ | ||
255 | clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); | ||
256 | setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); | ||
257 | |||
258 | setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); | ||
259 | clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); | ||
260 | |||
261 | for (np = NULL; (np = of_find_compatible_node(np, | ||
262 | "network", | ||
263 | "ucc_geth")) != NULL;) { | ||
264 | const unsigned int *prop; | ||
265 | int ucc_num; | ||
266 | |||
267 | prop = of_get_property(np, "cell-index", NULL); | ||
268 | if (prop == NULL) | ||
269 | continue; | ||
270 | |||
271 | ucc_num = *prop - 1; | ||
272 | |||
273 | prop = of_get_property(np, "phy-connection-type", NULL); | ||
274 | if (prop == NULL) | ||
275 | continue; | ||
276 | |||
277 | if (strcmp("rtbi", (const char *)prop) == 0) | ||
278 | clrsetbits_8(&bcsr_regs[7 + ucc_num], | ||
279 | BCSR_UCC_RGMII, BCSR_UCC_RTBI); | ||
280 | } | ||
281 | |||
282 | } else if (machine_is(p1021_mds)) { | ||
283 | #define BCSR11_ENET_MICRST (0x1 << 5) | ||
284 | /* Reset Micrel PHY */ | ||
285 | clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); | ||
286 | setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST); | ||
287 | } | ||
288 | |||
289 | iounmap(bcsr_regs); | ||
290 | } | ||
291 | 290 | ||
292 | if (machine_is(p1021_mds)) { | 291 | if (machine_is(p1021_mds)) { |
293 | #define MPC85xx_PMUXCR_OFFSET 0x60 | 292 | #define MPC85xx_PMUXCR_OFFSET 0x60 |
@@ -322,8 +321,72 @@ static void __init mpc85xx_mds_setup_arch(void) | |||
322 | } | 321 | } |
323 | 322 | ||
324 | } | 323 | } |
324 | } | ||
325 | |||
326 | static void __init mpc85xx_mds_qeic_init(void) | ||
327 | { | ||
328 | struct device_node *np; | ||
329 | |||
330 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); | ||
331 | if (!of_device_is_available(np)) { | ||
332 | of_node_put(np); | ||
333 | return; | ||
334 | } | ||
335 | |||
336 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | ||
337 | if (!np) { | ||
338 | np = of_find_node_by_type(NULL, "qeic"); | ||
339 | if (!np) | ||
340 | return; | ||
341 | } | ||
342 | |||
343 | if (machine_is(p1021_mds)) | ||
344 | qe_ic_init(np, 0, qe_ic_cascade_low_mpic, | ||
345 | qe_ic_cascade_high_mpic); | ||
346 | else | ||
347 | qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); | ||
348 | of_node_put(np); | ||
349 | } | ||
350 | #else | ||
351 | static void __init mpc85xx_publish_qe_devices(void) { } | ||
352 | static void __init mpc85xx_mds_qe_init(void) { } | ||
353 | static void __init mpc85xx_mds_qeic_init(void) { } | ||
325 | #endif /* CONFIG_QUICC_ENGINE */ | 354 | #endif /* CONFIG_QUICC_ENGINE */ |
326 | 355 | ||
356 | static void __init mpc85xx_mds_setup_arch(void) | ||
357 | { | ||
358 | #ifdef CONFIG_PCI | ||
359 | struct pci_controller *hose; | ||
360 | #endif | ||
361 | dma_addr_t max = 0xffffffff; | ||
362 | |||
363 | if (ppc_md.progress) | ||
364 | ppc_md.progress("mpc85xx_mds_setup_arch()", 0); | ||
365 | |||
366 | #ifdef CONFIG_PCI | ||
367 | for_each_node_by_type(np, "pci") { | ||
368 | if (of_device_is_compatible(np, "fsl,mpc8540-pci") || | ||
369 | of_device_is_compatible(np, "fsl,mpc8548-pcie")) { | ||
370 | struct resource rsrc; | ||
371 | of_address_to_resource(np, 0, &rsrc); | ||
372 | if ((rsrc.start & 0xfffff) == 0x8000) | ||
373 | fsl_add_bridge(np, 1); | ||
374 | else | ||
375 | fsl_add_bridge(np, 0); | ||
376 | |||
377 | hose = pci_find_hose_for_OF_device(np); | ||
378 | max = min(max, hose->dma_window_base_cur + | ||
379 | hose->dma_window_size); | ||
380 | } | ||
381 | } | ||
382 | #endif | ||
383 | |||
384 | #ifdef CONFIG_SMP | ||
385 | mpc85xx_smp_init(); | ||
386 | #endif | ||
387 | |||
388 | mpc85xx_mds_qe_init(); | ||
389 | |||
327 | #ifdef CONFIG_SWIOTLB | 390 | #ifdef CONFIG_SWIOTLB |
328 | if (memblock_end_of_DRAM() > max) { | 391 | if (memblock_end_of_DRAM() > max) { |
329 | ppc_swiotlb_enable = 1; | 392 | ppc_swiotlb_enable = 1; |
@@ -369,8 +432,6 @@ static struct of_device_id mpc85xx_ids[] = { | |||
369 | { .type = "soc", }, | 432 | { .type = "soc", }, |
370 | { .compatible = "soc", }, | 433 | { .compatible = "soc", }, |
371 | { .compatible = "simple-bus", }, | 434 | { .compatible = "simple-bus", }, |
372 | { .type = "qe", }, | ||
373 | { .compatible = "fsl,qe", }, | ||
374 | { .compatible = "gianfar", }, | 435 | { .compatible = "gianfar", }, |
375 | { .compatible = "fsl,rapidio-delta", }, | 436 | { .compatible = "fsl,rapidio-delta", }, |
376 | { .compatible = "fsl,mpc8548-guts", }, | 437 | { .compatible = "fsl,mpc8548-guts", }, |
@@ -382,8 +443,6 @@ static struct of_device_id p1021_ids[] = { | |||
382 | { .type = "soc", }, | 443 | { .type = "soc", }, |
383 | { .compatible = "soc", }, | 444 | { .compatible = "soc", }, |
384 | { .compatible = "simple-bus", }, | 445 | { .compatible = "simple-bus", }, |
385 | { .type = "qe", }, | ||
386 | { .compatible = "fsl,qe", }, | ||
387 | { .compatible = "gianfar", }, | 446 | { .compatible = "gianfar", }, |
388 | {}, | 447 | {}, |
389 | }; | 448 | }; |
@@ -395,16 +454,16 @@ static int __init mpc85xx_publish_devices(void) | |||
395 | if (machine_is(mpc8569_mds)) | 454 | if (machine_is(mpc8569_mds)) |
396 | simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); | 455 | simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio"); |
397 | 456 | ||
398 | /* Publish the QE devices */ | ||
399 | of_platform_bus_probe(NULL, mpc85xx_ids, NULL); | 457 | of_platform_bus_probe(NULL, mpc85xx_ids, NULL); |
458 | mpc85xx_publish_qe_devices(); | ||
400 | 459 | ||
401 | return 0; | 460 | return 0; |
402 | } | 461 | } |
403 | 462 | ||
404 | static int __init p1021_publish_devices(void) | 463 | static int __init p1021_publish_devices(void) |
405 | { | 464 | { |
406 | /* Publish the QE devices */ | ||
407 | of_platform_bus_probe(NULL, p1021_ids, NULL); | 465 | of_platform_bus_probe(NULL, p1021_ids, NULL); |
466 | mpc85xx_publish_qe_devices(); | ||
408 | 467 | ||
409 | return 0; | 468 | return 0; |
410 | } | 469 | } |
@@ -441,21 +500,7 @@ static void __init mpc85xx_mds_pic_init(void) | |||
441 | of_node_put(np); | 500 | of_node_put(np); |
442 | 501 | ||
443 | mpic_init(mpic); | 502 | mpic_init(mpic); |
444 | 503 | mpc85xx_mds_qeic_init(); | |
445 | #ifdef CONFIG_QUICC_ENGINE | ||
446 | np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); | ||
447 | if (!np) { | ||
448 | np = of_find_node_by_type(NULL, "qeic"); | ||
449 | if (!np) | ||
450 | return; | ||
451 | } | ||
452 | if (machine_is(p1021_mds)) | ||
453 | qe_ic_init(np, 0, qe_ic_cascade_low_mpic, | ||
454 | qe_ic_cascade_high_mpic); | ||
455 | else | ||
456 | qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); | ||
457 | of_node_put(np); | ||
458 | #endif /* CONFIG_QUICC_ENGINE */ | ||
459 | } | 504 | } |
460 | 505 | ||
461 | static int __init mpc85xx_mds_probe(void) | 506 | static int __init mpc85xx_mds_probe(void) |