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Diffstat (limited to 'arch/powerpc/platforms/52xx/mpc52xx_gpt.c')
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_gpt.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 2c3fa13571c..77572abca6c 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -378,12 +378,12 @@ EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
378/** 378/**
379 * mpc52xx_gpt_start_timer - Set and enable the GPT timer 379 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
380 * @gpt: Pointer to gpt private data structure 380 * @gpt: Pointer to gpt private data structure
381 * @period: period of timer 381 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
382 * @continuous: set to 1 to make timer continuous free running 382 * @continuous: set to 1 to make timer continuous free running
383 * 383 *
384 * An interrupt will be generated every time the timer fires 384 * An interrupt will be generated every time the timer fires
385 */ 385 */
386int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, int period, 386int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
387 int continuous) 387 int continuous)
388{ 388{
389 u32 clear, set; 389 u32 clear, set;
@@ -400,7 +400,7 @@ int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, int period,
400 * arithmatic is done here to preserve the precision until the value 400 * arithmatic is done here to preserve the precision until the value
401 * is scaled back down into the u32 range. Period is in 'ns', bus 401 * is scaled back down into the u32 range. Period is in 'ns', bus
402 * frequency is in Hz. */ 402 * frequency is in Hz. */
403 clocks = (u64)period * (u64)gpt->ipb_freq; 403 clocks = period * (u64)gpt->ipb_freq;
404 do_div(clocks, 1000000000); /* Scale it down to ns range */ 404 do_div(clocks, 1000000000); /* Scale it down to ns range */
405 405
406 /* This device cannot handle a clock count greater than 32 bits */ 406 /* This device cannot handle a clock count greater than 32 bits */