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-rw-r--r--arch/powerpc/boot/dts/socrates.dts338
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diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
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1/*
2 * Device Tree Source for the Socrates board (MPC8544).
3 *
4 * Copyright (c) 2008 Emcraft Systems.
5 * Sergei Poselenov, <sposelenov@emcraft.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "abb,socrates";
17 compatible = "abb,socrates";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8544@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>;
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
50 };
51
52 soc8544@e0000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55
56 ranges = <0x00000000 0xe0000000 0x00100000>;
57 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M
58 bus-frequency = <0>; // Filled in by U-Boot
59 compatible = "fsl,mpc8544-immr", "simple-bus";
60
61 memory-controller@2000 {
62 compatible = "fsl,mpc8544-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>;
66 };
67
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,mpc8544-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>;
72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>;
74 interrupts = <16 2>;
75 };
76
77 i2c@3000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c";
82 reg = <0x3000 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86
87 dtt@28 {
88 compatible = "winbond,w83782d";
89 reg = <0x28>;
90 };
91 rtc@32 {
92 compatible = "epson,rx8025";
93 reg = <0x32>;
94 interrupts = <7 1>;
95 interrupt-parent = <&mpic>;
96 };
97 dtt@4c {
98 compatible = "dallas,ds75";
99 reg = <0x4c>;
100 };
101 ts@4a {
102 compatible = "ti,tsc2003";
103 reg = <0x4a>;
104 interrupt-parent = <&mpic>;
105 interrupts = <8 1>;
106 };
107 };
108
109 i2c@3100 {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 cell-index = <1>;
113 compatible = "fsl-i2c";
114 reg = <0x3100 0x100>;
115 interrupts = <43 2>;
116 interrupt-parent = <&mpic>;
117 dfsrr;
118 };
119
120 enet0: ethernet@24000 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 cell-index = <0>;
124 device_type = "network";
125 model = "eTSEC";
126 compatible = "gianfar";
127 reg = <0x24000 0x1000>;
128 ranges = <0x0 0x24000 0x1000>;
129 local-mac-address = [ 00 00 00 00 00 00 ];
130 interrupts = <29 2 30 2 34 2>;
131 interrupt-parent = <&mpic>;
132 phy-handle = <&phy0>;
133 tbi-handle = <&tbi0>;
134 phy-connection-type = "rgmii-id";
135
136 mdio@520 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 compatible = "fsl,gianfar-mdio";
140 reg = <0x520 0x20>;
141
142 phy0: ethernet-phy@0 {
143 interrupt-parent = <&mpic>;
144 interrupts = <0 1>;
145 reg = <0>;
146 };
147 phy1: ethernet-phy@1 {
148 interrupt-parent = <&mpic>;
149 interrupts = <0 1>;
150 reg = <1>;
151 };
152 tbi0: tbi-phy@11 {
153 reg = <0x11>;
154 };
155 };
156 };
157
158 enet1: ethernet@26000 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 cell-index = <1>;
162 device_type = "network";
163 model = "eTSEC";
164 compatible = "gianfar";
165 reg = <0x26000 0x1000>;
166 ranges = <0x0 0x26000 0x1000>;
167 local-mac-address = [ 00 00 00 00 00 00 ];
168 interrupts = <31 2 32 2 33 2>;
169 interrupt-parent = <&mpic>;
170 phy-handle = <&phy1>;
171 tbi-handle = <&tbi1>;
172 phy-connection-type = "rgmii-id";
173
174 mdio@520 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,gianfar-tbi";
178 reg = <0x520 0x20>;
179
180 tbi1: tbi-phy@11 {
181 reg = <0x11>;
182 };
183 };
184 };
185
186 serial0: serial@4500 {
187 cell-index = <0>;
188 device_type = "serial";
189 compatible = "ns16550";
190 reg = <0x4500 0x100>;
191 clock-frequency = <0>;
192 interrupts = <42 2>;
193 interrupt-parent = <&mpic>;
194 };
195
196 serial1: serial@4600 {
197 cell-index = <1>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4600 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 global-utilities@e0000 { //global utilities block
207 compatible = "fsl,mpc8548-guts";
208 reg = <0xe0000 0x1000>;
209 fsl,has-rstcr;
210 };
211
212 mpic: pic@40000 {
213 interrupt-controller;
214 #address-cells = <0>;
215 #interrupt-cells = <2>;
216 reg = <0x40000 0x40000>;
217 compatible = "chrp,open-pic";
218 device_type = "open-pic";
219 };
220 };
221
222
223 localbus {
224 compatible = "fsl,mpc8544-localbus",
225 "fsl,pq3-localbus",
226 "simple-bus";
227 #address-cells = <2>;
228 #size-cells = <1>;
229 reg = <0xe0005000 0x40>;
230
231 ranges = <0 0 0xfc000000 0x04000000
232 2 0 0xc8000000 0x04000000
233 3 0 0xc0000000 0x00100000
234 >; /* Overwritten by U-Boot */
235
236 nor_flash@0,0 {
237 compatible = "amd,s29gl256n", "cfi-flash";
238 bank-width = <2>;
239 reg = <0x0 0x000000 0x4000000>;
240 #address-cells = <1>;
241 #size-cells = <1>;
242 partition@0 {
243 label = "kernel";
244 reg = <0x0 0x1e0000>;
245 read-only;
246 };
247 partition@1e0000 {
248 label = "dtb";
249 reg = <0x1e0000 0x20000>;
250 };
251 partition@200000 {
252 label = "root";
253 reg = <0x200000 0x200000>;
254 };
255 partition@400000 {
256 label = "user";
257 reg = <0x400000 0x3b80000>;
258 };
259 partition@3f80000 {
260 label = "env";
261 reg = <0x3f80000 0x40000>;
262 read-only;
263 };
264 partition@3fc0000 {
265 label = "u-boot";
266 reg = <0x3fc0000 0x40000>;
267 read-only;
268 };
269 };
270
271 display@2,0 {
272 compatible = "fujitsu,lime";
273 reg = <2 0x0 0x4000000>;
274 interrupt-parent = <&mpic>;
275 interrupts = <6 1>;
276 };
277
278 fpga_pic: fpga-pic@3,10 {
279 compatible = "abb,socrates-fpga-pic";
280 reg = <3 0x10 0x10>;
281 interrupt-controller;
282 /* IRQs 2, 10, 11, active low, level-sensitive */
283 interrupts = <2 1 10 1 11 1>;
284 interrupt-parent = <&mpic>;
285 #interrupt-cells = <3>;
286 };
287
288 spi@3,60 {
289 compatible = "abb,socrates-spi";
290 reg = <3 0x60 0x10>;
291 interrupts = <8 4 0>; // number, type, routing
292 interrupt-parent = <&fpga_pic>;
293 };
294
295 nand@3,70 {
296 compatible = "abb,socrates-nand";
297 reg = <3 0x70 0x04>;
298 bank-width = <1>;
299 #address-cells = <1>;
300 #size-cells = <1>;
301 data@0 {
302 label = "data";
303 reg = <0x0 0x40000000>;
304 };
305 };
306
307 can@3,100 {
308 compatible = "philips,sja1000";
309 reg = <3 0x100 0x80>;
310 interrupts = <2 8 1>; // number, type, routing
311 interrupt-parent = <&fpga_pic>;
312 };
313 };
314
315 pci0: pci@e0008000 {
316 cell-index = <0>;
317 #interrupt-cells = <1>;
318 #size-cells = <2>;
319 #address-cells = <3>;
320 compatible = "fsl,mpc8540-pci";
321 device_type = "pci";
322 reg = <0xe0008000 0x1000>;
323 clock-frequency = <66666666>;
324
325 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
326 interrupt-map = <
327 /* IDSEL 0x11 */
328 0x8800 0x0 0x0 1 &mpic 5 1
329 /* IDSEL 0x12 */
330 0x9000 0x0 0x0 1 &mpic 4 1>;
331 interrupt-parent = <&mpic>;
332 interrupts = <24 2>;
333 bus-range = <0x0 0x0>;
334 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
335 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
336 };
337
338};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 05:36:49 -0400