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-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts250
1 files changed, 179 insertions, 71 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 9d0b84b66cd..d215d21fff4 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8555 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 5 *
@@ -44,8 +44,14 @@
44 #size-cells = <1>; 44 #size-cells = <1>;
45 #interrupt-cells = <2>; 45 #interrupt-cells = <2>;
46 device_type = "soc"; 46 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 47 ranges = <00001000 e0001000 000ff000
48 reg = <e0000000 00100000>; // CCSRBAR 1M 48 80000000 80000000 10000000
49 e2000000 e2000000 00800000
50 90000000 90000000 10000000
51 e2800000 e2800000 00800000
52 a0000000 a0000000 20000000
53 e3000000 e3000000 01000000>;
54 reg = <e0000000 00001000>; // CCSRBAR
49 bus-frequency = <0>; 55 bus-frequency = <0>;
50 56
51 memory-controller@2000 { 57 memory-controller@2000 {
@@ -162,8 +168,8 @@
162 serial@4500 { 168 serial@4500 {
163 device_type = "serial"; 169 device_type = "serial";
164 compatible = "ns16550"; 170 compatible = "ns16550";
165 reg = <4500 100>; // reg base, size 171 reg = <4500 100>; // reg base, size
166 clock-frequency = <0>; // should we fill in in uboot? 172 clock-frequency = <0>; // should we fill in in uboot?
167 interrupts = <2a 2>; 173 interrupts = <2a 2>;
168 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>;
169 }; 175 };
@@ -172,7 +178,7 @@
172 device_type = "serial"; 178 device_type = "serial";
173 compatible = "ns16550"; 179 compatible = "ns16550";
174 reg = <4600 100>; // reg base, size 180 reg = <4600 100>; // reg base, size
175 clock-frequency = <0>; // should we fill in in uboot? 181 clock-frequency = <0>; // should we fill in in uboot?
176 interrupts = <2a 2>; 182 interrupts = <2a 2>;
177 interrupt-parent = <&mpic>; 183 interrupt-parent = <&mpic>;
178 }; 184 };
@@ -183,77 +189,154 @@
183 fsl,has-rstcr; 189 fsl,has-rstcr;
184 }; 190 };
185 191
186 pci1: pci@8000 { 192 pci@8000 {
187 interrupt-map-mask = <1f800 0 0 7>; 193 interrupt-map-mask = <f800 0 0 7>;
188 interrupt-map = < 194 interrupt-map = <
195 /* IDSEL 0x4 (PCIX Slot 2) */
196 02000 0 0 1 &mpic 0 1
197 02000 0 0 2 &mpic 1 1
198 02000 0 0 3 &mpic 2 1
199 02000 0 0 4 &mpic 3 1
200
201 /* IDSEL 0x5 (PCIX Slot 3) */
202 02800 0 0 1 &mpic 1 1
203 02800 0 0 2 &mpic 2 1
204 02800 0 0 3 &mpic 3 1
205 02800 0 0 4 &mpic 0 1
206
207 /* IDSEL 0x6 (PCIX Slot 4) */
208 03000 0 0 1 &mpic 2 1
209 03000 0 0 2 &mpic 3 1
210 03000 0 0 3 &mpic 0 1
211 03000 0 0 4 &mpic 1 1
212
213 /* IDSEL 0x8 (PCIX Slot 5) */
214 04000 0 0 1 &mpic 0 1
215 04000 0 0 2 &mpic 1 1
216 04000 0 0 3 &mpic 2 1
217 04000 0 0 4 &mpic 3 1
218
219 /* IDSEL 0xC (Tsi310 bridge) */
220 06000 0 0 1 &mpic 0 1
221 06000 0 0 2 &mpic 1 1
222 06000 0 0 3 &mpic 2 1
223 06000 0 0 4 &mpic 3 1
224
225 /* IDSEL 0x14 (Slot 2) */
226 0a000 0 0 1 &mpic 0 1
227 0a000 0 0 2 &mpic 1 1
228 0a000 0 0 3 &mpic 2 1
229 0a000 0 0 4 &mpic 3 1
230
231 /* IDSEL 0x15 (Slot 3) */
232 0a800 0 0 1 &mpic 1 1
233 0a800 0 0 2 &mpic 2 1
234 0a800 0 0 3 &mpic 3 1
235 0a800 0 0 4 &mpic 0 1
236
237 /* IDSEL 0x16 (Slot 4) */
238 0b000 0 0 1 &mpic 2 1
239 0b000 0 0 2 &mpic 3 1
240 0b000 0 0 3 &mpic 0 1
241 0b000 0 0 4 &mpic 1 1
242
243 /* IDSEL 0x18 (Slot 5) */
244 0c000 0 0 1 &mpic 0 1
245 0c000 0 0 2 &mpic 1 1
246 0c000 0 0 3 &mpic 2 1
247 0c000 0 0 4 &mpic 3 1
248
249 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
250 0E000 0 0 1 &mpic 0 1
251 0E000 0 0 2 &mpic 1 1
252 0E000 0 0 3 &mpic 2 1
253 0E000 0 0 4 &mpic 3 1>;
189 254
190 /* IDSEL 0x10 */
191 08000 0 0 1 &mpic 0 1
192 08000 0 0 2 &mpic 1 1
193 08000 0 0 3 &mpic 2 1
194 08000 0 0 4 &mpic 3 1
195
196 /* IDSEL 0x11 */
197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
207
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
213
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
219
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
225
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
233 interrupts = <18 2>; 256 interrupts = <18 2>;
234 bus-range = <0 0>; 257 bus-range = <0 0>;
235 ranges = <02000000 0 80000000 80000000 0 20000000 258 ranges = <02000000 0 80000000 80000000 0 10000000
236 01000000 0 00000000 e2000000 0 00100000>; 259 01000000 0 00000000 e2000000 0 00800000>;
237 clock-frequency = <3f940aa>; 260 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
239 #size-cells = <2>; 262 #size-cells = <2>;
240 #address-cells = <3>; 263 #address-cells = <3>;
241 reg = <8000 1000>; 264 reg = <8000 1000>;
242 compatible = "85xx"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
243 device_type = "pci"; 266 device_type = "pci";
244 267
245 i8259@19000 { 268 pci_bridge@1c {
246 clock-frequency = <0>; 269 interrupt-map-mask = <f800 0 0 7>;
247 interrupt-controller; 270 interrupt-map = <
248 device_type = "interrupt-controller"; 271
249 reg = <19000 0 0 0 1>; 272 /* IDSEL 0x00 (PrPMC Site) */
250 #address-cells = <0>; 273 0000 0 0 1 &mpic 0 1
251 #interrupt-cells = <2>; 274 0000 0 0 2 &mpic 1 1
252 built-in; 275 0000 0 0 3 &mpic 2 1
253 compatible = "chrp,iic"; 276 0000 0 0 4 &mpic 3 1
254 big-endian; 277
255 interrupts = <1>; 278 /* IDSEL 0x04 (VIA chip) */
256 interrupt-parent = <&pci1>; 279 2000 0 0 1 &mpic 0 1
280 2000 0 0 2 &mpic 1 1
281 2000 0 0 3 &mpic 2 1
282 2000 0 0 4 &mpic 3 1
283
284 /* IDSEL 0x05 (8139) */
285 2800 0 0 1 &mpic 1 1
286
287 /* IDSEL 0x06 (Slot 6) */
288 3000 0 0 1 &mpic 2 1
289 3000 0 0 2 &mpic 3 1
290 3000 0 0 3 &mpic 0 1
291 3000 0 0 4 &mpic 1 1
292
293 /* IDESL 0x07 (Slot 7) */
294 3800 0 0 1 &mpic 3 1
295 3800 0 0 2 &mpic 0 1
296 3800 0 0 3 &mpic 1 1
297 3800 0 0 4 &mpic 2 1>;
298
299 reg = <e000 0 0 0 0>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 ranges = <02000000 0 80000000
304 02000000 0 80000000
305 0 20000000
306 01000000 0 00000000
307 01000000 0 00000000
308 0 00080000>;
309 clock-frequency = <1fca055>;
310
311 isa@4 {
312 device_type = "isa";
313 #interrupt-cells = <2>;
314 #size-cells = <1>;
315 #address-cells = <2>;
316 reg = <2000 0 0 0 0>;
317 ranges = <1 0 01000000 0 0 00001000>;
318 interrupt-parent = <&i8259>;
319
320 i8259: interrupt-controller@20 {
321 clock-frequency = <0>;
322 interrupt-controller;
323 device_type = "interrupt-controller";
324 reg = <1 20 2
325 1 a0 2
326 1 4d0 2>;
327 #address-cells = <0>;
328 #interrupt-cells = <2>;
329 built-in;
330 compatible = "chrp,iic";
331 interrupts = <0 1>;
332 interrupt-parent = <&mpic>;
333 };
334
335 rtc@70 {
336 compatible = "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339 };
257 }; 340 };
258 }; 341 };
259 342
@@ -263,20 +346,45 @@
263 346
264 /* IDSEL 0x15 */ 347 /* IDSEL 0x15 */
265 a800 0 0 1 &mpic b 1 348 a800 0 0 1 &mpic b 1
266 a800 0 0 2 &mpic b 1 349 a800 0 0 2 &mpic 1 1
267 a800 0 0 3 &mpic b 1 350 a800 0 0 3 &mpic 2 1
268 a800 0 0 4 &mpic b 1>; 351 a800 0 0 4 &mpic 3 1>;
352
269 interrupt-parent = <&mpic>; 353 interrupt-parent = <&mpic>;
270 interrupts = <19 2>; 354 interrupts = <19 2>;
271 bus-range = <0 0>; 355 bus-range = <0 0>;
272 ranges = <02000000 0 a0000000 a0000000 0 20000000 356 ranges = <02000000 0 90000000 90000000 0 10000000
273 01000000 0 00000000 e3000000 0 00100000>; 357 01000000 0 00000000 e2800000 0 00800000>;
274 clock-frequency = <3f940aa>; 358 clock-frequency = <3f940aa>;
275 #interrupt-cells = <1>; 359 #interrupt-cells = <1>;
276 #size-cells = <2>; 360 #size-cells = <2>;
277 #address-cells = <3>; 361 #address-cells = <3>;
278 reg = <9000 1000>; 362 reg = <9000 1000>;
279 compatible = "85xx"; 363 compatible = "fsl,mpc8540-pci";
364 device_type = "pci";
365 };
366 /* PCI Express */
367 pcie@a000 {
368 interrupt-map-mask = <f800 0 0 7>;
369 interrupt-map = <
370
371 /* IDSEL 0x0 (PEX) */
372 00000 0 0 1 &mpic 0 1
373 00000 0 0 2 &mpic 1 1
374 00000 0 0 3 &mpic 2 1
375 00000 0 0 4 &mpic 3 1>;
376
377 interrupt-parent = <&mpic>;
378 interrupts = <1a 2>;
379 bus-range = <0 ff>;
380 ranges = <02000000 0 a0000000 a0000000 0 20000000
381 01000000 0 00000000 e3000000 0 08000000>;
382 clock-frequency = <1fca055>;
383 #interrupt-cells = <1>;
384 #size-cells = <2>;
385 #address-cells = <3>;
386 reg = <a000 1000>;
387 compatible = "fsl,mpc8548-pcie";
280 device_type = "pci"; 388 device_type = "pci";
281 }; 389 };
282 390
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 21:43:55 -0400