2 files changed, 27 insertions, 16 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6e99665ae86..c43f4b26a69 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -618,15 +618,35 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
         if (cpu_has_inclusive_pcaches) {
                 if (size >= scache_size)
                         r4k_blast_scache();
-                else
+                else {
+                        unsigned long lsize = cpu_scache_line_size();
+                        unsigned long almask = ~(lsize - 1);
+
+                        /*
+                         * There is no clearly documented alignment requirement
+                         * for the cache instruction on MIPS processors and
+                         * some processors, among them the RM5200 and RM7000
+                         * QED processors will throw an address error for cache
+                         * hit ops with insufficient alignment.  Solved by
+                         * aligning the address to cache line size.
+                         */
+                        cache_op(Hit_Writeback_Inv_SD, addr & almask);
+                        cache_op(Hit_Writeback_Inv_SD,
+                                 (addr + size - 1) & almask);
                         blast_inv_scache_range(addr, addr + size);
+                }
                 return;
         }
 
         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
                 r4k_blast_dcache();
         } else {
+                unsigned long lsize = cpu_dcache_line_size();
+                unsigned long almask = ~(lsize - 1);
+
                 R4600_HIT_CACHEOP_WAR_IMPL;
+                cache_op(Hit_Writeback_Inv_D, addr & almask);
+                cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
                 blast_inv_dcache_range(addr, addr + size);
         }
 
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index fa636fc6b7b..55767ad9f00 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -97,7 +97,6 @@ good_area:
                         goto bad_area;
         }
 
-survive:
         /*
          * If for any reason at all we couldn't handle the fault,
          * make sure we exit gracefully rather than endlessly redo
@@ -167,21 +166,13 @@ no_context:
                field,  regs->regs[31]);
         die("Oops", regs);
 
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
 out_of_memory:
-        up_read(&mm->mmap_sem);
-        if (is_global_init(tsk)) {
-                yield();
-                down_read(&mm->mmap_sem);
-                goto survive;
-        }
-        printk("VM: killing process %s\n", tsk->comm);
-        if (user_mode(regs))
-                do_group_exit(SIGKILL);
-        goto no_context;
+        /*
+         * We ran out of memory, call the OOM killer, and return the userspace
+         * (which will retry the fault, or kill us if we got oom-killed).
+         */
+        pagefault_out_of_memory();
+        return;
 
 do_sigbus:
         up_read(&mm->mmap_sem);