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-rw-r--r--arch/mips/mm/page.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 1417c649485..48060c635ac 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
172 */ 172 */
173 cache_line_size = cpu_dcache_line_size(); 173 cache_line_size = cpu_dcache_line_size();
174 switch (current_cpu_type()) { 174 switch (current_cpu_type()) {
175 case CPU_R5500:
175 case CPU_TX49XX: 176 case CPU_TX49XX:
176 /* TX49 supports only Pref_Load */ 177 /* These processors only support the Pref_Load. */
177 pref_bias_copy_load = 256; 178 pref_bias_copy_load = 256;
178 break; 179 break;
179 180