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Diffstat (limited to 'arch/mips/lantiq/xway/dma.c')
-rw-r--r--arch/mips/lantiq/xway/dma.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 55d2c4fa471..6453962ac89 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -25,6 +25,7 @@
25#include <lantiq_soc.h> 25#include <lantiq_soc.h>
26#include <xway_dma.h> 26#include <xway_dma.h>
27 27
28#define LTQ_DMA_ID 0x08
28#define LTQ_DMA_CTRL 0x10 29#define LTQ_DMA_CTRL 0x10
29#define LTQ_DMA_CPOLL 0x14 30#define LTQ_DMA_CPOLL 0x14
30#define LTQ_DMA_CS 0x18 31#define LTQ_DMA_CS 0x18
@@ -48,7 +49,7 @@
48#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ 49#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
49#define DMA_2W_BURST BIT(1) /* 2 word burst length */ 50#define DMA_2W_BURST BIT(1) /* 2 word burst length */
50#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ 51#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
51#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */ 52#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
52#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ 53#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
53 54
54#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) 55#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
@@ -191,10 +192,10 @@ ltq_dma_init_port(int p)
191 switch (p) { 192 switch (p) {
192 case DMA_PORT_ETOP: 193 case DMA_PORT_ETOP:
193 /* 194 /*
194 * Tell the DMA engine to swap the endianess of data frames and 195 * Tell the DMA engine to swap the endianness of data frames and
195 * drop packets if the channel arbitration fails. 196 * drop packets if the channel arbitration fails.
196 */ 197 */
197 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN, 198 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
198 LTQ_DMA_PCTRL); 199 LTQ_DMA_PCTRL);
199 break; 200 break;
200 201
@@ -214,6 +215,7 @@ ltq_dma_init(struct platform_device *pdev)
214{ 215{
215 struct clk *clk; 216 struct clk *clk;
216 struct resource *res; 217 struct resource *res;
218 unsigned id;
217 int i; 219 int i;
218 220
219 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -243,7 +245,12 @@ ltq_dma_init(struct platform_device *pdev)
243 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); 245 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
244 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 246 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
245 } 247 }
246 dev_info(&pdev->dev, "init done\n"); 248
249 id = ltq_dma_r32(LTQ_DMA_ID);
250 dev_info(&pdev->dev,
251 "Init done - hw rev: %X, ports: %d, channels: %d\n",
252 id & 0x1f, (id >> 16) & 0xf, id >> 20);
253
247 return 0; 254 return 0;
248} 255}
249 256