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-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 3ccae12cc7b..a5e0f17ea77 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -65,6 +65,8 @@
65#define AR934X_WMAC_SIZE 0x20000 65#define AR934X_WMAC_SIZE 0x20000
66#define AR934X_EHCI_BASE 0x1b000000 66#define AR934X_EHCI_BASE 0x1b000000
67#define AR934X_EHCI_SIZE 0x200 67#define AR934X_EHCI_SIZE 0x200
68#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
69#define AR934X_SRIF_SIZE 0x1000
68 70
69/* 71/*
70 * DDR_CTRL block 72 * DDR_CTRL block
@@ -406,4 +408,25 @@
406#define AR933X_GPIO_COUNT 30 408#define AR933X_GPIO_COUNT 30
407#define AR934X_GPIO_COUNT 23 409#define AR934X_GPIO_COUNT 23
408 410
411/*
412 * SRIF block
413 */
414#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
415#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
416#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
417
418#define AR934X_SRIF_DDR_DPLL1_REG 0x240
419#define AR934X_SRIF_DDR_DPLL2_REG 0x244
420#define AR934X_SRIF_DDR_DPLL3_REG 0x248
421
422#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
423#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
424#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
425#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
426#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
427
428#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
429#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
430#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
431
409#endif /* __ASM_MACH_AR71XX_REGS_H */ 432#endif /* __ASM_MACH_AR71XX_REGS_H */