diff options
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h')
-rw-r--r-- | arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h | 574 |
1 files changed, 533 insertions, 41 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h index 55d120fe8ae..b5b45d26f1c 100644 --- a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h | |||
@@ -4,7 +4,7 @@ | |||
4 | * Contact: support@caviumnetworks.com | 4 | * Contact: support@caviumnetworks.com |
5 | * This file is part of the OCTEON SDK | 5 | * This file is part of the OCTEON SDK |
6 | * | 6 | * |
7 | * Copyright (c) 2003-2008 Cavium Networks | 7 | * Copyright (c) 2003-2012 Cavium Networks |
8 | * | 8 | * |
9 | * This file is free software; you can redistribute it and/or modify | 9 | * This file is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License, Version 2, as | 10 | * it under the terms of the GNU General Public License, Version 2, as |
@@ -28,40 +28,250 @@ | |||
28 | #ifndef __CVMX_PCSXX_DEFS_H__ | 28 | #ifndef __CVMX_PCSXX_DEFS_H__ |
29 | #define __CVMX_PCSXX_DEFS_H__ | 29 | #define __CVMX_PCSXX_DEFS_H__ |
30 | 30 | ||
31 | #define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ | 31 | static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) |
32 | CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) | 32 | { |
33 | #define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ | 33 | switch (cvmx_get_octeon_family()) { |
34 | CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) | 34 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: |
35 | #define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ | 35 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: |
36 | CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) | 36 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: |
37 | #define CVMX_PCSXX_CONTROL1_REG(block_id) \ | 37 | return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; |
38 | CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) | 38 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: |
39 | #define CVMX_PCSXX_CONTROL2_REG(block_id) \ | 39 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: |
40 | CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) | 40 | return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull; |
41 | #define CVMX_PCSXX_INT_EN_REG(block_id) \ | 41 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: |
42 | CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) | 42 | return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; |
43 | #define CVMX_PCSXX_INT_REG(block_id) \ | 43 | } |
44 | CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) | 44 | return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull; |
45 | #define CVMX_PCSXX_LOG_ANL_REG(block_id) \ | 45 | } |
46 | CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) | 46 | |
47 | #define CVMX_PCSXX_MISC_CTL_REG(block_id) \ | 47 | static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) |
48 | CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) | 48 | { |
49 | #define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ | 49 | switch (cvmx_get_octeon_family()) { |
50 | CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) | 50 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: |
51 | #define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ | 51 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: |
52 | CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) | 52 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: |
53 | #define CVMX_PCSXX_STATUS1_REG(block_id) \ | 53 | return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; |
54 | CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) | 54 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: |
55 | #define CVMX_PCSXX_STATUS2_REG(block_id) \ | 55 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: |
56 | CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) | 56 | return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull; |
57 | #define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ | 57 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: |
58 | CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) | 58 | return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; |
59 | #define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ | 59 | } |
60 | CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) | 60 | return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull; |
61 | } | ||
62 | |||
63 | static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) | ||
64 | { | ||
65 | switch (cvmx_get_octeon_family()) { | ||
66 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
67 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
68 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
69 | return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; | ||
70 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
71 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
72 | return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull; | ||
73 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
74 | return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; | ||
75 | } | ||
76 | return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull; | ||
77 | } | ||
78 | |||
79 | static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) | ||
80 | { | ||
81 | switch (cvmx_get_octeon_family()) { | ||
82 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
83 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
84 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
85 | return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; | ||
86 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
87 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
88 | return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull; | ||
89 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
90 | return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; | ||
91 | } | ||
92 | return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull; | ||
93 | } | ||
94 | |||
95 | static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) | ||
96 | { | ||
97 | switch (cvmx_get_octeon_family()) { | ||
98 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
99 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
100 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
101 | return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; | ||
102 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
103 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
104 | return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull; | ||
105 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
106 | return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; | ||
107 | } | ||
108 | return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull; | ||
109 | } | ||
110 | |||
111 | static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) | ||
112 | { | ||
113 | switch (cvmx_get_octeon_family()) { | ||
114 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
115 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
116 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
117 | return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; | ||
118 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
119 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
120 | return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull; | ||
121 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
122 | return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; | ||
123 | } | ||
124 | return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull; | ||
125 | } | ||
126 | |||
127 | static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) | ||
128 | { | ||
129 | switch (cvmx_get_octeon_family()) { | ||
130 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
131 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
132 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
133 | return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; | ||
134 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
135 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
136 | return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull; | ||
137 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
138 | return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; | ||
139 | } | ||
140 | return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull; | ||
141 | } | ||
142 | |||
143 | static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) | ||
144 | { | ||
145 | switch (cvmx_get_octeon_family()) { | ||
146 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
147 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
148 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
149 | return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; | ||
150 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
151 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
152 | return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull; | ||
153 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
154 | return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; | ||
155 | } | ||
156 | return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull; | ||
157 | } | ||
158 | |||
159 | static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) | ||
160 | { | ||
161 | switch (cvmx_get_octeon_family()) { | ||
162 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
163 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
164 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
165 | return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; | ||
166 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
167 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
168 | return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull; | ||
169 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
170 | return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; | ||
171 | } | ||
172 | return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull; | ||
173 | } | ||
174 | |||
175 | static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) | ||
176 | { | ||
177 | switch (cvmx_get_octeon_family()) { | ||
178 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
179 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
180 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
181 | return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; | ||
182 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
183 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
184 | return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull; | ||
185 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
186 | return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; | ||
187 | } | ||
188 | return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull; | ||
189 | } | ||
190 | |||
191 | static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) | ||
192 | { | ||
193 | switch (cvmx_get_octeon_family()) { | ||
194 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
195 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
196 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
197 | return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; | ||
198 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
199 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
200 | return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull; | ||
201 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
202 | return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; | ||
203 | } | ||
204 | return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull; | ||
205 | } | ||
206 | |||
207 | static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) | ||
208 | { | ||
209 | switch (cvmx_get_octeon_family()) { | ||
210 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
211 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
212 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
213 | return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; | ||
214 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
215 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
216 | return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull; | ||
217 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
218 | return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; | ||
219 | } | ||
220 | return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull; | ||
221 | } | ||
222 | |||
223 | static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) | ||
224 | { | ||
225 | switch (cvmx_get_octeon_family()) { | ||
226 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
227 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
228 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
229 | return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; | ||
230 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
231 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
232 | return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull; | ||
233 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
234 | return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; | ||
235 | } | ||
236 | return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull; | ||
237 | } | ||
238 | |||
239 | static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) | ||
240 | { | ||
241 | switch (cvmx_get_octeon_family()) { | ||
242 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
243 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
244 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
245 | return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; | ||
246 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
247 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
248 | return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull; | ||
249 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
250 | return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; | ||
251 | } | ||
252 | return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull; | ||
253 | } | ||
254 | |||
255 | static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) | ||
256 | { | ||
257 | switch (cvmx_get_octeon_family()) { | ||
258 | case OCTEON_CN56XX & OCTEON_FAMILY_MASK: | ||
259 | case OCTEON_CN66XX & OCTEON_FAMILY_MASK: | ||
260 | case OCTEON_CN61XX & OCTEON_FAMILY_MASK: | ||
261 | return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; | ||
262 | case OCTEON_CN52XX & OCTEON_FAMILY_MASK: | ||
263 | case OCTEON_CN63XX & OCTEON_FAMILY_MASK: | ||
264 | return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull; | ||
265 | case OCTEON_CN68XX & OCTEON_FAMILY_MASK: | ||
266 | return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; | ||
267 | } | ||
268 | return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull; | ||
269 | } | ||
61 | 270 | ||
62 | union cvmx_pcsxx_10gbx_status_reg { | 271 | union cvmx_pcsxx_10gbx_status_reg { |
63 | uint64_t u64; | 272 | uint64_t u64; |
64 | struct cvmx_pcsxx_10gbx_status_reg_s { | 273 | struct cvmx_pcsxx_10gbx_status_reg_s { |
274 | #ifdef __BIG_ENDIAN_BITFIELD | ||
65 | uint64_t reserved_13_63:51; | 275 | uint64_t reserved_13_63:51; |
66 | uint64_t alignd:1; | 276 | uint64_t alignd:1; |
67 | uint64_t pattst:1; | 277 | uint64_t pattst:1; |
@@ -70,43 +280,85 @@ union cvmx_pcsxx_10gbx_status_reg { | |||
70 | uint64_t l2sync:1; | 280 | uint64_t l2sync:1; |
71 | uint64_t l1sync:1; | 281 | uint64_t l1sync:1; |
72 | uint64_t l0sync:1; | 282 | uint64_t l0sync:1; |
283 | #else | ||
284 | uint64_t l0sync:1; | ||
285 | uint64_t l1sync:1; | ||
286 | uint64_t l2sync:1; | ||
287 | uint64_t l3sync:1; | ||
288 | uint64_t reserved_4_10:7; | ||
289 | uint64_t pattst:1; | ||
290 | uint64_t alignd:1; | ||
291 | uint64_t reserved_13_63:51; | ||
292 | #endif | ||
73 | } s; | 293 | } s; |
74 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; | 294 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; |
75 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; | 295 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; |
76 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; | 296 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; |
77 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; | 297 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; |
298 | struct cvmx_pcsxx_10gbx_status_reg_s cn61xx; | ||
299 | struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; | ||
300 | struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; | ||
301 | struct cvmx_pcsxx_10gbx_status_reg_s cn66xx; | ||
302 | struct cvmx_pcsxx_10gbx_status_reg_s cn68xx; | ||
303 | struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1; | ||
78 | }; | 304 | }; |
79 | 305 | ||
80 | union cvmx_pcsxx_bist_status_reg { | 306 | union cvmx_pcsxx_bist_status_reg { |
81 | uint64_t u64; | 307 | uint64_t u64; |
82 | struct cvmx_pcsxx_bist_status_reg_s { | 308 | struct cvmx_pcsxx_bist_status_reg_s { |
309 | #ifdef __BIG_ENDIAN_BITFIELD | ||
83 | uint64_t reserved_1_63:63; | 310 | uint64_t reserved_1_63:63; |
84 | uint64_t bist_status:1; | 311 | uint64_t bist_status:1; |
312 | #else | ||
313 | uint64_t bist_status:1; | ||
314 | uint64_t reserved_1_63:63; | ||
315 | #endif | ||
85 | } s; | 316 | } s; |
86 | struct cvmx_pcsxx_bist_status_reg_s cn52xx; | 317 | struct cvmx_pcsxx_bist_status_reg_s cn52xx; |
87 | struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; | 318 | struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; |
88 | struct cvmx_pcsxx_bist_status_reg_s cn56xx; | 319 | struct cvmx_pcsxx_bist_status_reg_s cn56xx; |
89 | struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; | 320 | struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; |
321 | struct cvmx_pcsxx_bist_status_reg_s cn61xx; | ||
322 | struct cvmx_pcsxx_bist_status_reg_s cn63xx; | ||
323 | struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; | ||
324 | struct cvmx_pcsxx_bist_status_reg_s cn66xx; | ||
325 | struct cvmx_pcsxx_bist_status_reg_s cn68xx; | ||
326 | struct cvmx_pcsxx_bist_status_reg_s cn68xxp1; | ||
90 | }; | 327 | }; |
91 | 328 | ||
92 | union cvmx_pcsxx_bit_lock_status_reg { | 329 | union cvmx_pcsxx_bit_lock_status_reg { |
93 | uint64_t u64; | 330 | uint64_t u64; |
94 | struct cvmx_pcsxx_bit_lock_status_reg_s { | 331 | struct cvmx_pcsxx_bit_lock_status_reg_s { |
332 | #ifdef __BIG_ENDIAN_BITFIELD | ||
95 | uint64_t reserved_4_63:60; | 333 | uint64_t reserved_4_63:60; |
96 | uint64_t bitlck3:1; | 334 | uint64_t bitlck3:1; |
97 | uint64_t bitlck2:1; | 335 | uint64_t bitlck2:1; |
98 | uint64_t bitlck1:1; | 336 | uint64_t bitlck1:1; |
99 | uint64_t bitlck0:1; | 337 | uint64_t bitlck0:1; |
338 | #else | ||
339 | uint64_t bitlck0:1; | ||
340 | uint64_t bitlck1:1; | ||
341 | uint64_t bitlck2:1; | ||
342 | uint64_t bitlck3:1; | ||
343 | uint64_t reserved_4_63:60; | ||
344 | #endif | ||
100 | } s; | 345 | } s; |
101 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; | 346 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; |
102 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; | 347 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; |
103 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; | 348 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; |
104 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; | 349 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; |
350 | struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx; | ||
351 | struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; | ||
352 | struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; | ||
353 | struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx; | ||
354 | struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx; | ||
355 | struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1; | ||
105 | }; | 356 | }; |
106 | 357 | ||
107 | union cvmx_pcsxx_control1_reg { | 358 | union cvmx_pcsxx_control1_reg { |
108 | uint64_t u64; | 359 | uint64_t u64; |
109 | struct cvmx_pcsxx_control1_reg_s { | 360 | struct cvmx_pcsxx_control1_reg_s { |
361 | #ifdef __BIG_ENDIAN_BITFIELD | ||
110 | uint64_t reserved_16_63:48; | 362 | uint64_t reserved_16_63:48; |
111 | uint64_t reset:1; | 363 | uint64_t reset:1; |
112 | uint64_t loopbck1:1; | 364 | uint64_t loopbck1:1; |
@@ -117,137 +369,309 @@ union cvmx_pcsxx_control1_reg { | |||
117 | uint64_t spdsel0:1; | 369 | uint64_t spdsel0:1; |
118 | uint64_t spd:4; | 370 | uint64_t spd:4; |
119 | uint64_t reserved_0_1:2; | 371 | uint64_t reserved_0_1:2; |
372 | #else | ||
373 | uint64_t reserved_0_1:2; | ||
374 | uint64_t spd:4; | ||
375 | uint64_t spdsel0:1; | ||
376 | uint64_t reserved_7_10:4; | ||
377 | uint64_t lo_pwr:1; | ||
378 | uint64_t reserved_12_12:1; | ||
379 | uint64_t spdsel1:1; | ||
380 | uint64_t loopbck1:1; | ||
381 | uint64_t reset:1; | ||
382 | uint64_t reserved_16_63:48; | ||
383 | #endif | ||
120 | } s; | 384 | } s; |
121 | struct cvmx_pcsxx_control1_reg_s cn52xx; | 385 | struct cvmx_pcsxx_control1_reg_s cn52xx; |
122 | struct cvmx_pcsxx_control1_reg_s cn52xxp1; | 386 | struct cvmx_pcsxx_control1_reg_s cn52xxp1; |
123 | struct cvmx_pcsxx_control1_reg_s cn56xx; | 387 | struct cvmx_pcsxx_control1_reg_s cn56xx; |
124 | struct cvmx_pcsxx_control1_reg_s cn56xxp1; | 388 | struct cvmx_pcsxx_control1_reg_s cn56xxp1; |
389 | struct cvmx_pcsxx_control1_reg_s cn61xx; | ||
390 | struct cvmx_pcsxx_control1_reg_s cn63xx; | ||
391 | struct cvmx_pcsxx_control1_reg_s cn63xxp1; | ||
392 | struct cvmx_pcsxx_control1_reg_s cn66xx; | ||
393 | struct cvmx_pcsxx_control1_reg_s cn68xx; | ||
394 | struct cvmx_pcsxx_control1_reg_s cn68xxp1; | ||
125 | }; | 395 | }; |
126 | 396 | ||
127 | union cvmx_pcsxx_control2_reg { | 397 | union cvmx_pcsxx_control2_reg { |
128 | uint64_t u64; | 398 | uint64_t u64; |
129 | struct cvmx_pcsxx_control2_reg_s { | 399 | struct cvmx_pcsxx_control2_reg_s { |
400 | #ifdef __BIG_ENDIAN_BITFIELD | ||
130 | uint64_t reserved_2_63:62; | 401 | uint64_t reserved_2_63:62; |
131 | uint64_t type:2; | 402 | uint64_t type:2; |
403 | #else | ||
404 | uint64_t type:2; | ||
405 | uint64_t reserved_2_63:62; | ||
406 | #endif | ||
132 | } s; | 407 | } s; |
133 | struct cvmx_pcsxx_control2_reg_s cn52xx; | 408 | struct cvmx_pcsxx_control2_reg_s cn52xx; |
134 | struct cvmx_pcsxx_control2_reg_s cn52xxp1; | 409 | struct cvmx_pcsxx_control2_reg_s cn52xxp1; |
135 | struct cvmx_pcsxx_control2_reg_s cn56xx; | 410 | struct cvmx_pcsxx_control2_reg_s cn56xx; |
136 | struct cvmx_pcsxx_control2_reg_s cn56xxp1; | 411 | struct cvmx_pcsxx_control2_reg_s cn56xxp1; |
412 | struct cvmx_pcsxx_control2_reg_s cn61xx; | ||
413 | struct cvmx_pcsxx_control2_reg_s cn63xx; | ||
414 | struct cvmx_pcsxx_control2_reg_s cn63xxp1; | ||
415 | struct cvmx_pcsxx_control2_reg_s cn66xx; | ||
416 | struct cvmx_pcsxx_control2_reg_s cn68xx; | ||
417 | struct cvmx_pcsxx_control2_reg_s cn68xxp1; | ||
137 | }; | 418 | }; |
138 | 419 | ||
139 | union cvmx_pcsxx_int_en_reg { | 420 | union cvmx_pcsxx_int_en_reg { |
140 | uint64_t u64; | 421 | uint64_t u64; |
141 | struct cvmx_pcsxx_int_en_reg_s { | 422 | struct cvmx_pcsxx_int_en_reg_s { |
142 | uint64_t reserved_6_63:58; | 423 | #ifdef __BIG_ENDIAN_BITFIELD |
424 | uint64_t reserved_7_63:57; | ||
425 | uint64_t dbg_sync_en:1; | ||
143 | uint64_t algnlos_en:1; | 426 | uint64_t algnlos_en:1; |
144 | uint64_t synlos_en:1; | 427 | uint64_t synlos_en:1; |
145 | uint64_t bitlckls_en:1; | 428 | uint64_t bitlckls_en:1; |
146 | uint64_t rxsynbad_en:1; | 429 | uint64_t rxsynbad_en:1; |
147 | uint64_t rxbad_en:1; | 430 | uint64_t rxbad_en:1; |
148 | uint64_t txflt_en:1; | 431 | uint64_t txflt_en:1; |
432 | #else | ||
433 | uint64_t txflt_en:1; | ||
434 | uint64_t rxbad_en:1; | ||
435 | uint64_t rxsynbad_en:1; | ||
436 | uint64_t bitlckls_en:1; | ||
437 | uint64_t synlos_en:1; | ||
438 | uint64_t algnlos_en:1; | ||
439 | uint64_t dbg_sync_en:1; | ||
440 | uint64_t reserved_7_63:57; | ||
441 | #endif | ||
149 | } s; | 442 | } s; |
150 | struct cvmx_pcsxx_int_en_reg_s cn52xx; | 443 | struct cvmx_pcsxx_int_en_reg_cn52xx { |
151 | struct cvmx_pcsxx_int_en_reg_s cn52xxp1; | 444 | #ifdef __BIG_ENDIAN_BITFIELD |
152 | struct cvmx_pcsxx_int_en_reg_s cn56xx; | 445 | uint64_t reserved_6_63:58; |
153 | struct cvmx_pcsxx_int_en_reg_s cn56xxp1; | 446 | uint64_t algnlos_en:1; |
447 | uint64_t synlos_en:1; | ||
448 | uint64_t bitlckls_en:1; | ||
449 | uint64_t rxsynbad_en:1; | ||
450 | uint64_t rxbad_en:1; | ||
451 | uint64_t txflt_en:1; | ||
452 | #else | ||
453 | uint64_t txflt_en:1; | ||
454 | uint64_t rxbad_en:1; | ||
455 | uint64_t rxsynbad_en:1; | ||
456 | uint64_t bitlckls_en:1; | ||
457 | uint64_t synlos_en:1; | ||
458 | uint64_t algnlos_en:1; | ||
459 | uint64_t reserved_6_63:58; | ||
460 | #endif | ||
461 | } cn52xx; | ||
462 | struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; | ||
463 | struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; | ||
464 | struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; | ||
465 | struct cvmx_pcsxx_int_en_reg_s cn61xx; | ||
466 | struct cvmx_pcsxx_int_en_reg_s cn63xx; | ||
467 | struct cvmx_pcsxx_int_en_reg_s cn63xxp1; | ||
468 | struct cvmx_pcsxx_int_en_reg_s cn66xx; | ||
469 | struct cvmx_pcsxx_int_en_reg_s cn68xx; | ||
470 | struct cvmx_pcsxx_int_en_reg_s cn68xxp1; | ||
154 | }; | 471 | }; |
155 | 472 | ||
156 | union cvmx_pcsxx_int_reg { | 473 | union cvmx_pcsxx_int_reg { |
157 | uint64_t u64; | 474 | uint64_t u64; |
158 | struct cvmx_pcsxx_int_reg_s { | 475 | struct cvmx_pcsxx_int_reg_s { |
159 | uint64_t reserved_6_63:58; | 476 | #ifdef __BIG_ENDIAN_BITFIELD |
477 | uint64_t reserved_7_63:57; | ||
478 | uint64_t dbg_sync:1; | ||
160 | uint64_t algnlos:1; | 479 | uint64_t algnlos:1; |
161 | uint64_t synlos:1; | 480 | uint64_t synlos:1; |
162 | uint64_t bitlckls:1; | 481 | uint64_t bitlckls:1; |
163 | uint64_t rxsynbad:1; | 482 | uint64_t rxsynbad:1; |
164 | uint64_t rxbad:1; | 483 | uint64_t rxbad:1; |
165 | uint64_t txflt:1; | 484 | uint64_t txflt:1; |
485 | #else | ||
486 | uint64_t txflt:1; | ||
487 | uint64_t rxbad:1; | ||
488 | uint64_t rxsynbad:1; | ||
489 | uint64_t bitlckls:1; | ||
490 | uint64_t synlos:1; | ||
491 | uint64_t algnlos:1; | ||
492 | uint64_t dbg_sync:1; | ||
493 | uint64_t reserved_7_63:57; | ||
494 | #endif | ||
166 | } s; | 495 | } s; |
167 | struct cvmx_pcsxx_int_reg_s cn52xx; | 496 | struct cvmx_pcsxx_int_reg_cn52xx { |
168 | struct cvmx_pcsxx_int_reg_s cn52xxp1; | 497 | #ifdef __BIG_ENDIAN_BITFIELD |
169 | struct cvmx_pcsxx_int_reg_s cn56xx; | 498 | uint64_t reserved_6_63:58; |
170 | struct cvmx_pcsxx_int_reg_s cn56xxp1; | 499 | uint64_t algnlos:1; |
500 | uint64_t synlos:1; | ||
501 | uint64_t bitlckls:1; | ||
502 | uint64_t rxsynbad:1; | ||
503 | uint64_t rxbad:1; | ||
504 | uint64_t txflt:1; | ||
505 | #else | ||
506 | uint64_t txflt:1; | ||
507 | uint64_t rxbad:1; | ||
508 | uint64_t rxsynbad:1; | ||
509 | uint64_t bitlckls:1; | ||
510 | uint64_t synlos:1; | ||
511 | uint64_t algnlos:1; | ||
512 | uint64_t reserved_6_63:58; | ||
513 | #endif | ||
514 | } cn52xx; | ||
515 | struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; | ||
516 | struct cvmx_pcsxx_int_reg_cn52xx cn56xx; | ||
517 | struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; | ||
518 | struct cvmx_pcsxx_int_reg_s cn61xx; | ||
519 | struct cvmx_pcsxx_int_reg_s cn63xx; | ||
520 | struct cvmx_pcsxx_int_reg_s cn63xxp1; | ||
521 | struct cvmx_pcsxx_int_reg_s cn66xx; | ||
522 | struct cvmx_pcsxx_int_reg_s cn68xx; | ||
523 | struct cvmx_pcsxx_int_reg_s cn68xxp1; | ||
171 | }; | 524 | }; |
172 | 525 | ||
173 | union cvmx_pcsxx_log_anl_reg { | 526 | union cvmx_pcsxx_log_anl_reg { |
174 | uint64_t u64; | 527 | uint64_t u64; |
175 | struct cvmx_pcsxx_log_anl_reg_s { | 528 | struct cvmx_pcsxx_log_anl_reg_s { |
529 | #ifdef __BIG_ENDIAN_BITFIELD | ||
176 | uint64_t reserved_7_63:57; | 530 | uint64_t reserved_7_63:57; |
177 | uint64_t enc_mode:1; | 531 | uint64_t enc_mode:1; |
178 | uint64_t drop_ln:2; | 532 | uint64_t drop_ln:2; |
179 | uint64_t lafifovfl:1; | 533 | uint64_t lafifovfl:1; |
180 | uint64_t la_en:1; | 534 | uint64_t la_en:1; |
181 | uint64_t pkt_sz:2; | 535 | uint64_t pkt_sz:2; |
536 | #else | ||
537 | uint64_t pkt_sz:2; | ||
538 | uint64_t la_en:1; | ||
539 | uint64_t lafifovfl:1; | ||
540 | uint64_t drop_ln:2; | ||
541 | uint64_t enc_mode:1; | ||
542 | uint64_t reserved_7_63:57; | ||
543 | #endif | ||
182 | } s; | 544 | } s; |
183 | struct cvmx_pcsxx_log_anl_reg_s cn52xx; | 545 | struct cvmx_pcsxx_log_anl_reg_s cn52xx; |
184 | struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; | 546 | struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; |
185 | struct cvmx_pcsxx_log_anl_reg_s cn56xx; | 547 | struct cvmx_pcsxx_log_anl_reg_s cn56xx; |
186 | struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; | 548 | struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; |
549 | struct cvmx_pcsxx_log_anl_reg_s cn61xx; | ||
550 | struct cvmx_pcsxx_log_anl_reg_s cn63xx; | ||
551 | struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; | ||
552 | struct cvmx_pcsxx_log_anl_reg_s cn66xx; | ||
553 | struct cvmx_pcsxx_log_anl_reg_s cn68xx; | ||
554 | struct cvmx_pcsxx_log_anl_reg_s cn68xxp1; | ||
187 | }; | 555 | }; |
188 | 556 | ||
189 | union cvmx_pcsxx_misc_ctl_reg { | 557 | union cvmx_pcsxx_misc_ctl_reg { |
190 | uint64_t u64; | 558 | uint64_t u64; |
191 | struct cvmx_pcsxx_misc_ctl_reg_s { | 559 | struct cvmx_pcsxx_misc_ctl_reg_s { |
560 | #ifdef __BIG_ENDIAN_BITFIELD | ||
192 | uint64_t reserved_4_63:60; | 561 | uint64_t reserved_4_63:60; |
193 | uint64_t tx_swap:1; | 562 | uint64_t tx_swap:1; |
194 | uint64_t rx_swap:1; | 563 | uint64_t rx_swap:1; |
195 | uint64_t xaui:1; | 564 | uint64_t xaui:1; |
196 | uint64_t gmxeno:1; | 565 | uint64_t gmxeno:1; |
566 | #else | ||
567 | uint64_t gmxeno:1; | ||
568 | uint64_t xaui:1; | ||
569 | uint64_t rx_swap:1; | ||
570 | uint64_t tx_swap:1; | ||
571 | uint64_t reserved_4_63:60; | ||
572 | #endif | ||
197 | } s; | 573 | } s; |
198 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; | 574 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; |
199 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; | 575 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; |
200 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; | 576 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; |
201 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; | 577 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; |
578 | struct cvmx_pcsxx_misc_ctl_reg_s cn61xx; | ||
579 | struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; | ||
580 | struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; | ||
581 | struct cvmx_pcsxx_misc_ctl_reg_s cn66xx; | ||
582 | struct cvmx_pcsxx_misc_ctl_reg_s cn68xx; | ||
583 | struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1; | ||
202 | }; | 584 | }; |
203 | 585 | ||
204 | union cvmx_pcsxx_rx_sync_states_reg { | 586 | union cvmx_pcsxx_rx_sync_states_reg { |
205 | uint64_t u64; | 587 | uint64_t u64; |
206 | struct cvmx_pcsxx_rx_sync_states_reg_s { | 588 | struct cvmx_pcsxx_rx_sync_states_reg_s { |
589 | #ifdef __BIG_ENDIAN_BITFIELD | ||
207 | uint64_t reserved_16_63:48; | 590 | uint64_t reserved_16_63:48; |
208 | uint64_t sync3st:4; | 591 | uint64_t sync3st:4; |
209 | uint64_t sync2st:4; | 592 | uint64_t sync2st:4; |
210 | uint64_t sync1st:4; | 593 | uint64_t sync1st:4; |
211 | uint64_t sync0st:4; | 594 | uint64_t sync0st:4; |
595 | #else | ||
596 | uint64_t sync0st:4; | ||
597 | uint64_t sync1st:4; | ||
598 | uint64_t sync2st:4; | ||
599 | uint64_t sync3st:4; | ||
600 | uint64_t reserved_16_63:48; | ||
601 | #endif | ||
212 | } s; | 602 | } s; |
213 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; | 603 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; |
214 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; | 604 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; |
215 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; | 605 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; |
216 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; | 606 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; |
607 | struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx; | ||
608 | struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; | ||
609 | struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; | ||
610 | struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx; | ||
611 | struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx; | ||
612 | struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1; | ||
217 | }; | 613 | }; |
218 | 614 | ||
219 | union cvmx_pcsxx_spd_abil_reg { | 615 | union cvmx_pcsxx_spd_abil_reg { |
220 | uint64_t u64; | 616 | uint64_t u64; |
221 | struct cvmx_pcsxx_spd_abil_reg_s { | 617 | struct cvmx_pcsxx_spd_abil_reg_s { |
618 | #ifdef __BIG_ENDIAN_BITFIELD | ||
222 | uint64_t reserved_2_63:62; | 619 | uint64_t reserved_2_63:62; |
223 | uint64_t tenpasst:1; | 620 | uint64_t tenpasst:1; |
224 | uint64_t tengb:1; | 621 | uint64_t tengb:1; |
622 | #else | ||
623 | uint64_t tengb:1; | ||
624 | uint64_t tenpasst:1; | ||
625 | uint64_t reserved_2_63:62; | ||
626 | #endif | ||
225 | } s; | 627 | } s; |
226 | struct cvmx_pcsxx_spd_abil_reg_s cn52xx; | 628 | struct cvmx_pcsxx_spd_abil_reg_s cn52xx; |
227 | struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; | 629 | struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; |
228 | struct cvmx_pcsxx_spd_abil_reg_s cn56xx; | 630 | struct cvmx_pcsxx_spd_abil_reg_s cn56xx; |
229 | struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; | 631 | struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; |
632 | struct cvmx_pcsxx_spd_abil_reg_s cn61xx; | ||
633 | struct cvmx_pcsxx_spd_abil_reg_s cn63xx; | ||
634 | struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; | ||
635 | struct cvmx_pcsxx_spd_abil_reg_s cn66xx; | ||
636 | struct cvmx_pcsxx_spd_abil_reg_s cn68xx; | ||
637 | struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1; | ||
230 | }; | 638 | }; |
231 | 639 | ||
232 | union cvmx_pcsxx_status1_reg { | 640 | union cvmx_pcsxx_status1_reg { |
233 | uint64_t u64; | 641 | uint64_t u64; |
234 | struct cvmx_pcsxx_status1_reg_s { | 642 | struct cvmx_pcsxx_status1_reg_s { |
643 | #ifdef __BIG_ENDIAN_BITFIELD | ||
235 | uint64_t reserved_8_63:56; | 644 | uint64_t reserved_8_63:56; |
236 | uint64_t flt:1; | 645 | uint64_t flt:1; |
237 | uint64_t reserved_3_6:4; | 646 | uint64_t reserved_3_6:4; |
238 | uint64_t rcv_lnk:1; | 647 | uint64_t rcv_lnk:1; |
239 | uint64_t lpable:1; | 648 | uint64_t lpable:1; |
240 | uint64_t reserved_0_0:1; | 649 | uint64_t reserved_0_0:1; |
650 | #else | ||
651 | uint64_t reserved_0_0:1; | ||
652 | uint64_t lpable:1; | ||
653 | uint64_t rcv_lnk:1; | ||
654 | uint64_t reserved_3_6:4; | ||
655 | uint64_t flt:1; | ||
656 | uint64_t reserved_8_63:56; | ||
657 | #endif | ||
241 | } s; | 658 | } s; |
242 | struct cvmx_pcsxx_status1_reg_s cn52xx; | 659 | struct cvmx_pcsxx_status1_reg_s cn52xx; |
243 | struct cvmx_pcsxx_status1_reg_s cn52xxp1; | 660 | struct cvmx_pcsxx_status1_reg_s cn52xxp1; |
244 | struct cvmx_pcsxx_status1_reg_s cn56xx; | 661 | struct cvmx_pcsxx_status1_reg_s cn56xx; |
245 | struct cvmx_pcsxx_status1_reg_s cn56xxp1; | 662 | struct cvmx_pcsxx_status1_reg_s cn56xxp1; |
663 | struct cvmx_pcsxx_status1_reg_s cn61xx; | ||
664 | struct cvmx_pcsxx_status1_reg_s cn63xx; | ||
665 | struct cvmx_pcsxx_status1_reg_s cn63xxp1; | ||
666 | struct cvmx_pcsxx_status1_reg_s cn66xx; | ||
667 | struct cvmx_pcsxx_status1_reg_s cn68xx; | ||
668 | struct cvmx_pcsxx_status1_reg_s cn68xxp1; | ||
246 | }; | 669 | }; |
247 | 670 | ||
248 | union cvmx_pcsxx_status2_reg { | 671 | union cvmx_pcsxx_status2_reg { |
249 | uint64_t u64; | 672 | uint64_t u64; |
250 | struct cvmx_pcsxx_status2_reg_s { | 673 | struct cvmx_pcsxx_status2_reg_s { |
674 | #ifdef __BIG_ENDIAN_BITFIELD | ||
251 | uint64_t reserved_16_63:48; | 675 | uint64_t reserved_16_63:48; |
252 | uint64_t dev:2; | 676 | uint64_t dev:2; |
253 | uint64_t reserved_12_13:2; | 677 | uint64_t reserved_12_13:2; |
@@ -257,35 +681,73 @@ union cvmx_pcsxx_status2_reg { | |||
257 | uint64_t tengb_w:1; | 681 | uint64_t tengb_w:1; |
258 | uint64_t tengb_x:1; | 682 | uint64_t tengb_x:1; |
259 | uint64_t tengb_r:1; | 683 | uint64_t tengb_r:1; |
684 | #else | ||
685 | uint64_t tengb_r:1; | ||
686 | uint64_t tengb_x:1; | ||
687 | uint64_t tengb_w:1; | ||
688 | uint64_t reserved_3_9:7; | ||
689 | uint64_t rcvflt:1; | ||
690 | uint64_t xmtflt:1; | ||
691 | uint64_t reserved_12_13:2; | ||
692 | uint64_t dev:2; | ||
693 | uint64_t reserved_16_63:48; | ||
694 | #endif | ||
260 | } s; | 695 | } s; |
261 | struct cvmx_pcsxx_status2_reg_s cn52xx; | 696 | struct cvmx_pcsxx_status2_reg_s cn52xx; |
262 | struct cvmx_pcsxx_status2_reg_s cn52xxp1; | 697 | struct cvmx_pcsxx_status2_reg_s cn52xxp1; |
263 | struct cvmx_pcsxx_status2_reg_s cn56xx; | 698 | struct cvmx_pcsxx_status2_reg_s cn56xx; |
264 | struct cvmx_pcsxx_status2_reg_s cn56xxp1; | 699 | struct cvmx_pcsxx_status2_reg_s cn56xxp1; |
700 | struct cvmx_pcsxx_status2_reg_s cn61xx; | ||
701 | struct cvmx_pcsxx_status2_reg_s cn63xx; | ||
702 | struct cvmx_pcsxx_status2_reg_s cn63xxp1; | ||
703 | struct cvmx_pcsxx_status2_reg_s cn66xx; | ||
704 | struct cvmx_pcsxx_status2_reg_s cn68xx; | ||
705 | struct cvmx_pcsxx_status2_reg_s cn68xxp1; | ||
265 | }; | 706 | }; |
266 | 707 | ||
267 | union cvmx_pcsxx_tx_rx_polarity_reg { | 708 | union cvmx_pcsxx_tx_rx_polarity_reg { |
268 | uint64_t u64; | 709 | uint64_t u64; |
269 | struct cvmx_pcsxx_tx_rx_polarity_reg_s { | 710 | struct cvmx_pcsxx_tx_rx_polarity_reg_s { |
711 | #ifdef __BIG_ENDIAN_BITFIELD | ||
270 | uint64_t reserved_10_63:54; | 712 | uint64_t reserved_10_63:54; |
271 | uint64_t xor_rxplrt:4; | 713 | uint64_t xor_rxplrt:4; |
272 | uint64_t xor_txplrt:4; | 714 | uint64_t xor_txplrt:4; |
273 | uint64_t rxplrt:1; | 715 | uint64_t rxplrt:1; |
274 | uint64_t txplrt:1; | 716 | uint64_t txplrt:1; |
717 | #else | ||
718 | uint64_t txplrt:1; | ||
719 | uint64_t rxplrt:1; | ||
720 | uint64_t xor_txplrt:4; | ||
721 | uint64_t xor_rxplrt:4; | ||
722 | uint64_t reserved_10_63:54; | ||
723 | #endif | ||
275 | } s; | 724 | } s; |
276 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; | 725 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; |
277 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { | 726 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { |
727 | #ifdef __BIG_ENDIAN_BITFIELD | ||
278 | uint64_t reserved_2_63:62; | 728 | uint64_t reserved_2_63:62; |
279 | uint64_t rxplrt:1; | 729 | uint64_t rxplrt:1; |
280 | uint64_t txplrt:1; | 730 | uint64_t txplrt:1; |
731 | #else | ||
732 | uint64_t txplrt:1; | ||
733 | uint64_t rxplrt:1; | ||
734 | uint64_t reserved_2_63:62; | ||
735 | #endif | ||
281 | } cn52xxp1; | 736 | } cn52xxp1; |
282 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; | 737 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; |
283 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; | 738 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; |
739 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx; | ||
740 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; | ||
741 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; | ||
742 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx; | ||
743 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx; | ||
744 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1; | ||
284 | }; | 745 | }; |
285 | 746 | ||
286 | union cvmx_pcsxx_tx_rx_states_reg { | 747 | union cvmx_pcsxx_tx_rx_states_reg { |
287 | uint64_t u64; | 748 | uint64_t u64; |
288 | struct cvmx_pcsxx_tx_rx_states_reg_s { | 749 | struct cvmx_pcsxx_tx_rx_states_reg_s { |
750 | #ifdef __BIG_ENDIAN_BITFIELD | ||
289 | uint64_t reserved_14_63:50; | 751 | uint64_t reserved_14_63:50; |
290 | uint64_t term_err:1; | 752 | uint64_t term_err:1; |
291 | uint64_t syn3bad:1; | 753 | uint64_t syn3bad:1; |
@@ -296,9 +758,22 @@ union cvmx_pcsxx_tx_rx_states_reg { | |||
296 | uint64_t algn_st:3; | 758 | uint64_t algn_st:3; |
297 | uint64_t rx_st:2; | 759 | uint64_t rx_st:2; |
298 | uint64_t tx_st:3; | 760 | uint64_t tx_st:3; |
761 | #else | ||
762 | uint64_t tx_st:3; | ||
763 | uint64_t rx_st:2; | ||
764 | uint64_t algn_st:3; | ||
765 | uint64_t rxbad:1; | ||
766 | uint64_t syn0bad:1; | ||
767 | uint64_t syn1bad:1; | ||
768 | uint64_t syn2bad:1; | ||
769 | uint64_t syn3bad:1; | ||
770 | uint64_t term_err:1; | ||
771 | uint64_t reserved_14_63:50; | ||
772 | #endif | ||
299 | } s; | 773 | } s; |
300 | struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; | 774 | struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; |
301 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { | 775 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { |
776 | #ifdef __BIG_ENDIAN_BITFIELD | ||
302 | uint64_t reserved_13_63:51; | 777 | uint64_t reserved_13_63:51; |
303 | uint64_t syn3bad:1; | 778 | uint64_t syn3bad:1; |
304 | uint64_t syn2bad:1; | 779 | uint64_t syn2bad:1; |
@@ -308,9 +783,26 @@ union cvmx_pcsxx_tx_rx_states_reg { | |||
308 | uint64_t algn_st:3; | 783 | uint64_t algn_st:3; |
309 | uint64_t rx_st:2; | 784 | uint64_t rx_st:2; |
310 | uint64_t tx_st:3; | 785 | uint64_t tx_st:3; |
786 | #else | ||
787 | uint64_t tx_st:3; | ||
788 | uint64_t rx_st:2; | ||
789 | uint64_t algn_st:3; | ||
790 | uint64_t rxbad:1; | ||
791 | uint64_t syn0bad:1; | ||
792 | uint64_t syn1bad:1; | ||
793 | uint64_t syn2bad:1; | ||
794 | uint64_t syn3bad:1; | ||
795 | uint64_t reserved_13_63:51; | ||
796 | #endif | ||
311 | } cn52xxp1; | 797 | } cn52xxp1; |
312 | struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; | 798 | struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; |
313 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; | 799 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; |
800 | struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx; | ||
801 | struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; | ||
802 | struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; | ||
803 | struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx; | ||
804 | struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx; | ||
805 | struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1; | ||
314 | }; | 806 | }; |
315 | 807 | ||
316 | #endif | 808 | #endif |