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-rw-r--r--arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h67
-rw-r--r--arch/mips/include/asm/mach-mipssim/war.h25
2 files changed, 92 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
new file mode 100644
index 00000000000..27aaaa5d925
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
@@ -0,0 +1,67 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Chris Dearman
7 */
8#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
10
11
12/*
13 * CPU feature overrides for MIPS boards
14 */
15#ifdef CONFIG_CPU_MIPS32
16#define cpu_has_tlb 1
17#define cpu_has_4kex 1
18#define cpu_has_4k_cache 1
19#define cpu_has_fpu 0
20/* #define cpu_has_32fpr ? */
21#define cpu_has_counter 1
22/* #define cpu_has_watch ? */
23#define cpu_has_divec 1
24#define cpu_has_vce 0
25/* #define cpu_has_cache_cdex_p ? */
26/* #define cpu_has_cache_cdex_s ? */
27/* #define cpu_has_prefetch ? */
28#define cpu_has_mcheck 1
29/* #define cpu_has_ejtag ? */
30#define cpu_has_llsc 1
31/* #define cpu_has_vtag_icache ? */
32/* #define cpu_has_dc_aliases ? */
33/* #define cpu_has_ic_fills_f_dc ? */
34#define cpu_has_clo_clz 1
35#define cpu_has_nofpuex 0
36/* #define cpu_has_64bits ? */
37/* #define cpu_has_64bit_zero_reg ? */
38/* #define cpu_has_inclusive_pcaches ? */
39#endif
40
41#ifdef CONFIG_CPU_MIPS64
42#define cpu_has_tlb 1
43#define cpu_has_4kex 1
44#define cpu_has_4k_cache 1
45/* #define cpu_has_fpu ? */
46/* #define cpu_has_32fpr ? */
47#define cpu_has_counter 1
48/* #define cpu_has_watch ? */
49#define cpu_has_divec 1
50#define cpu_has_vce 0
51/* #define cpu_has_cache_cdex_p ? */
52/* #define cpu_has_cache_cdex_s ? */
53/* #define cpu_has_prefetch ? */
54#define cpu_has_mcheck 1
55/* #define cpu_has_ejtag ? */
56#define cpu_has_llsc 1
57/* #define cpu_has_vtag_icache ? */
58/* #define cpu_has_dc_aliases ? */
59/* #define cpu_has_ic_fills_f_dc ? */
60#define cpu_has_clo_clz 1
61#define cpu_has_nofpuex 0
62/* #define cpu_has_64bits ? */
63/* #define cpu_has_64bit_zero_reg ? */
64/* #define cpu_has_inclusive_pcaches ? */
65#endif
66
67#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-mipssim/war.h b/arch/mips/include/asm/mach-mipssim/war.h
new file mode 100644
index 00000000000..c8a74a3515e
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
9#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */