diff options
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1xxx_psc.h')
-rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h index 5a5cb738642..4e3f3bc26c6 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h | |||
@@ -33,19 +33,6 @@ | |||
33 | #ifndef _AU1000_PSC_H_ | 33 | #ifndef _AU1000_PSC_H_ |
34 | #define _AU1000_PSC_H_ | 34 | #define _AU1000_PSC_H_ |
35 | 35 | ||
36 | /* The PSC base addresses. */ | ||
37 | #ifdef CONFIG_SOC_AU1550 | ||
38 | #define PSC0_BASE_ADDR 0xb1a00000 | ||
39 | #define PSC1_BASE_ADDR 0xb1b00000 | ||
40 | #define PSC2_BASE_ADDR 0xb0a00000 | ||
41 | #define PSC3_BASE_ADDR 0xb0b00000 | ||
42 | #endif | ||
43 | |||
44 | #ifdef CONFIG_SOC_AU1200 | ||
45 | #define PSC0_BASE_ADDR 0xb1a00000 | ||
46 | #define PSC1_BASE_ADDR 0xb1b00000 | ||
47 | #endif | ||
48 | |||
49 | /* | 36 | /* |
50 | * The PSC select and control registers are common to all protocols. | 37 | * The PSC select and control registers are common to all protocols. |
51 | */ | 38 | */ |
@@ -80,19 +67,6 @@ | |||
80 | #define PSC_AC97GPO_OFFSET 0x00000028 | 67 | #define PSC_AC97GPO_OFFSET 0x00000028 |
81 | #define PSC_AC97GPI_OFFSET 0x0000002c | 68 | #define PSC_AC97GPI_OFFSET 0x0000002c |
82 | 69 | ||
83 | #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) | ||
84 | #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) | ||
85 | #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) | ||
86 | #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) | ||
87 | #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) | ||
88 | #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) | ||
89 | #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) | ||
90 | #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) | ||
91 | #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) | ||
92 | #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) | ||
93 | #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) | ||
94 | #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) | ||
95 | |||
96 | /* AC97 Config Register. */ | 70 | /* AC97 Config Register. */ |
97 | #define PSC_AC97CFG_RT_MASK (3 << 30) | 71 | #define PSC_AC97CFG_RT_MASK (3 << 30) |
98 | #define PSC_AC97CFG_RT_FIFO1 (0 << 30) | 72 | #define PSC_AC97CFG_RT_FIFO1 (0 << 30) |