diff options
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00/au1000.h')
| -rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1000.h | 559 |
1 files changed, 210 insertions, 349 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index f260ebed713..de24ec57dd2 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h | |||
| @@ -245,6 +245,23 @@ void alchemy_sleep_au1000(void); | |||
| 245 | void alchemy_sleep_au1550(void); | 245 | void alchemy_sleep_au1550(void); |
| 246 | void au_sleep(void); | 246 | void au_sleep(void); |
| 247 | 247 | ||
| 248 | /* USB: drivers/usb/host/alchemy-common.c */ | ||
| 249 | enum alchemy_usb_block { | ||
| 250 | ALCHEMY_USB_OHCI0, | ||
| 251 | ALCHEMY_USB_UDC0, | ||
| 252 | ALCHEMY_USB_EHCI0, | ||
| 253 | ALCHEMY_USB_OTG0, | ||
| 254 | }; | ||
| 255 | int alchemy_usb_control(int block, int enable); | ||
| 256 | |||
| 257 | /* PCI controller platform data */ | ||
| 258 | struct alchemy_pci_platdata { | ||
| 259 | int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); | ||
| 260 | int (*board_pci_idsel)(unsigned int devsel, int assert); | ||
| 261 | /* bits to set/clear in PCI_CONFIG register */ | ||
| 262 | unsigned long pci_cfg_set; | ||
| 263 | unsigned long pci_cfg_clr; | ||
| 264 | }; | ||
| 248 | 265 | ||
| 249 | /* SOC Interrupt numbers */ | 266 | /* SOC Interrupt numbers */ |
| 250 | 267 | ||
| @@ -575,38 +592,95 @@ enum soc_au1200_ints { | |||
| 575 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | 592 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ |
| 576 | 593 | ||
| 577 | /* | 594 | /* |
| 578 | * SDRAM register offsets | 595 | * Physical base addresses for integrated peripherals |
| 596 | * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 | ||
| 579 | */ | 597 | */ |
| 580 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ | ||
| 581 | defined(CONFIG_SOC_AU1100) | ||
| 582 | #define MEM_SDMODE0 0x0000 | ||
| 583 | #define MEM_SDMODE1 0x0004 | ||
| 584 | #define MEM_SDMODE2 0x0008 | ||
| 585 | #define MEM_SDADDR0 0x000C | ||
| 586 | #define MEM_SDADDR1 0x0010 | ||
| 587 | #define MEM_SDADDR2 0x0014 | ||
| 588 | #define MEM_SDREFCFG 0x0018 | ||
| 589 | #define MEM_SDPRECMD 0x001C | ||
| 590 | #define MEM_SDAUTOREF 0x0020 | ||
| 591 | #define MEM_SDWRMD0 0x0024 | ||
| 592 | #define MEM_SDWRMD1 0x0028 | ||
| 593 | #define MEM_SDWRMD2 0x002C | ||
| 594 | #define MEM_SDSLEEP 0x0030 | ||
| 595 | #define MEM_SDSMCKE 0x0034 | ||
| 596 | 598 | ||
| 597 | /* | 599 | #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ |
| 598 | * MEM_SDMODE register content definitions | 600 | #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ |
| 599 | */ | 601 | #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ |
| 602 | #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ | ||
| 603 | #define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ | ||
| 604 | #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ | ||
| 605 | #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ | ||
| 606 | #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ | ||
| 607 | #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ | ||
| 608 | #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ | ||
| 609 | #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ | ||
| 610 | #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ | ||
| 611 | #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ | ||
| 612 | #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ | ||
| 613 | #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ | ||
| 614 | #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ | ||
| 615 | #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ | ||
| 616 | #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ | ||
| 617 | #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ | ||
| 618 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ | ||
| 619 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ | ||
| 620 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ | ||
| 621 | #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ | ||
| 622 | #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ | ||
| 623 | #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ | ||
| 624 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ | ||
| 625 | #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ | ||
| 626 | #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ | ||
| 627 | #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ | ||
| 628 | #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ | ||
| 629 | #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ | ||
| 630 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ | ||
| 631 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ | ||
| 632 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ | ||
| 633 | #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ | ||
| 634 | #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ | ||
| 635 | #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ | ||
| 636 | #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ | ||
| 637 | #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ | ||
| 638 | #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ | ||
| 639 | #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ | ||
| 640 | #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ | ||
| 641 | #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ | ||
| 642 | #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ | ||
| 643 | #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ | ||
| 644 | #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ | ||
| 645 | #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ | ||
| 646 | #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ | ||
| 647 | #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ | ||
| 648 | #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ | ||
| 649 | #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ | ||
| 650 | #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ | ||
| 651 | #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ | ||
| 652 | #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ | ||
| 653 | #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ | ||
| 654 | #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ | ||
| 655 | |||
| 656 | |||
| 657 | /* Au1000 SDRAM memory controller register offsets */ | ||
| 658 | #define AU1000_MEM_SDMODE0 0x0000 | ||
| 659 | #define AU1000_MEM_SDMODE1 0x0004 | ||
| 660 | #define AU1000_MEM_SDMODE2 0x0008 | ||
| 661 | #define AU1000_MEM_SDADDR0 0x000C | ||
| 662 | #define AU1000_MEM_SDADDR1 0x0010 | ||
| 663 | #define AU1000_MEM_SDADDR2 0x0014 | ||
| 664 | #define AU1000_MEM_SDREFCFG 0x0018 | ||
| 665 | #define AU1000_MEM_SDPRECMD 0x001C | ||
| 666 | #define AU1000_MEM_SDAUTOREF 0x0020 | ||
| 667 | #define AU1000_MEM_SDWRMD0 0x0024 | ||
| 668 | #define AU1000_MEM_SDWRMD1 0x0028 | ||
| 669 | #define AU1000_MEM_SDWRMD2 0x002C | ||
| 670 | #define AU1000_MEM_SDSLEEP 0x0030 | ||
| 671 | #define AU1000_MEM_SDSMCKE 0x0034 | ||
| 672 | |||
| 673 | /* MEM_SDMODE register content definitions */ | ||
| 600 | #define MEM_SDMODE_F (1 << 22) | 674 | #define MEM_SDMODE_F (1 << 22) |
| 601 | #define MEM_SDMODE_SR (1 << 21) | 675 | #define MEM_SDMODE_SR (1 << 21) |
| 602 | #define MEM_SDMODE_BS (1 << 20) | 676 | #define MEM_SDMODE_BS (1 << 20) |
| 603 | #define MEM_SDMODE_RS (3 << 18) | 677 | #define MEM_SDMODE_RS (3 << 18) |
| 604 | #define MEM_SDMODE_CS (7 << 15) | 678 | #define MEM_SDMODE_CS (7 << 15) |
| 605 | #define MEM_SDMODE_TRAS (15 << 11) | 679 | #define MEM_SDMODE_TRAS (15 << 11) |
| 606 | #define MEM_SDMODE_TMRD (3 << 9) | 680 | #define MEM_SDMODE_TMRD (3 << 9) |
| 607 | #define MEM_SDMODE_TWR (3 << 7) | 681 | #define MEM_SDMODE_TWR (3 << 7) |
| 608 | #define MEM_SDMODE_TRP (3 << 5) | 682 | #define MEM_SDMODE_TRP (3 << 5) |
| 609 | #define MEM_SDMODE_TRCD (3 << 3) | 683 | #define MEM_SDMODE_TRCD (3 << 3) |
| 610 | #define MEM_SDMODE_TCL (7 << 0) | 684 | #define MEM_SDMODE_TCL (7 << 0) |
| 611 | 685 | ||
| 612 | #define MEM_SDMODE_BS_2Bank (0 << 20) | 686 | #define MEM_SDMODE_BS_2Bank (0 << 20) |
| @@ -628,173 +702,43 @@ enum soc_au1200_ints { | |||
| 628 | #define MEM_SDMODE_TRCD_N(N) ((N) << 3) | 702 | #define MEM_SDMODE_TRCD_N(N) ((N) << 3) |
| 629 | #define MEM_SDMODE_TCL_N(N) ((N) << 0) | 703 | #define MEM_SDMODE_TCL_N(N) ((N) << 0) |
| 630 | 704 | ||
| 631 | /* | 705 | /* MEM_SDADDR register contents definitions */ |
| 632 | * MEM_SDADDR register contents definitions | ||
| 633 | */ | ||
| 634 | #define MEM_SDADDR_E (1 << 20) | 706 | #define MEM_SDADDR_E (1 << 20) |
| 635 | #define MEM_SDADDR_CSBA (0x03FF << 10) | 707 | #define MEM_SDADDR_CSBA (0x03FF << 10) |
| 636 | #define MEM_SDADDR_CSMASK (0x03FF << 0) | 708 | #define MEM_SDADDR_CSMASK (0x03FF << 0) |
| 637 | #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) | 709 | #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) |
| 638 | #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) | 710 | #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) |
| 639 | 711 | ||
| 640 | /* | 712 | /* MEM_SDREFCFG register content definitions */ |
| 641 | * MEM_SDREFCFG register content definitions | ||
| 642 | */ | ||
| 643 | #define MEM_SDREFCFG_TRC (15 << 28) | 713 | #define MEM_SDREFCFG_TRC (15 << 28) |
| 644 | #define MEM_SDREFCFG_TRPM (3 << 26) | 714 | #define MEM_SDREFCFG_TRPM (3 << 26) |
| 645 | #define MEM_SDREFCFG_E (1 << 25) | 715 | #define MEM_SDREFCFG_E (1 << 25) |
| 646 | #define MEM_SDREFCFG_RE (0x1ffffff << 0) | 716 | #define MEM_SDREFCFG_RE (0x1ffffff << 0) |
| 647 | #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) | 717 | #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) |
| 648 | #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) | 718 | #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) |
| 649 | #define MEM_SDREFCFG_REF_N(N) (N) | 719 | #define MEM_SDREFCFG_REF_N(N) (N) |
| 650 | #endif | ||
| 651 | |||
| 652 | /***********************************************************************/ | ||
| 653 | 720 | ||
| 654 | /* | 721 | /* Au1550 SDRAM Register Offsets */ |
| 655 | * Au1550 SDRAM Register Offsets | 722 | #define AU1550_MEM_SDMODE0 0x0800 |
| 656 | */ | 723 | #define AU1550_MEM_SDMODE1 0x0808 |
| 657 | 724 | #define AU1550_MEM_SDMODE2 0x0810 | |
| 658 | /***********************************************************************/ | 725 | #define AU1550_MEM_SDADDR0 0x0820 |
| 659 | 726 | #define AU1550_MEM_SDADDR1 0x0828 | |
| 660 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | 727 | #define AU1550_MEM_SDADDR2 0x0830 |
| 661 | #define MEM_SDMODE0 0x0800 | 728 | #define AU1550_MEM_SDCONFIGA 0x0840 |
| 662 | #define MEM_SDMODE1 0x0808 | 729 | #define AU1550_MEM_SDCONFIGB 0x0848 |
| 663 | #define MEM_SDMODE2 0x0810 | 730 | #define AU1550_MEM_SDSTAT 0x0850 |
| 664 | #define MEM_SDADDR0 0x0820 | 731 | #define AU1550_MEM_SDERRADDR 0x0858 |
| 665 | #define MEM_SDADDR1 0x0828 | 732 | #define AU1550_MEM_SDSTRIDE0 0x0860 |
| 666 | #define MEM_SDADDR2 0x0830 | 733 | #define AU1550_MEM_SDSTRIDE1 0x0868 |
| 667 | #define MEM_SDCONFIGA 0x0840 | 734 | #define AU1550_MEM_SDSTRIDE2 0x0870 |
| 668 | #define MEM_SDCONFIGB 0x0848 | 735 | #define AU1550_MEM_SDWRMD0 0x0880 |
| 669 | #define MEM_SDSTAT 0x0850 | 736 | #define AU1550_MEM_SDWRMD1 0x0888 |
| 670 | #define MEM_SDERRADDR 0x0858 | 737 | #define AU1550_MEM_SDWRMD2 0x0890 |
| 671 | #define MEM_SDSTRIDE0 0x0860 | 738 | #define AU1550_MEM_SDPRECMD 0x08C0 |
| 672 | #define MEM_SDSTRIDE1 0x0868 | 739 | #define AU1550_MEM_SDAUTOREF 0x08C8 |
| 673 | #define MEM_SDSTRIDE2 0x0870 | 740 | #define AU1550_MEM_SDSREF 0x08D0 |
| 674 | #define MEM_SDWRMD0 0x0880 | 741 | #define AU1550_MEM_SDSLEEP MEM_SDSREF |
| 675 | #define MEM_SDWRMD1 0x0888 | ||
| 676 | #define MEM_SDWRMD2 0x0890 | ||
| 677 | #define MEM_SDPRECMD 0x08C0 | ||
| 678 | #define MEM_SDAUTOREF 0x08C8 | ||
| 679 | #define MEM_SDSREF 0x08D0 | ||
| 680 | #define MEM_SDSLEEP MEM_SDSREF | ||
| 681 | |||
| 682 | #endif | ||
| 683 | |||
| 684 | /* | ||
| 685 | * Physical base addresses for integrated peripherals | ||
| 686 | * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 | ||
| 687 | */ | ||
| 688 | |||
| 689 | #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ | ||
| 690 | #define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */ | ||
| 691 | #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ | ||
| 692 | #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ | ||
| 693 | #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ | ||
| 694 | #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ | ||
| 695 | #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ | ||
| 696 | #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ | ||
| 697 | #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ | ||
| 698 | #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ | ||
| 699 | #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ | ||
| 700 | #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ | ||
| 701 | #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ | ||
| 702 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ | ||
| 703 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ | ||
| 704 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ | ||
| 705 | #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ | ||
| 706 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ | ||
| 707 | #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ | ||
| 708 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ | ||
| 709 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ | ||
| 710 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ | ||
| 711 | #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ | ||
| 712 | #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ | ||
| 713 | |||
| 714 | |||
| 715 | #ifdef CONFIG_SOC_AU1000 | ||
| 716 | #define MEM_PHYS_ADDR 0x14000000 | ||
| 717 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | ||
| 718 | #define USBH_PHYS_ADDR 0x10100000 | ||
| 719 | #define IRDA_PHYS_ADDR 0x10300000 | ||
| 720 | #define SSI0_PHYS_ADDR 0x11600000 | ||
| 721 | #define SSI1_PHYS_ADDR 0x11680000 | ||
| 722 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | ||
| 723 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | ||
| 724 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | ||
| 725 | #endif | ||
| 726 | |||
| 727 | /********************************************************************/ | ||
| 728 | |||
| 729 | #ifdef CONFIG_SOC_AU1500 | ||
| 730 | #define MEM_PHYS_ADDR 0x14000000 | ||
| 731 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | ||
| 732 | #define USBH_PHYS_ADDR 0x10100000 | ||
| 733 | #define PCI_PHYS_ADDR 0x14005000 | ||
| 734 | #define PCI_MEM_PHYS_ADDR 0x400000000ULL | ||
| 735 | #define PCI_IO_PHYS_ADDR 0x500000000ULL | ||
| 736 | #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL | ||
| 737 | #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL | ||
| 738 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | ||
| 739 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | ||
| 740 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | ||
| 741 | #endif | ||
| 742 | |||
| 743 | /********************************************************************/ | ||
| 744 | |||
| 745 | #ifdef CONFIG_SOC_AU1100 | ||
| 746 | #define MEM_PHYS_ADDR 0x14000000 | ||
| 747 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | ||
| 748 | #define USBH_PHYS_ADDR 0x10100000 | ||
| 749 | #define IRDA_PHYS_ADDR 0x10300000 | ||
| 750 | #define SSI0_PHYS_ADDR 0x11600000 | ||
| 751 | #define SSI1_PHYS_ADDR 0x11680000 | ||
| 752 | #define LCD_PHYS_ADDR 0x15000000 | ||
| 753 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | ||
| 754 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | ||
| 755 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | ||
| 756 | #endif | ||
| 757 | |||
| 758 | /***********************************************************************/ | ||
| 759 | |||
| 760 | #ifdef CONFIG_SOC_AU1550 | ||
| 761 | #define MEM_PHYS_ADDR 0x14000000 | ||
| 762 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | ||
| 763 | #define USBH_PHYS_ADDR 0x14020000 | ||
| 764 | #define PCI_PHYS_ADDR 0x14005000 | ||
| 765 | #define PE_PHYS_ADDR 0x14008000 | ||
| 766 | #define PSC0_PHYS_ADDR 0x11A00000 | ||
| 767 | #define PSC1_PHYS_ADDR 0x11B00000 | ||
| 768 | #define PSC2_PHYS_ADDR 0x10A00000 | ||
| 769 | #define PSC3_PHYS_ADDR 0x10B00000 | ||
| 770 | #define PCI_MEM_PHYS_ADDR 0x400000000ULL | ||
| 771 | #define PCI_IO_PHYS_ADDR 0x500000000ULL | ||
| 772 | #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL | ||
| 773 | #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL | ||
| 774 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | ||
| 775 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | ||
| 776 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | ||
| 777 | #endif | ||
| 778 | |||
| 779 | /***********************************************************************/ | ||
| 780 | |||
| 781 | #ifdef CONFIG_SOC_AU1200 | ||
| 782 | #define MEM_PHYS_ADDR 0x14000000 | ||
| 783 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | ||
| 784 | #define AES_PHYS_ADDR 0x10300000 | ||
| 785 | #define CIM_PHYS_ADDR 0x14004000 | ||
| 786 | #define USBM_PHYS_ADDR 0x14020000 | ||
| 787 | #define USBH_PHYS_ADDR 0x14020100 | ||
| 788 | #define PSC0_PHYS_ADDR 0x11A00000 | ||
| 789 | #define PSC1_PHYS_ADDR 0x11B00000 | ||
| 790 | #define LCD_PHYS_ADDR 0x15000000 | ||
| 791 | #define SWCNT_PHYS_ADDR 0x1110010C | ||
| 792 | #define MAEFE_PHYS_ADDR 0x14012000 | ||
| 793 | #define MAEBE_PHYS_ADDR 0x14010000 | ||
| 794 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | ||
| 795 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | ||
| 796 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | ||
| 797 | #endif | ||
| 798 | 742 | ||
| 799 | /* Static Bus Controller */ | 743 | /* Static Bus Controller */ |
| 800 | #define MEM_STCFG0 0xB4001000 | 744 | #define MEM_STCFG0 0xB4001000 |
| @@ -813,81 +757,14 @@ enum soc_au1200_ints { | |||
| 813 | #define MEM_STTIME3 0xB4001034 | 757 | #define MEM_STTIME3 0xB4001034 |
| 814 | #define MEM_STADDR3 0xB4001038 | 758 | #define MEM_STADDR3 0xB4001038 |
| 815 | 759 | ||
| 816 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | ||
| 817 | #define MEM_STNDCTL 0xB4001100 | 760 | #define MEM_STNDCTL 0xB4001100 |
| 818 | #define MEM_STSTAT 0xB4001104 | 761 | #define MEM_STSTAT 0xB4001104 |
| 819 | 762 | ||
| 820 | #define MEM_STNAND_CMD 0x0 | 763 | #define MEM_STNAND_CMD 0x0 |
| 821 | #define MEM_STNAND_ADDR 0x4 | 764 | #define MEM_STNAND_ADDR 0x4 |
| 822 | #define MEM_STNAND_DATA 0x20 | 765 | #define MEM_STNAND_DATA 0x20 |
| 823 | #endif | ||
| 824 | |||
| 825 | 766 | ||
| 826 | 767 | ||
| 827 | |||
| 828 | /* Au1000 */ | ||
| 829 | #ifdef CONFIG_SOC_AU1000 | ||
| 830 | |||
| 831 | #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ | ||
| 832 | #define USB_HOST_CONFIG 0xB017FFFC | ||
| 833 | #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT | ||
| 834 | #endif /* CONFIG_SOC_AU1000 */ | ||
| 835 | |||
| 836 | /* Au1500 */ | ||
| 837 | #ifdef CONFIG_SOC_AU1500 | ||
| 838 | |||
| 839 | #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ | ||
| 840 | #define USB_HOST_CONFIG 0xB017fffc | ||
| 841 | #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT | ||
| 842 | #endif /* CONFIG_SOC_AU1500 */ | ||
| 843 | |||
| 844 | /* Au1100 */ | ||
| 845 | #ifdef CONFIG_SOC_AU1100 | ||
| 846 | |||
| 847 | #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ | ||
| 848 | #define USB_HOST_CONFIG 0xB017FFFC | ||
| 849 | #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT | ||
| 850 | #endif /* CONFIG_SOC_AU1100 */ | ||
| 851 | |||
| 852 | #ifdef CONFIG_SOC_AU1550 | ||
| 853 | |||
| 854 | #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ | ||
| 855 | #define USB_OHCI_LEN 0x00060000 | ||
| 856 | #define USB_HOST_CONFIG 0xB4027ffc | ||
| 857 | #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT | ||
| 858 | #endif /* CONFIG_SOC_AU1550 */ | ||
| 859 | |||
| 860 | |||
| 861 | #ifdef CONFIG_SOC_AU1200 | ||
| 862 | |||
| 863 | #define USB_UOC_BASE 0x14020020 | ||
| 864 | #define USB_UOC_LEN 0x20 | ||
| 865 | #define USB_OHCI_BASE 0x14020100 | ||
| 866 | #define USB_OHCI_LEN 0x100 | ||
| 867 | #define USB_EHCI_BASE 0x14020200 | ||
| 868 | #define USB_EHCI_LEN 0x100 | ||
| 869 | #define USB_UDC_BASE 0x14022000 | ||
| 870 | #define USB_UDC_LEN 0x2000 | ||
| 871 | #define USB_MSR_BASE 0xB4020000 | ||
| 872 | #define USB_MSR_MCFG 4 | ||
| 873 | #define USBMSRMCFG_OMEMEN 0 | ||
| 874 | #define USBMSRMCFG_OBMEN 1 | ||
| 875 | #define USBMSRMCFG_EMEMEN 2 | ||
| 876 | #define USBMSRMCFG_EBMEN 3 | ||
| 877 | #define USBMSRMCFG_DMEMEN 4 | ||
| 878 | #define USBMSRMCFG_DBMEN 5 | ||
| 879 | #define USBMSRMCFG_GMEMEN 6 | ||
| 880 | #define USBMSRMCFG_OHCCLKEN 16 | ||
| 881 | #define USBMSRMCFG_EHCCLKEN 17 | ||
| 882 | #define USBMSRMCFG_UDCCLKEN 18 | ||
| 883 | #define USBMSRMCFG_PHYPLLEN 19 | ||
| 884 | #define USBMSRMCFG_RDCOMB 30 | ||
| 885 | #define USBMSRMCFG_PFEN 31 | ||
| 886 | |||
| 887 | #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT | ||
| 888 | |||
| 889 | #endif /* CONFIG_SOC_AU1200 */ | ||
| 890 | |||
| 891 | /* Programmable Counters 0 and 1 */ | 768 | /* Programmable Counters 0 and 1 */ |
| 892 | #define SYS_BASE 0xB1900000 | 769 | #define SYS_BASE 0xB1900000 |
| 893 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | 770 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) |
| @@ -958,56 +835,6 @@ enum soc_au1200_ints { | |||
| 958 | # define I2S_CONTROL_D (1 << 1) | 835 | # define I2S_CONTROL_D (1 << 1) |
| 959 | # define I2S_CONTROL_CE (1 << 0) | 836 | # define I2S_CONTROL_CE (1 << 0) |
| 960 | 837 | ||
| 961 | /* USB Host Controller */ | ||
| 962 | #ifndef USB_OHCI_LEN | ||
| 963 | #define USB_OHCI_LEN 0x00100000 | ||
| 964 | #endif | ||
| 965 | |||
| 966 | #ifndef CONFIG_SOC_AU1200 | ||
| 967 | |||
| 968 | /* USB Device Controller */ | ||
| 969 | #define USBD_EP0RD 0xB0200000 | ||
| 970 | #define USBD_EP0WR 0xB0200004 | ||
| 971 | #define USBD_EP2WR 0xB0200008 | ||
| 972 | #define USBD_EP3WR 0xB020000C | ||
| 973 | #define USBD_EP4RD 0xB0200010 | ||
| 974 | #define USBD_EP5RD 0xB0200014 | ||
| 975 | #define USBD_INTEN 0xB0200018 | ||
| 976 | #define USBD_INTSTAT 0xB020001C | ||
| 977 | # define USBDEV_INT_SOF (1 << 12) | ||
| 978 | # define USBDEV_INT_HF_BIT 6 | ||
| 979 | # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) | ||
| 980 | # define USBDEV_INT_CMPLT_BIT 0 | ||
| 981 | # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) | ||
| 982 | #define USBD_CONFIG 0xB0200020 | ||
| 983 | #define USBD_EP0CS 0xB0200024 | ||
| 984 | #define USBD_EP2CS 0xB0200028 | ||
| 985 | #define USBD_EP3CS 0xB020002C | ||
| 986 | #define USBD_EP4CS 0xB0200030 | ||
| 987 | #define USBD_EP5CS 0xB0200034 | ||
| 988 | # define USBDEV_CS_SU (1 << 14) | ||
| 989 | # define USBDEV_CS_NAK (1 << 13) | ||
| 990 | # define USBDEV_CS_ACK (1 << 12) | ||
| 991 | # define USBDEV_CS_BUSY (1 << 11) | ||
| 992 | # define USBDEV_CS_TSIZE_BIT 1 | ||
| 993 | # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) | ||
| 994 | # define USBDEV_CS_STALL (1 << 0) | ||
| 995 | #define USBD_EP0RDSTAT 0xB0200040 | ||
| 996 | #define USBD_EP0WRSTAT 0xB0200044 | ||
| 997 | #define USBD_EP2WRSTAT 0xB0200048 | ||
| 998 | #define USBD_EP3WRSTAT 0xB020004C | ||
| 999 | #define USBD_EP4RDSTAT 0xB0200050 | ||
| 1000 | #define USBD_EP5RDSTAT 0xB0200054 | ||
| 1001 | # define USBDEV_FSTAT_FLUSH (1 << 6) | ||
| 1002 | # define USBDEV_FSTAT_UF (1 << 5) | ||
| 1003 | # define USBDEV_FSTAT_OF (1 << 4) | ||
| 1004 | # define USBDEV_FSTAT_FCNT_BIT 0 | ||
| 1005 | # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) | ||
| 1006 | #define USBD_ENABLE 0xB0200058 | ||
| 1007 | # define USBDEV_ENABLE (1 << 1) | ||
| 1008 | # define USBDEV_CE (1 << 0) | ||
| 1009 | |||
| 1010 | #endif /* !CONFIG_SOC_AU1200 */ | ||
| 1011 | 838 | ||
| 1012 | /* Ethernet Controllers */ | 839 | /* Ethernet Controllers */ |
| 1013 | 840 | ||
| @@ -1322,7 +1149,6 @@ enum soc_au1200_ints { | |||
| 1322 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | 1149 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) |
| 1323 | 1150 | ||
| 1324 | /* Au1200 only */ | 1151 | /* Au1200 only */ |
| 1325 | #ifdef CONFIG_SOC_AU1200 | ||
| 1326 | #define SYS_PINFUNC_DMA (1 << 31) | 1152 | #define SYS_PINFUNC_DMA (1 << 31) |
| 1327 | #define SYS_PINFUNC_S0A (1 << 30) | 1153 | #define SYS_PINFUNC_S0A (1 << 30) |
| 1328 | #define SYS_PINFUNC_S1A (1 << 29) | 1154 | #define SYS_PINFUNC_S1A (1 << 29) |
| @@ -1350,7 +1176,6 @@ enum soc_au1200_ints { | |||
| 1350 | #define SYS_PINFUNC_P0B (1 << 4) | 1176 | #define SYS_PINFUNC_P0B (1 << 4) |
| 1351 | #define SYS_PINFUNC_U0T (1 << 3) | 1177 | #define SYS_PINFUNC_U0T (1 << 3) |
| 1352 | #define SYS_PINFUNC_S1B (1 << 2) | 1178 | #define SYS_PINFUNC_S1B (1 << 2) |
| 1353 | #endif | ||
| 1354 | 1179 | ||
| 1355 | /* Power Management */ | 1180 | /* Power Management */ |
| 1356 | #define SYS_SCRATCH0 0xB1900018 | 1181 | #define SYS_SCRATCH0 0xB1900018 |
| @@ -1406,12 +1231,12 @@ enum soc_au1200_ints { | |||
| 1406 | # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) | 1231 | # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) |
| 1407 | # define SYS_CS_DI2 (1 << 16) | 1232 | # define SYS_CS_DI2 (1 << 16) |
| 1408 | # define SYS_CS_CI2 (1 << 15) | 1233 | # define SYS_CS_CI2 (1 << 15) |
| 1409 | #ifdef CONFIG_SOC_AU1100 | 1234 | |
| 1410 | # define SYS_CS_ML_BIT 7 | 1235 | # define SYS_CS_ML_BIT 7 |
| 1411 | # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) | 1236 | # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) |
| 1412 | # define SYS_CS_DL (1 << 6) | 1237 | # define SYS_CS_DL (1 << 6) |
| 1413 | # define SYS_CS_CL (1 << 5) | 1238 | # define SYS_CS_CL (1 << 5) |
| 1414 | #else | 1239 | |
| 1415 | # define SYS_CS_MUH_BIT 12 | 1240 | # define SYS_CS_MUH_BIT 12 |
| 1416 | # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) | 1241 | # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) |
| 1417 | # define SYS_CS_DUH (1 << 11) | 1242 | # define SYS_CS_DUH (1 << 11) |
| @@ -1420,7 +1245,7 @@ enum soc_au1200_ints { | |||
| 1420 | # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) | 1245 | # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) |
| 1421 | # define SYS_CS_DUD (1 << 6) | 1246 | # define SYS_CS_DUD (1 << 6) |
| 1422 | # define SYS_CS_CUD (1 << 5) | 1247 | # define SYS_CS_CUD (1 << 5) |
| 1423 | #endif | 1248 | |
| 1424 | # define SYS_CS_MIR_BIT 2 | 1249 | # define SYS_CS_MIR_BIT 2 |
| 1425 | # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) | 1250 | # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) |
| 1426 | # define SYS_CS_DIR (1 << 1) | 1251 | # define SYS_CS_DIR (1 << 1) |
| @@ -1467,58 +1292,30 @@ enum soc_au1200_ints { | |||
| 1467 | # define AC97C_RS (1 << 1) | 1292 | # define AC97C_RS (1 << 1) |
| 1468 | # define AC97C_CE (1 << 0) | 1293 | # define AC97C_CE (1 << 0) |
| 1469 | 1294 | ||
| 1470 | #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) | ||
| 1471 | /* Au1500 PCI Controller */ | ||
| 1472 | #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ | ||
| 1473 | #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) | ||
| 1474 | #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) | ||
| 1475 | # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ | ||
| 1476 | (1 << 25) | (1 << 26) | (1 << 27)) | ||
| 1477 | #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) | ||
| 1478 | #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) | ||
| 1479 | #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) | ||
| 1480 | #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) | ||
| 1481 | #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) | ||
| 1482 | #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) | ||
| 1483 | #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) | ||
| 1484 | #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) | ||
| 1485 | #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) | ||
| 1486 | #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) | ||
| 1487 | #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) | ||
| 1488 | #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) | ||
| 1489 | |||
| 1490 | #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ | ||
| 1491 | 1295 | ||
| 1492 | /* | 1296 | /* The PCI chip selects are outside the 32bit space, and since we can't |
| 1493 | * All of our structures, like PCI resource, have 32-bit members. | 1297 | * just program the 36bit addresses into BARs, we have to take a chunk |
| 1494 | * Drivers are expected to do an ioremap on the PCI MEM resource, but it's | 1298 | * out of the 32bit space and reserve it for PCI. When these addresses |
| 1495 | * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch | 1299 | * are ioremap()ed, they'll be fixed up to the real 36bit address before |
| 1496 | * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and | 1300 | * being passed to the real ioremap function. |
| 1497 | * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM | ||
| 1498 | * addresses. For PCI I/O, it's simpler because we get to do the ioremap | ||
| 1499 | * ourselves and then adjust the device's resources. | ||
| 1500 | */ | 1301 | */ |
| 1501 | #define Au1500_EXT_CFG 0x600000000ULL | 1302 | #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) |
| 1502 | #define Au1500_EXT_CFG_TYPE1 0x680000000ULL | 1303 | #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) |
| 1503 | #define Au1500_PCI_IO_START 0x500000000ULL | ||
| 1504 | #define Au1500_PCI_IO_END 0x5000FFFFFULL | ||
| 1505 | #define Au1500_PCI_MEM_START 0x440000000ULL | ||
| 1506 | #define Au1500_PCI_MEM_END 0x44FFFFFFFULL | ||
| 1507 | 1304 | ||
| 1508 | #define PCI_IO_START 0x00001000 | 1305 | /* for PCI IO it's simpler because we get to do the ioremap ourselves and then |
| 1509 | #define PCI_IO_END 0x000FFFFF | 1306 | * adjust the device's resources. |
| 1510 | #define PCI_MEM_START 0x40000000 | 1307 | */ |
| 1511 | #define PCI_MEM_END 0x4FFFFFFF | 1308 | #define ALCHEMY_PCI_IOWIN_START 0x00001000 |
| 1309 | #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF | ||
| 1512 | 1310 | ||
| 1513 | #define PCI_FIRST_DEVFN (0 << 3) | 1311 | #ifdef CONFIG_PCI |
| 1514 | #define PCI_LAST_DEVFN (19 << 3) | ||
| 1515 | 1312 | ||
| 1516 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ | 1313 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ |
| 1517 | #define IOPORT_RESOURCE_END 0xffffffff | 1314 | #define IOPORT_RESOURCE_END 0xffffffff |
| 1518 | #define IOMEM_RESOURCE_START 0x10000000 | 1315 | #define IOMEM_RESOURCE_START 0x10000000 |
| 1519 | #define IOMEM_RESOURCE_END 0xfffffffffULL | 1316 | #define IOMEM_RESOURCE_END 0xfffffffffULL |
| 1520 | 1317 | ||
| 1521 | #else /* Au1000 and Au1100 and Au1200 */ | 1318 | #else |
| 1522 | 1319 | ||
| 1523 | /* Don't allow any legacy ports probing */ | 1320 | /* Don't allow any legacy ports probing */ |
| 1524 | #define IOPORT_RESOURCE_START 0x10000000 | 1321 | #define IOPORT_RESOURCE_START 0x10000000 |
| @@ -1526,13 +1323,77 @@ enum soc_au1200_ints { | |||
| 1526 | #define IOMEM_RESOURCE_START 0x10000000 | 1323 | #define IOMEM_RESOURCE_START 0x10000000 |
| 1527 | #define IOMEM_RESOURCE_END 0xfffffffffULL | 1324 | #define IOMEM_RESOURCE_END 0xfffffffffULL |
| 1528 | 1325 | ||
| 1529 | #define PCI_IO_START 0 | ||
| 1530 | #define PCI_IO_END 0 | ||
| 1531 | #define PCI_MEM_START 0 | ||
| 1532 | #define PCI_MEM_END 0 | ||
| 1533 | #define PCI_FIRST_DEVFN 0 | ||
| 1534 | #define PCI_LAST_DEVFN 0 | ||
| 1535 | |||
| 1536 | #endif | 1326 | #endif |
| 1537 | 1327 | ||
| 1328 | /* PCI controller block register offsets */ | ||
| 1329 | #define PCI_REG_CMEM 0x0000 | ||
| 1330 | #define PCI_REG_CONFIG 0x0004 | ||
| 1331 | #define PCI_REG_B2BMASK_CCH 0x0008 | ||
| 1332 | #define PCI_REG_B2BBASE0_VID 0x000C | ||
| 1333 | #define PCI_REG_B2BBASE1_SID 0x0010 | ||
| 1334 | #define PCI_REG_MWMASK_DEV 0x0014 | ||
| 1335 | #define PCI_REG_MWBASE_REV_CCL 0x0018 | ||
| 1336 | #define PCI_REG_ERR_ADDR 0x001C | ||
| 1337 | #define PCI_REG_SPEC_INTACK 0x0020 | ||
| 1338 | #define PCI_REG_ID 0x0100 | ||
| 1339 | #define PCI_REG_STATCMD 0x0104 | ||
| 1340 | #define PCI_REG_CLASSREV 0x0108 | ||
| 1341 | #define PCI_REG_PARAM 0x010C | ||
| 1342 | #define PCI_REG_MBAR 0x0110 | ||
| 1343 | #define PCI_REG_TIMEOUT 0x0140 | ||
| 1344 | |||
| 1345 | /* PCI controller block register bits */ | ||
| 1346 | #define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ | ||
| 1347 | #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) | ||
| 1348 | #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) | ||
| 1349 | #define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ | ||
| 1350 | #define PCI_CONFIG_ET (1 << 26) /* error in target mode */ | ||
| 1351 | #define PCI_CONFIG_EF (1 << 25) /* fatal error */ | ||
| 1352 | #define PCI_CONFIG_EP (1 << 24) /* parity error */ | ||
| 1353 | #define PCI_CONFIG_EM (1 << 23) /* multiple errors */ | ||
| 1354 | #define PCI_CONFIG_BM (1 << 22) /* bad master error */ | ||
| 1355 | #define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ | ||
| 1356 | #define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ | ||
| 1357 | #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ | ||
| 1358 | #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ | ||
| 1359 | #define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ | ||
| 1360 | #define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ | ||
| 1361 | #define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ | ||
| 1362 | #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ | ||
| 1363 | #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ | ||
| 1364 | #define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ | ||
| 1365 | #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ | ||
| 1366 | #define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ | ||
| 1367 | #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ | ||
| 1368 | #define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ | ||
| 1369 | #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ | ||
| 1370 | #define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ | ||
| 1371 | #define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ | ||
| 1372 | #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ | ||
| 1373 | #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ | ||
| 1374 | #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ | ||
| 1375 | #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) | ||
| 1376 | #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ | ||
| 1377 | #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) | ||
| 1378 | #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) | ||
| 1379 | #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) | ||
| 1380 | #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) | ||
| 1381 | #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) | ||
| 1382 | #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) | ||
| 1383 | #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) | ||
| 1384 | #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) | ||
| 1385 | #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) | ||
| 1386 | #define PCI_ID_DID(x) (((x) & 0xffff) << 16) | ||
| 1387 | #define PCI_ID_VID(x) ((x) & 0xffff) | ||
| 1388 | #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) | ||
| 1389 | #define PCI_STATCMD_CMD(x) ((x) & 0xffff) | ||
| 1390 | #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) | ||
| 1391 | #define PCI_CLASSREV_REV(x) ((x) & 0xff) | ||
| 1392 | #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) | ||
| 1393 | #define PCI_PARAM_HT(x) (((x) & 0xff) << 16) | ||
| 1394 | #define PCI_PARAM_LT(x) (((x) & 0xff) << 8) | ||
| 1395 | #define PCI_PARAM_CLS(x) ((x) & 0xff) | ||
| 1396 | #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ | ||
| 1397 | #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ | ||
| 1398 | |||
| 1538 | #endif | 1399 | #endif |