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-rw-r--r--arch/mips/au1000/common/power.c157
1 files changed, 74 insertions, 83 deletions
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c
index a8cd2c1b9e1..2166b9e1e80 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/au1000/common/power.c
@@ -1,10 +1,9 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Au1000 Power Management routines. 3 * Au1xx0 Power Management routines.
4 * 4 *
5 * Copyright 2001 MontaVista Software Inc. 5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 * ppopov@mvista.com or source@mvista.com
8 * 7 *
9 * Some of the routines are right out of init/main.c, whose 8 * Some of the routines are right out of init/main.c, whose
10 * copyrights apply here. 9 * copyrights apply here.
@@ -43,10 +42,10 @@
43#ifdef CONFIG_PM 42#ifdef CONFIG_PM
44 43
45#define DEBUG 1 44#define DEBUG 1
46#ifdef DEBUG 45#ifdef DEBUG
47# define DPRINTK(fmt, args...) printk("%s: " fmt, __func__, ## args) 46#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
48#else 47#else
49# define DPRINTK(fmt, args...) 48#define DPRINTK(fmt, args...)
50#endif 49#endif
51 50
52static void au1000_calibrate_delay(void); 51static void au1000_calibrate_delay(void);
@@ -57,7 +56,8 @@ extern void local_enable_irq(unsigned int irq_nr);
57 56
58static DEFINE_SPINLOCK(pm_lock); 57static DEFINE_SPINLOCK(pm_lock);
59 58
60/* We need to save/restore a bunch of core registers that are 59/*
60 * We need to save/restore a bunch of core registers that are
61 * either volatile or reset to some state across a processor sleep. 61 * either volatile or reset to some state across a processor sleep.
62 * If reading a register doesn't provide a proper result for a 62 * If reading a register doesn't provide a proper result for a
63 * later restore, we have to provide a function for loading that 63 * later restore, we have to provide a function for loading that
@@ -78,24 +78,25 @@ static unsigned int sleep_usbhost_enable;
78static unsigned int sleep_usbdev_enable; 78static unsigned int sleep_usbdev_enable;
79static unsigned int sleep_static_memctlr[4][3]; 79static unsigned int sleep_static_memctlr[4][3];
80 80
81/* Define this to cause the value you write to /proc/sys/pm/sleep to 81/*
82 * Define this to cause the value you write to /proc/sys/pm/sleep to
82 * set the TOY timer for the amount of time you want to sleep. 83 * set the TOY timer for the amount of time you want to sleep.
83 * This is done mainly for testing, but may be useful in other cases. 84 * This is done mainly for testing, but may be useful in other cases.
84 * The value is number of 32KHz ticks to sleep. 85 * The value is number of 32KHz ticks to sleep.
85 */ 86 */
86#define SLEEP_TEST_TIMEOUT 1 87#define SLEEP_TEST_TIMEOUT 1
87#ifdef SLEEP_TEST_TIMEOUT 88#ifdef SLEEP_TEST_TIMEOUT
88static int sleep_ticks; 89static int sleep_ticks;
89void wakeup_counter0_set(int ticks); 90void wakeup_counter0_set(int ticks);
90#endif 91#endif
91 92
92static void 93static void save_core_regs(void)
93save_core_regs(void)
94{ 94{
95 extern void save_au1xxx_intctl(void); 95 extern void save_au1xxx_intctl(void);
96 extern void pm_eth0_shutdown(void); 96 extern void pm_eth0_shutdown(void);
97 97
98 /* Do the serial ports.....these really should be a pm_* 98 /*
99 * Do the serial ports.....these really should be a pm_*
99 * registered function by the driver......but of course the 100 * registered function by the driver......but of course the
100 * standard serial driver doesn't understand our Au1xxx 101 * standard serial driver doesn't understand our Au1xxx
101 * unique registers. 102 * unique registers.
@@ -106,27 +107,24 @@ save_core_regs(void)
106 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); 107 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
107 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); 108 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
108 109
109 /* Shutdown USB host/device. 110 /* Shutdown USB host/device. */
110 */
111 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); 111 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
112 112
113 /* There appears to be some undocumented reset register.... 113 /* There appears to be some undocumented reset register.... */
114 */
115 au_writel(0, 0xb0100004); au_sync(); 114 au_writel(0, 0xb0100004); au_sync();
116 au_writel(0, USB_HOST_CONFIG); au_sync(); 115 au_writel(0, USB_HOST_CONFIG); au_sync();
117 116
118 sleep_usbdev_enable = au_readl(USBD_ENABLE); 117 sleep_usbdev_enable = au_readl(USBD_ENABLE);
119 au_writel(0, USBD_ENABLE); au_sync(); 118 au_writel(0, USBD_ENABLE); au_sync();
120 119
121 /* Save interrupt controller state. 120 /* Save interrupt controller state. */
122 */
123 save_au1xxx_intctl(); 121 save_au1xxx_intctl();
124 122
125 /* Clocks and PLLs. 123 /* Clocks and PLLs. */
126 */
127 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); 124 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
128 125
129 /* We don't really need to do this one, but unless we 126 /*
127 * We don't really need to do this one, but unless we
130 * write it again it won't have a valid value if we 128 * write it again it won't have a valid value if we
131 * happen to read it. 129 * happen to read it.
132 */ 130 */
@@ -134,8 +132,7 @@ save_core_regs(void)
134 132
135 sleep_pin_function = au_readl(SYS_PINFUNC); 133 sleep_pin_function = au_readl(SYS_PINFUNC);
136 134
137 /* Save the static memory controller configuration. 135 /* Save the static memory controller configuration. */
138 */
139 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 136 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
140 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); 137 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
141 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); 138 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
@@ -150,8 +147,7 @@ save_core_regs(void)
150 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 147 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
151} 148}
152 149
153static void 150static void restore_core_regs(void)
154restore_core_regs(void)
155{ 151{
156 extern void restore_au1xxx_intctl(void); 152 extern void restore_au1xxx_intctl(void);
157 extern void wakeup_counter0_adjust(void); 153 extern void wakeup_counter0_adjust(void);
@@ -160,8 +156,7 @@ restore_core_regs(void)
160 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); 156 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
161 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); 157 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
162 158
163 /* Restore the static memory controller configuration. 159 /* Restore the static memory controller configuration. */
164 */
165 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 160 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
166 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); 161 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
167 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); 162 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
@@ -175,7 +170,8 @@ restore_core_regs(void)
175 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); 170 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
176 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); 171 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
177 172
178 /* Enable the UART if it was enabled before sleep. 173 /*
174 * Enable the UART if it was enabled before sleep.
179 * I guess I should define module control bits........ 175 * I guess I should define module control bits........
180 */ 176 */
181 if (sleep_uart0_enable & 0x02) { 177 if (sleep_uart0_enable & 0x02) {
@@ -202,7 +198,7 @@ void wakeup_from_suspend(void)
202int au_sleep(void) 198int au_sleep(void)
203{ 199{
204 unsigned long wakeup, flags; 200 unsigned long wakeup, flags;
205 extern void save_and_sleep(void); 201 extern void save_and_sleep(void);
206 202
207 spin_lock_irqsave(&pm_lock, flags); 203 spin_lock_irqsave(&pm_lock, flags);
208 204
@@ -210,23 +206,22 @@ int au_sleep(void)
210 206
211 flush_cache_all(); 207 flush_cache_all();
212 208
213 /** The code below is all system dependent and we should probably 209 /**
210 ** The code below is all system dependent and we should probably
214 ** have a function call out of here to set this up. You need 211 ** have a function call out of here to set this up. You need
215 ** to configure the GPIO or timer interrupts that will bring 212 ** to configure the GPIO or timer interrupts that will bring
216 ** you out of sleep. 213 ** you out of sleep.
217 ** For testing, the TOY counter wakeup is useful. 214 ** For testing, the TOY counter wakeup is useful.
218 **/ 215 **/
219
220#if 0 216#if 0
221 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); 217 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
222 218
223 /* gpio 6 can cause a wake up event */ 219 /* GPIO 6 can cause a wake up event */
224 wakeup = au_readl(SYS_WAKEMSK); 220 wakeup = au_readl(SYS_WAKEMSK);
225 wakeup &= ~(1 << 8); /* turn off match20 wakeup */ 221 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
226 wakeup |= 1 << 6; /* turn on gpio 6 wakeup */ 222 wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */
227#else 223#else
228 /* For testing, allow match20 to wake us up. 224 /* For testing, allow match20 to wake us up. */
229 */
230#ifdef SLEEP_TEST_TIMEOUT 225#ifdef SLEEP_TEST_TIMEOUT
231 wakeup_counter0_set(sleep_ticks); 226 wakeup_counter0_set(sleep_ticks);
232#endif 227#endif
@@ -240,7 +235,8 @@ int au_sleep(void)
240 235
241 save_and_sleep(); 236 save_and_sleep();
242 237
243 /* after a wakeup, the cpu vectors back to 0x1fc00000 so 238 /*
239 * After a wakeup, the cpu vectors back to 0x1fc00000, so
244 * it's up to the boot code to get us back here. 240 * it's up to the boot code to get us back here.
245 */ 241 */
246 restore_core_regs(); 242 restore_core_regs();
@@ -248,24 +244,22 @@ int au_sleep(void)
248 return 0; 244 return 0;
249} 245}
250 246
251static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, 247static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
252 void __user *buffer, size_t * len, loff_t *ppos) 248 void __user *buffer, size_t *len, loff_t *ppos)
253{ 249{
254#ifdef SLEEP_TEST_TIMEOUT 250#ifdef SLEEP_TEST_TIMEOUT
255#define TMPBUFLEN2 16 251#define TMPBUFLEN2 16
256 char buf[TMPBUFLEN2], *p; 252 char buf[TMPBUFLEN2], *p;
257#endif 253#endif
258 254
259 if (!write) { 255 if (!write)
260 *len = 0; 256 *len = 0;
261 } else { 257 else {
262#ifdef SLEEP_TEST_TIMEOUT 258#ifdef SLEEP_TEST_TIMEOUT
263 if (*len > TMPBUFLEN2 - 1) { 259 if (*len > TMPBUFLEN2 - 1)
264 return -EFAULT; 260 return -EFAULT;
265 } 261 if (copy_from_user(buf, buffer, *len))
266 if (copy_from_user(buf, buffer, *len)) {
267 return -EFAULT; 262 return -EFAULT;
268 }
269 buf[*len] = 0; 263 buf[*len] = 0;
270 p = buf; 264 p = buf;
271 sleep_ticks = simple_strtoul(p, &p, 0); 265 sleep_ticks = simple_strtoul(p, &p, 0);
@@ -276,8 +270,8 @@ static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
276 return 0; 270 return 0;
277} 271}
278 272
279static int pm_do_freq(ctl_table * ctl, int write, struct file *file, 273static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
280 void __user *buffer, size_t * len, loff_t *ppos) 274 void __user *buffer, size_t *len, loff_t *ppos)
281{ 275{
282 int retval = 0, i; 276 int retval = 0, i;
283 unsigned long val, pll; 277 unsigned long val, pll;
@@ -285,14 +279,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
285#define MAX_CPU_FREQ 396 279#define MAX_CPU_FREQ 396
286 char buf[TMPBUFLEN], *p; 280 char buf[TMPBUFLEN], *p;
287 unsigned long flags, intc0_mask, intc1_mask; 281 unsigned long flags, intc0_mask, intc1_mask;
288 unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk, 282 unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
289 old_refresh;
290 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; 283 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
284 unsigned long baud_rate;
291 285
292 spin_lock_irqsave(&pm_lock, flags); 286 spin_lock_irqsave(&pm_lock, flags);
293 if (!write) { 287 if (!write)
294 *len = 0; 288 *len = 0;
295 } else { 289 else {
296 /* Parse the new frequency */ 290 /* Parse the new frequency */
297 if (*len > TMPBUFLEN - 1) { 291 if (*len > TMPBUFLEN - 1) {
298 spin_unlock_irqrestore(&pm_lock, flags); 292 spin_unlock_irqrestore(&pm_lock, flags);
@@ -312,7 +306,7 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
312 306
313 pll = val / 12; 307 pll = val / 12;
314 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ 308 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
315 /* revisit this for higher speed cpus */ 309 /* Revisit this for higher speed CPUs */
316 spin_unlock_irqrestore(&pm_lock, flags); 310 spin_unlock_irqrestore(&pm_lock, flags);
317 return -EFAULT; 311 return -EFAULT;
318 } 312 }
@@ -321,30 +315,28 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
321 old_cpu_freq = get_au1x00_speed(); 315 old_cpu_freq = get_au1x00_speed();
322 316
323 new_cpu_freq = pll * 12 * 1000000; 317 new_cpu_freq = pll * 12 * 1000000;
324 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); 318 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
319 & 0x03) + 2) * 16));
325 set_au1x00_speed(new_cpu_freq); 320 set_au1x00_speed(new_cpu_freq);
326 set_au1x00_uart_baud_base(new_baud_base); 321 set_au1x00_uart_baud_base(new_baud_base);
327 322
328 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; 323 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
329 new_refresh = 324 new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
330 ((old_refresh * new_cpu_freq) / 325 (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
331 old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
332 326
333 au_writel(pll, SYS_CPUPLL); 327 au_writel(pll, SYS_CPUPLL);
334 au_sync_delay(1); 328 au_sync_delay(1);
335 au_writel(new_refresh, MEM_SDREFCFG); 329 au_writel(new_refresh, MEM_SDREFCFG);
336 au_sync_delay(1); 330 au_sync_delay(1);
337 331
338 for (i = 0; i < 4; i++) { 332 for (i = 0; i < 4; i++)
339 if (au_readl 333 if (au_readl(UART_BASE + UART_MOD_CNTRL +
340 (UART_BASE + UART_MOD_CNTRL + 334 i * 0x00100000) == 3) {
341 i * 0x00100000) == 3) { 335 old_clk = au_readl(UART_BASE + UART_CLK +
342 old_clk = 336 i * 0x00100000);
343 au_readl(UART_BASE + UART_CLK +
344 i * 0x00100000);
345 // baud_rate = baud_base/clk
346 baud_rate = old_baud_base / old_clk; 337 baud_rate = old_baud_base / old_clk;
347 /* we won't get an exact baud rate and the error 338 /*
339 * We won't get an exact baud rate and the error
348 * could be significant enough that our new 340 * could be significant enough that our new
349 * calculation will result in a clock that will 341 * calculation will result in a clock that will
350 * give us a baud rate that's too far off from 342 * give us a baud rate that's too far off from
@@ -359,18 +351,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
359 else if (baud_rate > 17000) 351 else if (baud_rate > 17000)
360 baud_rate = 19200; 352 baud_rate = 19200;
361 else 353 else
362 (baud_rate = 9600); 354 baud_rate = 9600;
363 // new_clk = new_baud_base/baud_rate
364 new_clk = new_baud_base / baud_rate; 355 new_clk = new_baud_base / baud_rate;
365 au_writel(new_clk, 356 au_writel(new_clk, UART_BASE + UART_CLK +
366 UART_BASE + UART_CLK + 357 i * 0x00100000);
367 i * 0x00100000);
368 au_sync_delay(10); 358 au_sync_delay(10);
369 } 359 }
370 }
371 } 360 }
372 361
373
374 /* 362 /*
375 * We don't want _any_ interrupts other than match20. Otherwise our 363 * We don't want _any_ interrupts other than match20. Otherwise our
376 * au1000_calibrate_delay() calculation will be off, potentially a lot. 364 * au1000_calibrate_delay() calculation will be off, potentially a lot.
@@ -428,14 +416,15 @@ static int __init pm_init(void)
428 416
429__initcall(pm_init); 417__initcall(pm_init);
430 418
431
432/* 419/*
433 * This is right out of init/main.c 420 * This is right out of init/main.c
434 */ 421 */
435 422
436/* This is the number of bits of precision for the loops_per_jiffy. Each 423/*
437 bit takes on average 1.5/HZ seconds. This (like the original) is a little 424 * This is the number of bits of precision for the loops_per_jiffy.
438 better than 1% */ 425 * Each bit takes on average 1.5/HZ seconds. This (like the original)
426 * is a little better than 1%.
427 */
439#define LPS_PREC 8 428#define LPS_PREC 8
440 429
441static void au1000_calibrate_delay(void) 430static void au1000_calibrate_delay(void)
@@ -443,14 +432,14 @@ static void au1000_calibrate_delay(void)
443 unsigned long ticks, loopbit; 432 unsigned long ticks, loopbit;
444 int lps_precision = LPS_PREC; 433 int lps_precision = LPS_PREC;
445 434
446 loops_per_jiffy = (1 << 12); 435 loops_per_jiffy = 1 << 12;
447 436
448 while (loops_per_jiffy <<= 1) { 437 while (loops_per_jiffy <<= 1) {
449 /* wait for "start of" clock tick */ 438 /* Wait for "start of" clock tick */
450 ticks = jiffies; 439 ticks = jiffies;
451 while (ticks == jiffies) 440 while (ticks == jiffies)
452 /* nothing */ ; 441 /* nothing */ ;
453 /* Go .. */ 442 /* Go ... */
454 ticks = jiffies; 443 ticks = jiffies;
455 __delay(loops_per_jiffy); 444 __delay(loops_per_jiffy);
456 ticks = jiffies - ticks; 445 ticks = jiffies - ticks;
@@ -458,8 +447,10 @@ static void au1000_calibrate_delay(void)
458 break; 447 break;
459 } 448 }
460 449
461/* Do a binary approximation to get loops_per_jiffy set to equal one clock 450 /*
462 (up to lps_precision bits) */ 451 * Do a binary approximation to get loops_per_jiffy set to be equal
452 * one clock (up to lps_precision bits)
453 */
463 loops_per_jiffy >>= 1; 454 loops_per_jiffy >>= 1;
464 loopbit = loops_per_jiffy; 455 loopbit = loops_per_jiffy;
465 while (lps_precision-- && (loopbit >>= 1)) { 456 while (lps_precision-- && (loopbit >>= 1)) {
@@ -472,4 +463,4 @@ static void au1000_calibrate_delay(void)
472 loops_per_jiffy &= ~loopbit; 463 loops_per_jiffy &= ~loopbit;
473 } 464 }
474} 465}
475#endif /* CONFIG_PM */ 466#endif /* CONFIG_PM */