aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/alchemy
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/dma.c46
-rw-r--r--arch/mips/alchemy/common/platform.c8
2 files changed, 29 insertions, 25 deletions
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index d5278877891..347980e79a8 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -58,6 +58,9 @@
58 * returned from request_dma. 58 * returned from request_dma.
59 */ 59 */
60 60
61/* DMA Channel register block spacing */
62#define DMA_CHANNEL_LEN 0x00000100
63
61DEFINE_SPINLOCK(au1000_dma_spin_lock); 64DEFINE_SPINLOCK(au1000_dma_spin_lock);
62 65
63struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { 66struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
@@ -77,22 +80,23 @@ static const struct dma_dev {
77 unsigned int fifo_addr; 80 unsigned int fifo_addr;
78 unsigned int dma_mode; 81 unsigned int dma_mode;
79} dma_dev_table[DMA_NUM_DEV] = { 82} dma_dev_table[DMA_NUM_DEV] = {
80 {UART0_ADDR + UART_TX, 0}, 83 { AU1000_UART0_PHYS_ADDR + 0x04, DMA_DW8 }, /* UART0_TX */
81 {UART0_ADDR + UART_RX, 0}, 84 { AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR }, /* UART0_RX */
82 {0, 0}, 85 { 0, 0 }, /* DMA_REQ0 */
83 {0, 0}, 86 { 0, 0 }, /* DMA_REQ1 */
84 {AC97C_DATA, DMA_DW16 }, /* coherent */ 87 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 }, /* AC97 TX c */
85 {AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */ 88 { AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
86 {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, 89 { AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
87 {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, 90 { AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
88 {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, 91 { AU1000_USBD_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
89 {USBD_EP0WR, DMA_DW8 | DMA_NC}, 92 { AU1000_USBD_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
90 {USBD_EP2WR, DMA_DW8 | DMA_NC}, 93 { AU1000_USBD_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
91 {USBD_EP3WR, DMA_DW8 | DMA_NC}, 94 { AU1000_USBD_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
92 {USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC}, 95 { AU1000_USBD_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
93 {USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC}, 96 { AU1000_USBD_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
94 {I2S_DATA, DMA_DW32 | DMA_NC}, 97 /* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
95 {I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC} 98 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
99 { AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
96}; 100};
97 101
98int au1000_dma_read_proc(char *buf, char **start, off_t fpos, 102int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
@@ -123,10 +127,10 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
123 127
124/* Device FIFO addresses and default DMA modes - 2nd bank */ 128/* Device FIFO addresses and default DMA modes - 2nd bank */
125static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = { 129static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
126 { SD0_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ 130 { AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
127 { SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }, /* coherent */ 131 { AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */
128 { SD1_XMIT_FIFO, DMA_DS | DMA_DW8 }, /* coherent */ 132 { AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
129 { SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 } /* coherent */ 133 { AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */
130}; 134};
131 135
132void dump_au1000_dma_channel(unsigned int dmanr) 136void dump_au1000_dma_channel(unsigned int dmanr)
@@ -202,7 +206,7 @@ int request_au1000_dma(int dev_id, const char *dev_str,
202 } 206 }
203 207
204 /* fill it in */ 208 /* fill it in */
205 chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN; 209 chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN;
206 chan->dev_id = dev_id; 210 chan->dev_id = dev_id;
207 chan->dev_str = dev_str; 211 chan->dev_str = dev_str;
208 chan->fifo_addr = dev->fifo_addr; 212 chan->fifo_addr = dev->fifo_addr;
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 541fff24abe..3b2c18b1434 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -283,8 +283,8 @@ extern struct au1xmmc_platform_data au1xmmc_platdata[2];
283 283
284static struct resource au1200_mmc0_resources[] = { 284static struct resource au1200_mmc0_resources[] = {
285 [0] = { 285 [0] = {
286 .start = SD0_PHYS_ADDR, 286 .start = AU1100_SD0_PHYS_ADDR,
287 .end = SD0_PHYS_ADDR + 0x7ffff, 287 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
288 .flags = IORESOURCE_MEM, 288 .flags = IORESOURCE_MEM,
289 }, 289 },
290 [1] = { 290 [1] = {
@@ -319,8 +319,8 @@ static struct platform_device au1200_mmc0_device = {
319#ifndef CONFIG_MIPS_DB1200 319#ifndef CONFIG_MIPS_DB1200
320static struct resource au1200_mmc1_resources[] = { 320static struct resource au1200_mmc1_resources[] = {
321 [0] = { 321 [0] = {
322 .start = SD1_PHYS_ADDR, 322 .start = AU1100_SD1_PHYS_ADDR,
323 .end = SD1_PHYS_ADDR + 0x7ffff, 323 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
324 .flags = IORESOURCE_MEM, 324 .flags = IORESOURCE_MEM,
325 }, 325 },
326 [1] = { 326 [1] = {