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-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile8
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c148
-rw-r--r--arch/mips/alchemy/devboards/pb1500/platform.c49
3 files changed, 205 insertions, 0 deletions
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
new file mode 100644
index 00000000000..e83b151b5b6
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for the Alchemy Semiconductor Pb1500 board.
6#
7
8obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
new file mode 100644
index 00000000000..3b4fa320696
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -0,0 +1,148 @@
1/*
2 * Copyright 2000, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30
31#include <asm/mach-au1x00/au1000.h>
32#include <asm/mach-db1x00/bcsr.h>
33
34#include <prom.h>
35
36
37char irq_tab_alchemy[][5] __initdata = {
38 [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT370 */
39 [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
40};
41
42
43const char *get_system_type(void)
44{
45 return "Alchemy Pb1500";
46}
47
48void __init board_setup(void)
49{
50 u32 pin_func;
51 u32 sys_freqctrl, sys_clksrc;
52
53 bcsr_init(DB1000_BCSR_PHYS_ADDR,
54 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
55
56 sys_clksrc = sys_freqctrl = pin_func = 0;
57 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
58 au_writel(8, SYS_AUXPLL);
59 alchemy_gpio1_input_enable();
60 udelay(100);
61
62 /* GPIO201 is input for PCMCIA card detect */
63 /* GPIO203 is input for PCMCIA interrupt request */
64 alchemy_gpio_direction_input(201);
65 alchemy_gpio_direction_input(203);
66
67#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
68
69 /* Zero and disable FREQ2 */
70 sys_freqctrl = au_readl(SYS_FREQCTRL0);
71 sys_freqctrl &= ~0xFFF00000;
72 au_writel(sys_freqctrl, SYS_FREQCTRL0);
73
74 /* zero and disable USBH/USBD clocks */
75 sys_clksrc = au_readl(SYS_CLKSRC);
76 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
77 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
78 au_writel(sys_clksrc, SYS_CLKSRC);
79
80 sys_freqctrl = au_readl(SYS_FREQCTRL0);
81 sys_freqctrl &= ~0xFFF00000;
82
83 sys_clksrc = au_readl(SYS_CLKSRC);
84 sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
85 SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
86
87 /* FREQ2 = aux/2 = 48 MHz */
88 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
89 au_writel(sys_freqctrl, SYS_FREQCTRL0);
90
91 /*
92 * Route 48MHz FREQ2 into USB Host and/or Device
93 */
94 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
95 au_writel(sys_clksrc, SYS_CLKSRC);
96
97 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
98 /* 2nd USB port is USB host */
99 pin_func |= SYS_PF_USB;
100 au_writel(pin_func, SYS_PINFUNC);
101#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
102
103#ifdef CONFIG_PCI
104 /* Setup PCI bus controller */
105 au_writel(0, Au1500_PCI_CMEM);
106 au_writel(0x00003fff, Au1500_CFG_BASE);
107#if defined(__MIPSEB__)
108 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
109#else
110 au_writel(0xf, Au1500_PCI_CFG);
111#endif
112 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
113 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
114 au_writel(0x02a00356, Au1500_PCI_STATCMD);
115 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
116 au_writel(0x00000008, Au1500_PCI_MBAR);
117 au_sync();
118#endif
119
120 /* Enable sys bus clock divider when IDLE state or no bus activity. */
121 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
122
123 /* Enable the RTC if not already enabled */
124 if (!(au_readl(0xac000028) & 0x20)) {
125 printk(KERN_INFO "enabling clock ...\n");
126 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
127 }
128 /* Put the clock in BCD mode */
129 if (au_readl(0xac00002c) & 0x4) { /* reg B */
130 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
131 au_sync();
132 }
133}
134
135static int __init pb1500_init_irq(void)
136{
137 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
138 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
139 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
140 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
141 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
142 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
143 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
144 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
145
146 return 0;
147}
148arch_initcall(pb1500_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
new file mode 100644
index 00000000000..d443bc7aa76
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -0,0 +1,49 @@
1/*
2 * Pb1500 board platform device registration
3 *
4 * Copyright (C) 2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-db1x00/bcsr.h>
24
25#include "../platform.h"
26
27static int __init pb1500_dev_init(void)
28{
29 int swapped;
30
31 /* PCMCIA. single socket, identical to Pb1500 */
32 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
33 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
34 PCMCIA_MEM_PHYS_ADDR,
35 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
36 PCMCIA_IO_PHYS_ADDR,
37 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
38 AU1500_GPIO11_INT, /* card */
39 AU1500_GPIO9_INT, /* insert */
40 /*AU1500_GPIO10_INT*/0, /* stschg */
41 0, /* eject */
42 0); /* id */
43
44 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
45 db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
46
47 return 0;
48}
49device_initcall(pb1500_dev_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 17:47:23 -0400