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-rw-r--r--arch/mips/alchemy/devboards/db1200/Makefile1
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c567
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c81
3 files changed, 649 insertions, 0 deletions
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
new file mode 100644
index 00000000000..17840a5e273
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/Makefile
@@ -0,0 +1 @@
obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
new file mode 100644
index 00000000000..fbb55935b99
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -0,0 +1,567 @@
1/*
2 * DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008-2009 Manuel Lauss
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/platform_device.h>
32#include <linux/serial_8250.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/flash.h>
35#include <linux/smc91x.h>
36
37#include <asm/mach-au1x00/au1100_mmc.h>
38#include <asm/mach-au1x00/au1xxx_dbdma.h>
39#include <asm/mach-au1x00/au1550_spi.h>
40#include <asm/mach-db1x00/bcsr.h>
41#include <asm/mach-db1x00/db1200.h>
42
43#include "../platform.h"
44
45static struct mtd_partition db1200_spiflash_parts[] = {
46 {
47 .name = "DB1200 SPI flash",
48 .offset = 0,
49 .size = MTDPART_SIZ_FULL,
50 },
51};
52
53static struct flash_platform_data db1200_spiflash_data = {
54 .name = "s25fl001",
55 .parts = db1200_spiflash_parts,
56 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
57 .type = "m25p10",
58};
59
60static struct spi_board_info db1200_spi_devs[] __initdata = {
61 {
62 /* TI TMP121AIDBVR temp sensor */
63 .modalias = "tmp121",
64 .max_speed_hz = 2000000,
65 .bus_num = 0,
66 .chip_select = 0,
67 .mode = 0,
68 },
69 {
70 /* Spansion S25FL001D0FMA SPI flash */
71 .modalias = "m25p80",
72 .max_speed_hz = 50000000,
73 .bus_num = 0,
74 .chip_select = 1,
75 .mode = 0,
76 .platform_data = &db1200_spiflash_data,
77 },
78};
79
80static struct i2c_board_info db1200_i2c_devs[] __initdata = {
81 {
82 /* AT24C04-10 I2C eeprom */
83 I2C_BOARD_INFO("24c04", 0x52),
84 },
85 {
86 /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
87 I2C_BOARD_INFO("ne1619", 0x2d),
88 },
89 {
90 /* I2S audio codec WM8731 */
91 I2C_BOARD_INFO("wm8731", 0x1b),
92 },
93};
94
95/**********************************************************************/
96
97static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 struct nand_chip *this = mtd->priv;
101 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
102
103 ioaddr &= 0xffffff00;
104
105 if (ctrl & NAND_CLE) {
106 ioaddr += MEM_STNAND_CMD;
107 } else if (ctrl & NAND_ALE) {
108 ioaddr += MEM_STNAND_ADDR;
109 } else {
110 /* assume we want to r/w real data by default */
111 ioaddr += MEM_STNAND_DATA;
112 }
113 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
114 if (cmd != NAND_CMD_NONE) {
115 __raw_writeb(cmd, this->IO_ADDR_W);
116 wmb();
117 }
118}
119
120static int au1200_nand_device_ready(struct mtd_info *mtd)
121{
122 return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
123}
124
125static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
126
127static struct mtd_partition db1200_nand_parts[] = {
128 {
129 .name = "NAND FS 0",
130 .offset = 0,
131 .size = 8 * 1024 * 1024,
132 },
133 {
134 .name = "NAND FS 1",
135 .offset = MTDPART_OFS_APPEND,
136 .size = MTDPART_SIZ_FULL
137 },
138};
139
140struct platform_nand_data db1200_nand_platdata = {
141 .chip = {
142 .nr_chips = 1,
143 .chip_offset = 0,
144 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
145 .partitions = db1200_nand_parts,
146 .chip_delay = 20,
147 .part_probe_types = db1200_part_probes,
148 },
149 .ctrl = {
150 .dev_ready = au1200_nand_device_ready,
151 .cmd_ctrl = au1200_nand_cmd_ctrl,
152 },
153};
154
155static struct resource db1200_nand_res[] = {
156 [0] = {
157 .start = DB1200_NAND_PHYS_ADDR,
158 .end = DB1200_NAND_PHYS_ADDR + 0xff,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device db1200_nand_dev = {
164 .name = "gen_nand",
165 .num_resources = ARRAY_SIZE(db1200_nand_res),
166 .resource = db1200_nand_res,
167 .id = -1,
168 .dev = {
169 .platform_data = &db1200_nand_platdata,
170 }
171};
172
173/**********************************************************************/
174
175static struct smc91x_platdata db1200_eth_data = {
176 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
177 .leda = RPC_LED_100_10,
178 .ledb = RPC_LED_TX_RX,
179};
180
181static struct resource db1200_eth_res[] = {
182 [0] = {
183 .start = DB1200_ETH_PHYS_ADDR,
184 .end = DB1200_ETH_PHYS_ADDR + 0xf,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = DB1200_ETH_INT,
189 .end = DB1200_ETH_INT,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device db1200_eth_dev = {
195 .dev = {
196 .platform_data = &db1200_eth_data,
197 },
198 .name = "smc91x",
199 .id = -1,
200 .num_resources = ARRAY_SIZE(db1200_eth_res),
201 .resource = db1200_eth_res,
202};
203
204/**********************************************************************/
205
206static struct resource db1200_ide_res[] = {
207 [0] = {
208 .start = DB1200_IDE_PHYS_ADDR,
209 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = DB1200_IDE_INT,
214 .end = DB1200_IDE_INT,
215 .flags = IORESOURCE_IRQ,
216 }
217};
218
219static u64 ide_dmamask = DMA_BIT_MASK(32);
220
221static struct platform_device db1200_ide_dev = {
222 .name = "au1200-ide",
223 .id = 0,
224 .dev = {
225 .dma_mask = &ide_dmamask,
226 .coherent_dma_mask = DMA_BIT_MASK(32),
227 },
228 .num_resources = ARRAY_SIZE(db1200_ide_res),
229 .resource = db1200_ide_res,
230};
231
232/**********************************************************************/
233
234static struct platform_device db1200_rtc_dev = {
235 .name = "rtc-au1xxx",
236 .id = -1,
237};
238
239/**********************************************************************/
240
241/* SD carddetects: they're supposed to be edge-triggered, but ack
242 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one
243 * is disabled and its counterpart enabled. The 500ms timeout is
244 * because the carddetect isn't debounced in hardware.
245 */
246static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
247{
248 void(*mmc_cd)(struct mmc_host *, unsigned long);
249
250 if (irq == DB1200_SD0_INSERT_INT) {
251 disable_irq_nosync(DB1200_SD0_INSERT_INT);
252 enable_irq(DB1200_SD0_EJECT_INT);
253 } else {
254 disable_irq_nosync(DB1200_SD0_EJECT_INT);
255 enable_irq(DB1200_SD0_INSERT_INT);
256 }
257
258 /* link against CONFIG_MMC=m */
259 mmc_cd = symbol_get(mmc_detect_change);
260 if (mmc_cd) {
261 mmc_cd(ptr, msecs_to_jiffies(500));
262 symbol_put(mmc_detect_change);
263 }
264
265 return IRQ_HANDLED;
266}
267
268static int db1200_mmc_cd_setup(void *mmc_host, int en)
269{
270 int ret;
271
272 if (en) {
273 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
274 IRQF_DISABLED, "sd_insert", mmc_host);
275 if (ret)
276 goto out;
277
278 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
279 IRQF_DISABLED, "sd_eject", mmc_host);
280 if (ret) {
281 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
282 goto out;
283 }
284
285 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
286 enable_irq(DB1200_SD0_EJECT_INT);
287 else
288 enable_irq(DB1200_SD0_INSERT_INT);
289
290 } else {
291 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
292 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
293 }
294 ret = 0;
295out:
296 return ret;
297}
298
299static void db1200_mmc_set_power(void *mmc_host, int state)
300{
301 if (state) {
302 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
303 msleep(400); /* stabilization time */
304 } else
305 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
306}
307
308static int db1200_mmc_card_readonly(void *mmc_host)
309{
310 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
311}
312
313static int db1200_mmc_card_inserted(void *mmc_host)
314{
315 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
316}
317
318static void db1200_mmcled_set(struct led_classdev *led,
319 enum led_brightness brightness)
320{
321 if (brightness != LED_OFF)
322 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
323 else
324 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
325}
326
327static struct led_classdev db1200_mmc_led = {
328 .brightness_set = db1200_mmcled_set,
329};
330
331/* needed by arch/mips/alchemy/common/platform.c */
332struct au1xmmc_platform_data au1xmmc_platdata[] = {
333 [0] = {
334 .cd_setup = db1200_mmc_cd_setup,
335 .set_power = db1200_mmc_set_power,
336 .card_inserted = db1200_mmc_card_inserted,
337 .card_readonly = db1200_mmc_card_readonly,
338 .led = &db1200_mmc_led,
339 },
340};
341
342/**********************************************************************/
343
344static struct resource au1200_psc0_res[] = {
345 [0] = {
346 .start = PSC0_PHYS_ADDR,
347 .end = PSC0_PHYS_ADDR + 0x000fffff,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AU1200_PSC0_INT,
352 .end = AU1200_PSC0_INT,
353 .flags = IORESOURCE_IRQ,
354 },
355 [2] = {
356 .start = DSCR_CMD0_PSC0_TX,
357 .end = DSCR_CMD0_PSC0_TX,
358 .flags = IORESOURCE_DMA,
359 },
360 [3] = {
361 .start = DSCR_CMD0_PSC0_RX,
362 .end = DSCR_CMD0_PSC0_RX,
363 .flags = IORESOURCE_DMA,
364 },
365};
366
367static struct platform_device db1200_i2c_dev = {
368 .name = "au1xpsc_smbus",
369 .id = 0, /* bus number */
370 .num_resources = ARRAY_SIZE(au1200_psc0_res),
371 .resource = au1200_psc0_res,
372};
373
374static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
375{
376 if (cs)
377 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
378 else
379 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
380}
381
382static struct au1550_spi_info db1200_spi_platdata = {
383 .mainclk_hz = 50000000, /* PSC0 clock */
384 .num_chipselect = 2,
385 .activate_cs = db1200_spi_cs_en,
386};
387
388static u64 spi_dmamask = DMA_BIT_MASK(32);
389
390static struct platform_device db1200_spi_dev = {
391 .dev = {
392 .dma_mask = &spi_dmamask,
393 .coherent_dma_mask = DMA_BIT_MASK(32),
394 .platform_data = &db1200_spi_platdata,
395 },
396 .name = "au1550-spi",
397 .id = 0, /* bus number */
398 .num_resources = ARRAY_SIZE(au1200_psc0_res),
399 .resource = au1200_psc0_res,
400};
401
402static struct resource au1200_psc1_res[] = {
403 [0] = {
404 .start = PSC1_PHYS_ADDR,
405 .end = PSC1_PHYS_ADDR + 0x000fffff,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = AU1200_PSC1_INT,
410 .end = AU1200_PSC1_INT,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 .start = DSCR_CMD0_PSC1_TX,
415 .end = DSCR_CMD0_PSC1_TX,
416 .flags = IORESOURCE_DMA,
417 },
418 [3] = {
419 .start = DSCR_CMD0_PSC1_RX,
420 .end = DSCR_CMD0_PSC1_RX,
421 .flags = IORESOURCE_DMA,
422 },
423};
424
425static struct platform_device db1200_audio_dev = {
426 /* name assigned later based on switch setting */
427 .id = 1, /* PSC ID */
428 .num_resources = ARRAY_SIZE(au1200_psc1_res),
429 .resource = au1200_psc1_res,
430};
431
432static struct platform_device db1200_stac_dev = {
433 .name = "ac97-codec",
434 .id = 1, /* on PSC1 */
435};
436
437static struct platform_device *db1200_devs[] __initdata = {
438 NULL, /* PSC0, selected by S6.8 */
439 &db1200_ide_dev,
440 &db1200_eth_dev,
441 &db1200_rtc_dev,
442 &db1200_nand_dev,
443 &db1200_audio_dev,
444 &db1200_stac_dev,
445};
446
447static int __init db1200_dev_init(void)
448{
449 unsigned long pfc;
450 unsigned short sw;
451 int swapped;
452
453 i2c_register_board_info(0, db1200_i2c_devs,
454 ARRAY_SIZE(db1200_i2c_devs));
455 spi_register_board_info(db1200_spi_devs,
456 ARRAY_SIZE(db1200_i2c_devs));
457
458 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI)
459 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
460 */
461
462 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however
463 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
464 * allow to free it without crippling the SPI interface).
465 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
466 * it as an input pin which is pulled high on the boards).
467 */
468 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
469
470 /* switch off OTG VBUS supply */
471 gpio_request(215, "otg-vbus");
472 gpio_direction_output(215, 1);
473
474 printk(KERN_INFO "DB1200 device configuration:\n");
475
476 sw = bcsr_read(BCSR_SWITCHES);
477 if (sw & BCSR_SWITCHES_DIP_8) {
478 db1200_devs[0] = &db1200_i2c_dev;
479 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
480
481 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */
482
483 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
484 printk(KERN_INFO " OTG port VBUS supply available!\n");
485 } else {
486 db1200_devs[0] = &db1200_spi_dev;
487 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
488
489 pfc |= (1 << 17); /* PSC0 owns GPIO215 */
490
491 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
492 printk(KERN_INFO " OTG port VBUS supply disabled\n");
493 }
494 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
495 wmb();
496
497 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
498 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
499 */
500 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
501 if (sw == BCSR_SWITCHES_DIP_8) {
502 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
503 db1200_audio_dev.name = "au1xpsc_i2s";
504 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
505 } else {
506 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
507 db1200_audio_dev.name = "au1xpsc_ac97";
508 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
509 }
510
511 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
512 __raw_writel(PSC_SEL_CLK_SERCLK,
513 (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
514 wmb();
515
516 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
517 PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
518 PCMCIA_MEM_PHYS_ADDR,
519 PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
520 PCMCIA_IO_PHYS_ADDR,
521 PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
522 DB1200_PC0_INT,
523 DB1200_PC0_INSERT_INT,
524 /*DB1200_PC0_STSCHG_INT*/0,
525 DB1200_PC0_EJECT_INT,
526 0);
527
528 db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
529 PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
530 PCMCIA_MEM_PHYS_ADDR + 0x004000000,
531 PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
532 PCMCIA_IO_PHYS_ADDR + 0x004000000,
533 PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
534 DB1200_PC1_INT,
535 DB1200_PC1_INSERT_INT,
536 /*DB1200_PC1_STSCHG_INT*/0,
537 DB1200_PC1_EJECT_INT,
538 1);
539
540 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
541 db1x_register_norflash(64 << 20, 2, swapped);
542
543 return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
544}
545device_initcall(db1200_dev_init);
546
547/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
548int board_au1200fb_panel(void)
549{
550 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
551}
552
553int board_au1200fb_panel_init(void)
554{
555 /* Apply power */
556 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
557 BCSR_BOARD_LCDBL);
558 return 0;
559}
560
561int board_au1200fb_panel_shutdown(void)
562{
563 /* Remove power */
564 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
565 BCSR_BOARD_LCDBL, 0);
566 return 0;
567}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
new file mode 100644
index 00000000000..4a8980027ec
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -0,0 +1,81 @@
1/*
2 * Alchemy/AMD/RMI DB1200 board setup.
3 *
4 * Licensed under the terms outlined in the file COPYING in the root of
5 * this source archive.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <asm/mach-au1x00/au1000.h>
13#include <asm/mach-db1x00/bcsr.h>
14#include <asm/mach-db1x00/db1200.h>
15
16const char *get_system_type(void)
17{
18 return "Alchemy Db1200";
19}
20
21void __init board_setup(void)
22{
23 unsigned long freq0, clksrc, div, pfc;
24 unsigned short whoami;
25
26 bcsr_init(DB1200_BCSR_PHYS_ADDR,
27 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
28
29 whoami = bcsr_read(BCSR_WHOAMI);
30 printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
31 " Board-ID %d Daughtercard ID %d\n",
32 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
33
34 /* SMBus/SPI on PSC0, Audio on PSC1 */
35 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
36 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
37 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
38 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
39 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
40 wmb();
41
42 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
43 * CPU clock; all other clock generators off/unused.
44 */
45 div = (get_au1x00_speed() + 25000000) / 50000000;
46 if (div & 1)
47 div++;
48 div = ((div >> 1) - 1) & 0xff;
49
50 freq0 = div << SYS_FC_FRDIV0_BIT;
51 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
52 wmb();
53 freq0 |= SYS_FC_FE0; /* enable F0 */
54 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
55 wmb();
56
57 /* psc0_intclk comes 1:1 from F0 */
58 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
59 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
60 wmb();
61}
62
63static int __init db1200_arch_init(void)
64{
65 /* GPIO7 is low-level triggered CPLD cascade */
66 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
68
69 /* insert/eject pairs: one of both is always screaming. To avoid
70 * issues they must not be automatically enabled when initially
71 * requested.
72 */
73 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
74 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
75 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
76 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
77 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
78 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
79 return 0;
80}
81arch_initcall(db1200_arch_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 18:07:14 -0400