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-rw-r--r--arch/mips/alchemy/common/gpiolib-au1000.c126
-rw-r--r--arch/mips/alchemy/common/pci.c104
2 files changed, 230 insertions, 0 deletions
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
new file mode 100644
index 00000000000..c8e1a94d4a9
--- /dev/null
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO block : GPIO1
27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
35
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h>
38
39static int gpio2_get(struct gpio_chip *chip, unsigned offset)
40{
41 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
42}
43
44static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
45{
46 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
47}
48
49static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
50{
51 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
52}
53
54static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
55 int value)
56{
57 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
58 value);
59}
60
61static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
62{
63 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
64}
65
66
67static int gpio1_get(struct gpio_chip *chip, unsigned offset)
68{
69 return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
70}
71
72static void gpio1_set(struct gpio_chip *chip,
73 unsigned offset, int value)
74{
75 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
76}
77
78static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
79{
80 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
81}
82
83static int gpio1_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
85{
86 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
87 value);
88}
89
90static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
91{
92 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
93}
94
95struct gpio_chip alchemy_gpio_chip[] = {
96 [0] = {
97 .label = "alchemy-gpio1",
98 .direction_input = gpio1_direction_input,
99 .direction_output = gpio1_direction_output,
100 .get = gpio1_get,
101 .set = gpio1_set,
102 .to_irq = gpio1_to_irq,
103 .base = ALCHEMY_GPIO1_BASE,
104 .ngpio = ALCHEMY_GPIO1_NUM,
105 },
106 [1] = {
107 .label = "alchemy-gpio2",
108 .direction_input = gpio2_direction_input,
109 .direction_output = gpio2_direction_output,
110 .get = gpio2_get,
111 .set = gpio2_set,
112 .to_irq = gpio2_to_irq,
113 .base = ALCHEMY_GPIO2_BASE,
114 .ngpio = ALCHEMY_GPIO2_NUM,
115 },
116};
117
118static int __init alchemy_gpiolib_init(void)
119{
120 gpiochip_add(&alchemy_gpio_chip[0]);
121 if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
122 gpiochip_add(&alchemy_gpio_chip[1]);
123
124 return 0;
125}
126arch_initcall(alchemy_gpiolib_init);
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
new file mode 100644
index 00000000000..7866cf50cf9
--- /dev/null
+++ b/arch/mips/alchemy/common/pci.c
@@ -0,0 +1,104 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Alchemy/AMD Au1x00 PCI support.
4 *
5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 *
10 * Support for all devices (greater than 16) added by David Gathright.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#include <linux/pci.h>
34#include <linux/kernel.h>
35#include <linux/init.h>
36
37#include <asm/mach-au1x00/au1000.h>
38
39/* TBD */
40static struct resource pci_io_resource = {
41 .start = PCI_IO_START,
42 .end = PCI_IO_END,
43 .name = "PCI IO space",
44 .flags = IORESOURCE_IO
45};
46
47static struct resource pci_mem_resource = {
48 .start = PCI_MEM_START,
49 .end = PCI_MEM_END,
50 .name = "PCI memory space",
51 .flags = IORESOURCE_MEM
52};
53
54extern struct pci_ops au1x_pci_ops;
55
56static struct pci_controller au1x_controller = {
57 .pci_ops = &au1x_pci_ops,
58 .io_resource = &pci_io_resource,
59 .mem_resource = &pci_mem_resource,
60};
61
62#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
63static unsigned long virt_io_addr;
64#endif
65
66static int __init au1x_pci_setup(void)
67{
68 extern void au1x_pci_cfg_init(void);
69
70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
73
74 if (!virt_io_addr) {
75 printk(KERN_ERR "Unable to ioremap pci space\n");
76 return 1;
77 }
78 au1x_controller.io_map_base = virt_io_addr;
79
80#ifdef CONFIG_DMA_NONCOHERENT
81 {
82 /*
83 * Set the NC bit in controller for Au1500 pre-AC silicon
84 */
85 u32 prid = read_c0_prid();
86
87 if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
88 au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
89 Au1500_PCI_CFG);
90 printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
91 }
92 }
93#endif
94
95 set_io_port_base(virt_io_addr);
96#endif
97
98 au1x_pci_cfg_init();
99
100 register_pci_controller(&au1x_controller);
101 return 0;
102}
103
104arch_initcall(au1x_pci_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 06:18:18 -0400