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-rw-r--r--arch/m32r/include/asm/tlbflush.h2
-rw-r--r--arch/m32r/mm/fault-nommu.c2
-rw-r--r--arch/m32r/mm/fault.c6
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/m32r/include/asm/tlbflush.h b/arch/m32r/include/asm/tlbflush.h
index 0ef95307784..92614b0ccf1 100644
--- a/arch/m32r/include/asm/tlbflush.h
+++ b/arch/m32r/include/asm/tlbflush.h
@@ -92,6 +92,6 @@ static __inline__ void __flush_tlb_all(void)
92 ); 92 );
93} 93}
94 94
95extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); 95extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
96 96
97#endif /* _ASM_M32R_TLBFLUSH_H */ 97#endif /* _ASM_M32R_TLBFLUSH_H */
diff --git a/arch/m32r/mm/fault-nommu.c b/arch/m32r/mm/fault-nommu.c
index 88469178ea6..888aab1157e 100644
--- a/arch/m32r/mm/fault-nommu.c
+++ b/arch/m32r/mm/fault-nommu.c
@@ -95,7 +95,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
95 * update_mmu_cache() 95 * update_mmu_cache()
96 *======================================================================*/ 96 *======================================================================*/
97void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, 97void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
98 pte_t pte) 98 pte_t *ptep)
99{ 99{
100 BUG(); 100 BUG();
101} 101}
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c
index 7274b47f4c2..28ee389e5f5 100644
--- a/arch/m32r/mm/fault.c
+++ b/arch/m32r/mm/fault.c
@@ -336,7 +336,7 @@ vmalloc_fault:
336 336
337 addr = (address & PAGE_MASK); 337 addr = (address & PAGE_MASK);
338 set_thread_fault_code(error_code); 338 set_thread_fault_code(error_code);
339 update_mmu_cache(NULL, addr, *pte_k); 339 update_mmu_cache(NULL, addr, pte_k);
340 set_thread_fault_code(0); 340 set_thread_fault_code(0);
341 return; 341 return;
342 } 342 }
@@ -349,7 +349,7 @@ vmalloc_fault:
349#define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8)) 349#define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
350#define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8)) 350#define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
351void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, 351void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
352 pte_t pte) 352 pte_t *ptep)
353{ 353{
354 volatile unsigned long *entry1, *entry2; 354 volatile unsigned long *entry1, *entry2;
355 unsigned long pte_data, flags; 355 unsigned long pte_data, flags;
@@ -365,7 +365,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
365 365
366 vaddr = (vaddr & PAGE_MASK) | get_asid(); 366 vaddr = (vaddr & PAGE_MASK) | get_asid();
367 367
368 pte_data = pte_val(pte); 368 pte_data = pte_val(*ptep);
369 369
370#ifdef CONFIG_CHIP_OPSP 370#ifdef CONFIG_CHIP_OPSP
371 entry1 = (unsigned long *)ITLB_BASE; 371 entry1 = (unsigned long *)ITLB_BASE;