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Diffstat (limited to 'arch/m32r/platforms/usrv/setup.c')
-rw-r--r--arch/m32r/platforms/usrv/setup.c115
1 files changed, 40 insertions, 75 deletions
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index 1beac7a51ed..f3cff26d6e7 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_mappi(struct irq_data *data)
41{ 41{
42 disable_mappi_irq(irq); 42 disable_mappi_irq(data->irq);
43} 43}
44 44
45static void end_mappi_irq(unsigned int irq) 45static void unmask_mappi(struct irq_data *data)
46{ 46{
47 enable_mappi_irq(irq); 47 enable_mappi_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_mappi_irq(unsigned int irq) 50static void shutdown_mappi(struct irq_data *data)
51{
52 enable_mappi_irq(irq);
53 return 0;
54}
55
56static void shutdown_mappi_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip mappi_irq_type = 58static struct irq_chip mappi_irq_type =
65{ 59{
66 .name = "M32700-IRQ", 60 .name = "M32700-IRQ",
67 .startup = startup_mappi_irq, 61 .irq_shutdown = shutdown_mappi,
68 .shutdown = shutdown_mappi_irq, 62 .irq_mask = mask_mappi,
69 .enable = enable_mappi_irq, 63 .irq_unmask = unmask_mappi,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_mappi_irq
73}; 64};
74 65
75/* 66/*
@@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
107 outw(data, port); 98 outw(data, port);
108} 99}
109 100
110static void mask_and_ack_m32700ut_pld(unsigned int irq) 101static void mask_m32700ut_pld(struct irq_data *data)
111{ 102{
112 disable_m32700ut_pld_irq(irq); 103 disable_m32700ut_pld_irq(data->irq);
113} 104}
114 105
115static void end_m32700ut_pld_irq(unsigned int irq) 106static void unmask_m32700ut_pld(struct irq_data *data)
116{ 107{
117 enable_m32700ut_pld_irq(irq); 108 enable_m32700ut_pld_irq(data->irq);
118 end_mappi_irq(M32R_IRQ_INT1); 109 enable_mappi_irq(M32R_IRQ_INT1);
119}
120
121static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
122{
123 enable_m32700ut_pld_irq(irq);
124 return 0;
125} 110}
126 111
127static void shutdown_m32700ut_pld_irq(unsigned int irq) 112static void shutdown_m32700ut_pld(struct irq_data *data)
128{ 113{
129 unsigned long port; 114 unsigned long port;
130 unsigned int pldirq; 115 unsigned int pldirq;
131 116
132 pldirq = irq2pldirq(irq); 117 pldirq = irq2pldirq(data->irq);
133 port = pldirq2port(pldirq); 118 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port); 119 outw(PLD_ICUCR_ILEVEL7, port);
135} 120}
136 121
137static struct irq_chip m32700ut_pld_irq_type = 122static struct irq_chip m32700ut_pld_irq_type =
138{ 123{
139 .name = "USRV-PLD-IRQ", 124 .name = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq, 125 .irq_shutdown = shutdown_m32700ut_pld,
141 .shutdown = shutdown_m32700ut_pld_irq, 126 .irq_mask = mask_m32700ut_pld,
142 .enable = enable_m32700ut_pld_irq, 127 .irq_unmask = unmask_m32700ut_pld,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
146}; 128};
147 129
148void __init init_IRQ(void) 130void __init init_IRQ(void)
@@ -156,53 +138,42 @@ void __init init_IRQ(void)
156 once++; 138 once++;
157 139
158 /* MFT2 : system timer */ 140 /* MFT2 : system timer */
159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 141 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 142 handle_level_irq);
161 irq_desc[M32R_IRQ_MFT2].action = 0;
162 irq_desc[M32R_IRQ_MFT2].depth = 1;
163 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
164 disable_mappi_irq(M32R_IRQ_MFT2); 144 disable_mappi_irq(M32R_IRQ_MFT2);
165 145
166#if defined(CONFIG_SERIAL_M32R_SIO) 146#if defined(CONFIG_SERIAL_M32R_SIO)
167 /* SIO0_R : uart receive data */ 147 /* SIO0_R : uart receive data */
168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 148 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 149 handle_level_irq);
170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
172 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 150 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
173 disable_mappi_irq(M32R_IRQ_SIO0_R); 151 disable_mappi_irq(M32R_IRQ_SIO0_R);
174 152
175 /* SIO0_S : uart send data */ 153 /* SIO0_S : uart send data */
176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 154 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 155 handle_level_irq);
178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
180 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 156 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
181 disable_mappi_irq(M32R_IRQ_SIO0_S); 157 disable_mappi_irq(M32R_IRQ_SIO0_S);
182 158
183 /* SIO1_R : uart receive data */ 159 /* SIO1_R : uart receive data */
184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 160 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 161 handle_level_irq);
186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
188 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 162 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
189 disable_mappi_irq(M32R_IRQ_SIO1_R); 163 disable_mappi_irq(M32R_IRQ_SIO1_R);
190 164
191 /* SIO1_S : uart send data */ 165 /* SIO1_S : uart send data */
192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 166 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 167 handle_level_irq);
194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
196 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 168 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
197 disable_mappi_irq(M32R_IRQ_SIO1_S); 169 disable_mappi_irq(M32R_IRQ_SIO1_S);
198#endif /* CONFIG_SERIAL_M32R_SIO */ 170#endif /* CONFIG_SERIAL_M32R_SIO */
199 171
200 /* INT#67-#71: CFC#0 IREQ on PLD */ 172 /* INT#67-#71: CFC#0 IREQ on PLD */
201 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { 173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; 174 set_irq_chip_and_handler(PLD_IRQ_CF0 + i,
203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; 175 &m32700ut_pld_irq_type,
204 irq_desc[PLD_IRQ_CF0 + i].action = 0; 176 handle_level_irq);
205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
206 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr 177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
207 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 178 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
208 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); 179 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
@@ -210,19 +181,15 @@ void __init init_IRQ(void)
210 181
211#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 182#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
212 /* INT#76: 16552D#0 IREQ on PLD */ 183 /* INT#76: 16552D#0 IREQ on PLD */
213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; 184 set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; 185 handle_level_irq);
215 irq_desc[PLD_IRQ_UART0].action = 0;
216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
217 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
218 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
219 disable_m32700ut_pld_irq(PLD_IRQ_UART0); 188 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
220 189
221 /* INT#77: 16552D#1 IREQ on PLD */ 190 /* INT#77: 16552D#1 IREQ on PLD */
222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; 191 set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; 192 handle_level_irq);
224 irq_desc[PLD_IRQ_UART1].action = 0;
225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
226 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
227 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
228 disable_m32700ut_pld_irq(PLD_IRQ_UART1); 195 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
@@ -230,10 +197,8 @@ void __init init_IRQ(void)
230 197
231#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 198#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
232 /* INT#80: AK4524 IREQ on PLD */ 199 /* INT#80: AK4524 IREQ on PLD */
233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; 200 set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; 201 handle_level_irq);
235 irq_desc[PLD_IRQ_SNDINT].action = 0;
236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
237 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
238 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
239 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); 204 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);