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diff --git a/arch/ia64/sn/include/xtalk/xbow.h b/arch/ia64/sn/include/xtalk/xbow.h
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
7 */
8#ifndef _ASM_IA64_SN_XTALK_XBOW_H
9#define _ASM_IA64_SN_XTALK_XBOW_H
10
11#define XBOW_PORT_8 0x8
12#define XBOW_PORT_C 0xc
13#define XBOW_PORT_F 0xf
14
15#define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */
16#define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */
17
18#define XBOW_CREDIT 4
19
20#define MAX_XBOW_NAME 16
21
22/* Register set for each xbow link */
23typedef volatile struct xb_linkregs_s {
24/*
25 * we access these through synergy unswizzled space, so the address
26 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
27 * That's why we put the register first and filler second.
28 */
29 uint32_t link_ibf;
30 uint32_t filler0; /* filler for proper alignment */
31 uint32_t link_control;
32 uint32_t filler1;
33 uint32_t link_status;
34 uint32_t filler2;
35 uint32_t link_arb_upper;
36 uint32_t filler3;
37 uint32_t link_arb_lower;
38 uint32_t filler4;
39 uint32_t link_status_clr;
40 uint32_t filler5;
41 uint32_t link_reset;
42 uint32_t filler6;
43 uint32_t link_aux_status;
44 uint32_t filler7;
45} xb_linkregs_t;
46
47typedef volatile struct xbow_s {
48 /* standard widget configuration 0x000000-0x000057 */
49 struct widget_cfg xb_widget; /* 0x000000 */
50
51 /* helper fieldnames for accessing bridge widget */
52
53#define xb_wid_id xb_widget.w_id
54#define xb_wid_stat xb_widget.w_status
55#define xb_wid_err_upper xb_widget.w_err_upper_addr
56#define xb_wid_err_lower xb_widget.w_err_lower_addr
57#define xb_wid_control xb_widget.w_control
58#define xb_wid_req_timeout xb_widget.w_req_timeout
59#define xb_wid_int_upper xb_widget.w_intdest_upper_addr
60#define xb_wid_int_lower xb_widget.w_intdest_lower_addr
61#define xb_wid_err_cmdword xb_widget.w_err_cmd_word
62#define xb_wid_llp xb_widget.w_llp_cfg
63#define xb_wid_stat_clr xb_widget.w_tflush
64
65/*
66 * we access these through synergy unswizzled space, so the address
67 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
68 * That's why we put the register first and filler second.
69 */
70 /* xbow-specific widget configuration 0x000058-0x0000FF */
71 uint32_t xb_wid_arb_reload; /* 0x00005C */
72 uint32_t _pad_000058;
73 uint32_t xb_perf_ctr_a; /* 0x000064 */
74 uint32_t _pad_000060;
75 uint32_t xb_perf_ctr_b; /* 0x00006c */
76 uint32_t _pad_000068;
77 uint32_t xb_nic; /* 0x000074 */
78 uint32_t _pad_000070;
79
80 /* Xbridge only */
81 uint32_t xb_w0_rst_fnc; /* 0x00007C */
82 uint32_t _pad_000078;
83 uint32_t xb_l8_rst_fnc; /* 0x000084 */
84 uint32_t _pad_000080;
85 uint32_t xb_l9_rst_fnc; /* 0x00008c */
86 uint32_t _pad_000088;
87 uint32_t xb_la_rst_fnc; /* 0x000094 */
88 uint32_t _pad_000090;
89 uint32_t xb_lb_rst_fnc; /* 0x00009c */
90 uint32_t _pad_000098;
91 uint32_t xb_lc_rst_fnc; /* 0x0000a4 */
92 uint32_t _pad_0000a0;
93 uint32_t xb_ld_rst_fnc; /* 0x0000ac */
94 uint32_t _pad_0000a8;
95 uint32_t xb_le_rst_fnc; /* 0x0000b4 */
96 uint32_t _pad_0000b0;
97 uint32_t xb_lf_rst_fnc; /* 0x0000bc */
98 uint32_t _pad_0000b8;
99 uint32_t xb_lock; /* 0x0000c4 */
100 uint32_t _pad_0000c0;
101 uint32_t xb_lock_clr; /* 0x0000cc */
102 uint32_t _pad_0000c8;
103 /* end of Xbridge only */
104 uint32_t _pad_0000d0[12];
105
106 /* Link Specific Registers, port 8..15 0x000100-0x000300 */
107 xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
108#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
109
110} xbow_t;
111
112#define XB_FLAGS_EXISTS 0x1 /* device exists */
113#define XB_FLAGS_MASTER 0x2
114#define XB_FLAGS_SLAVE 0x0
115#define XB_FLAGS_GBR 0x4
116#define XB_FLAGS_16BIT 0x8
117#define XB_FLAGS_8BIT 0x0
118
119/* is widget port number valid? (based on version 7.0 of xbow spec) */
120#define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
121
122/* whether to use upper or lower arbitration register, given source widget id */
123#define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
124#define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
125
126/* offset of arbitration register, given source widget id */
127#define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
128
129#define XBOW_WID_ID WIDGET_ID
130#define XBOW_WID_STAT WIDGET_STATUS
131#define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
132#define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
133#define XBOW_WID_CONTROL WIDGET_CONTROL
134#define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT
135#define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
136#define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
137#define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
138#define XBOW_WID_LLP WIDGET_LLP_CFG
139#define XBOW_WID_STAT_CLR WIDGET_TFLUSH
140#define XBOW_WID_ARB_RELOAD 0x5c
141#define XBOW_WID_PERF_CTR_A 0x64
142#define XBOW_WID_PERF_CTR_B 0x6c
143#define XBOW_WID_NIC 0x74
144
145/* Xbridge only */
146#define XBOW_W0_RST_FNC 0x00007C
147#define XBOW_L8_RST_FNC 0x000084
148#define XBOW_L9_RST_FNC 0x00008c
149#define XBOW_LA_RST_FNC 0x000094
150#define XBOW_LB_RST_FNC 0x00009c
151#define XBOW_LC_RST_FNC 0x0000a4
152#define XBOW_LD_RST_FNC 0x0000ac
153#define XBOW_LE_RST_FNC 0x0000b4
154#define XBOW_LF_RST_FNC 0x0000bc
155#define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
156 (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
157 ((x) == 0) ? XBOW_W0_RST_FNC : 0
158#define XBOW_LOCK 0x0000c4
159#define XBOW_LOCK_CLR 0x0000cc
160/* End of Xbridge only */
161
162/* used only in ide, but defined here within the reserved portion */
163/* of the widget0 address space (before 0xf4) */
164#define XBOW_WID_UNDEF 0xe4
165
166/* xbow link register set base, legal value for x is 0x8..0xf */
167#define XB_LINK_BASE 0x100
168#define XB_LINK_OFFSET 0x40
169#define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
170
171#define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4)
172#define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc)
173#define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14)
174#define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c)
175#define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24)
176#define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c)
177#define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34)
178#define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c)
179
180/* link_control(x) */
181#define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */
182 /* reserved: 0x40000000 */
183#define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */
184#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */
185#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */
186#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */
187#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */
188#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */
189#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */
190#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */
191 /* reserved: 0x0000fe00 */
192#define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */
193#define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */
194#define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */
195#define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */
196#define XB_CTRL_RCV_IE 0x00000010 /* receive */
197#define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */
198 /* reserved: 0x00000004 */
199#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */
200#define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */
201
202/* link_status(x) */
203#define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE
204 /* reserved: 0x7ff80000 */
205#define XB_STAT_MULTI_ERR 0x00040000 /* multi error */
206#define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE
207#define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE
208#define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */
209#define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE
210#define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE
211#define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE
212#define XB_STAT_RCV_ERR XB_CTRL_RCV_IE
213#define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE
214 /* reserved: 0x00000004 */
215#define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE
216#define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE
217
218/* link_aux_status(x) */
219#define XB_AUX_STAT_RCV_CNT 0xff000000
220#define XB_AUX_STAT_XMT_CNT 0x00ff0000
221#define XB_AUX_STAT_TOUT_DST 0x0000ff00
222#define XB_AUX_LINKFAIL_RST_BAD 0x00000040
223#define XB_AUX_STAT_PRESENT 0x00000020
224#define XB_AUX_STAT_PORT_WIDTH 0x00000010
225 /* reserved: 0x0000000f */
226
227/*
228 * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
229 * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
230 */
231#define XB_ARB_GBR_MSK 0x1f
232#define XB_ARB_RR_MSK 0x7
233#define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8)
234#define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5)
235#define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
236#define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
237
238/* XBOW_WID_STAT */
239#define XB_WID_STAT_LINK_INTR_SHFT (24)
240#define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
241#define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
242#define XB_WID_STAT_WIDGET0_INTR 0x00800000
243#define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */
244#define XB_WID_STAT_REG_ACC_ERR 0x00000020
245#define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */
246#define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */
247#define XB_WID_STAT_XTALK_ERR 0x00000004
248#define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */
249#define XB_WID_STAT_MULTI_ERR 0x00000001
250
251#define XB_WID_STAT_SRCID_SHFT 6
252
253/* XBOW_WID_CONTROL */
254#define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR
255#define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT
256#define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT
257#define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR
258
259/* XBOW_WID_INT_UPPER */
260/* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
261
262/* XBOW WIDGET part number, in the ID register */
263#define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */
264#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
265#define XBOW_WIDGET_MFGR_NUM 0x0
266#define XXBOW_WIDGET_MFGR_NUM 0x0
267#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */
268
269#define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */
270#define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */
271#define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */
272#define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */
273#define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */
274
275#define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
276#define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
277
278/* XBOW_WID_ARB_RELOAD */
279#define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */
280
281#define IS_XBRIDGE_XBOW(wid) \
282 (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
283 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
284
285#define IS_PIC_XBOW(wid) \
286 (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
287 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
288
289#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
290
291#endif /* _ASM_IA64_SN_XTALK_XBOW_H */
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