6 files changed, 56 insertions, 15 deletions

diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index ef6870e9eea..d5cfe611b77 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -13,6 +13,7 @@
 #include <asm/dma.h>
 #include <asm/clocks.h>
 #include <asm/mem_init.h>
+#include <asm/dpmc.h>
 
 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
 #define PLL_CTL_VAL \
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 01506504e6d..77758289725 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -13,7 +13,7 @@
 #include <linux/fs.h>
 #include <asm/blackfin.h>
 #include <asm/time.h>
-
+#include <asm/dpmc.h>
 
 /* this is the table of CCLK frequencies, in Hz */
 /* .index is the entry in the auxillary dpm_state_table[] */
@@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
                                                  dpm_state_table[index].tscale);
         }
 
-        policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
+        policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
+
         /*Now ,only support one cpu */
         policy->cur = cclk;
         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 8009a512fb1..b0371689605 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -404,6 +404,21 @@ ENTRY(_do_hibernate)
         PM_SYS_PUSH(EBIU_FCTL)
 #endif
 
+#ifdef PORTCIO_FER
+        PM_SYS_PUSH16(PORTCIO_DIR)
+        PM_SYS_PUSH16(PORTCIO_INEN)
+        PM_SYS_PUSH16(PORTCIO)
+        PM_SYS_PUSH16(PORTCIO_FER)
+        PM_SYS_PUSH16(PORTDIO_DIR)
+        PM_SYS_PUSH16(PORTDIO_INEN)
+        PM_SYS_PUSH16(PORTDIO)
+        PM_SYS_PUSH16(PORTDIO_FER)
+        PM_SYS_PUSH16(PORTEIO_DIR)
+        PM_SYS_PUSH16(PORTEIO_INEN)
+        PM_SYS_PUSH16(PORTEIO)
+        PM_SYS_PUSH16(PORTEIO_FER)
+#endif
+
         PM_SYS_PUSH16(SYSCR)
 
         /* Save Core MMRs */
@@ -716,6 +731,21 @@ ENTRY(_do_hibernate)
         P0.L = lo(PLL_CTL);
         PM_SYS_POP16(SYSCR)
 
+#ifdef PORTCIO_FER
+        PM_SYS_POP16(PORTEIO_FER)
+        PM_SYS_POP16(PORTEIO)
+        PM_SYS_POP16(PORTEIO_INEN)
+        PM_SYS_POP16(PORTEIO_DIR)
+        PM_SYS_POP16(PORTDIO_FER)
+        PM_SYS_POP16(PORTDIO)
+        PM_SYS_POP16(PORTDIO_INEN)
+        PM_SYS_POP16(PORTDIO_DIR)
+        PM_SYS_POP16(PORTCIO_FER)
+        PM_SYS_POP16(PORTCIO)
+        PM_SYS_POP16(PORTCIO_INEN)
+        PM_SYS_POP16(PORTCIO_DIR)
+#endif
+
 #ifdef EBIU_FCTL
         PM_SYS_POP(EBIU_FCTL)
         PM_SYS_POP(EBIU_MODE)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index f3f8bb46b51..b0ed0b487ff 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -713,6 +713,8 @@ ENTRY(_system_call)
         cc = BITTST(r7, TIF_RESTORE_SIGMASK);
         if cc jump .Lsyscall_do_signals;
         cc = BITTST(r7, TIF_SIGPENDING);
+        if cc jump .Lsyscall_do_signals;
+        cc = BITTST(r7, TIF_NOTIFY_RESUME);
         if !cc jump .Lsyscall_really_exit;
 .Lsyscall_do_signals:
         /* Reenable interrupts.  */
@@ -721,7 +723,7 @@ ENTRY(_system_call)
 
         r0 = sp;
         SP += -12;
-        call _do_signal;
+        call _do_notify_resume;
         SP += 12;
 
 .Lsyscall_really_exit:
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 660ea1bec54..1873b2c1fed 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -25,11 +25,20 @@
 #include <asm/blackfin.h>
 #include <asm/gpio.h>
 #include <asm/irq_handler.h>
+#include <asm/dpmc.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_sport.h>
 
 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
 
 #ifdef BF537_FAMILY
 # define BF537_GENERIC_ERROR_INT_DEMUX
+# define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
+# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
+# define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
+# define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
+# define UART_ERR_MASK  (0x6)   /* UART_IIR */
+# define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
 #else
 # undef BF537_GENERIC_ERROR_INT_DEMUX
 #endif
@@ -324,11 +333,9 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
                 irq = IRQ_CAN_ERROR;
         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
                 irq = IRQ_SPI_ERROR;
-        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
-                 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
+        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
                 irq = IRQ_UART0_ERROR;
-        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
-                 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
+        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
                 irq = IRQ_UART1_ERROR;
 
         if (irq) {
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index d92b168c832..369e687582b 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -336,13 +336,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
 
         ret = platform_boot_secondary(cpu, idle);
 
-        if (ret) {
-                cpu_clear(cpu, cpu_present_map);
-                printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
-                free_task(idle);
-        } else
-                cpu_set(cpu, cpu_online_map);
-
         secondary_stack = NULL;
 
         return ret;
@@ -418,9 +411,16 @@ void __cpuinit secondary_start_kernel(void)
 
         setup_secondary(cpu);
 
+        platform_secondary_init(cpu);
+
         local_irq_enable();
 
-        platform_secondary_init(cpu);
+        /*
+         * Calibrate loops per jiffy value.
+         * IRQs need to be enabled here - D-cache can be invalidated
+         * in timer irq handler, so core B can read correct jiffies.
+         */
+        calibrate_delay();
 
         cpu_idle();
 }