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-rw-r--r--arch/blackfin/mach-common/ints-priority.c68
1 files changed, 61 insertions, 7 deletions
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 64d746114e4..62f8883a5c2 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -71,6 +71,7 @@ atomic_t num_spurious;
71 71
72#ifdef CONFIG_PM 72#ifdef CONFIG_PM
73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ 73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74unsigned vr_wakeup;
74#endif 75#endif
75 76
76struct ivgx { 77struct ivgx {
@@ -184,17 +185,56 @@ static void bfin_internal_unmask_irq(unsigned int irq)
184#ifdef CONFIG_PM 185#ifdef CONFIG_PM
185int bfin_internal_set_wake(unsigned int irq, unsigned int state) 186int bfin_internal_set_wake(unsigned int irq, unsigned int state)
186{ 187{
187 unsigned bank, bit; 188 unsigned bank, bit, wakeup = 0;
188 unsigned long flags; 189 unsigned long flags;
189 bank = SIC_SYSIRQ(irq) / 32; 190 bank = SIC_SYSIRQ(irq) / 32;
190 bit = SIC_SYSIRQ(irq) % 32; 191 bit = SIC_SYSIRQ(irq) % 32;
191 192
193 switch (irq) {
194#ifdef IRQ_RTC
195 case IRQ_RTC:
196 wakeup |= WAKE;
197 break;
198#endif
199#ifdef IRQ_CAN0_RX
200 case IRQ_CAN0_RX:
201 wakeup |= CANWE;
202 break;
203#endif
204#ifdef IRQ_CAN1_RX
205 case IRQ_CAN1_RX:
206 wakeup |= CANWE;
207 break;
208#endif
209#ifdef IRQ_USB_INT0
210 case IRQ_USB_INT0:
211 wakeup |= USBWE;
212 break;
213#endif
214#ifdef IRQ_KEY
215 case IRQ_KEY:
216 wakeup |= KPADWE;
217 break;
218#endif
219#ifdef IRQ_CNT
220 case IRQ_CNT:
221 wakeup |= ROTWE;
222 break;
223#endif
224 default:
225 break;
226 }
227
192 local_irq_save(flags); 228 local_irq_save(flags);
193 229
194 if (state) 230 if (state) {
195 bfin_sic_iwr[bank] |= (1 << bit); 231 bfin_sic_iwr[bank] |= (1 << bit);
196 else 232 vr_wakeup |= wakeup;
233
234 } else {
197 bfin_sic_iwr[bank] &= ~(1 << bit); 235 bfin_sic_iwr[bank] &= ~(1 << bit);
236 vr_wakeup &= ~wakeup;
237 }
198 238
199 local_irq_restore(flags); 239 local_irq_restore(flags);
200 240
@@ -943,6 +983,11 @@ int __init init_arch_irq(void)
943 983
944 local_irq_disable(); 984 local_irq_disable();
945 985
986#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
987 /* Clear EMAC Interrupt Status bits so we can demux it later */
988 bfin_write_EMAC_SYSTAT(-1);
989#endif
990
946#ifdef CONFIG_BF54x 991#ifdef CONFIG_BF54x
947# ifdef CONFIG_PINTx_REASSIGN 992# ifdef CONFIG_PINTx_REASSIGN
948 pint[0]->assign = CONFIG_PINT0_ASSIGN; 993 pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1028,13 +1073,22 @@ int __init init_arch_irq(void)
1028 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 1073 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1029 1074
1030#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) 1075#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1031 bfin_write_SIC_IWR0(IWR_ENABLE_ALL); 1076 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1032 bfin_write_SIC_IWR1(IWR_ENABLE_ALL); 1077#if defined(CONFIG_BF52x)
1078 /* BF52x system reset does not properly reset SIC_IWR1 which
1079 * will screw up the bootrom as it relies on MDMA0/1 waking it
1080 * up from IDLE instructions. See this report for more info:
1081 * http://blackfin.uclinux.org/gf/tracker/4323
1082 */
1083 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1084#else
1085 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1086#endif
1033# ifdef CONFIG_BF54x 1087# ifdef CONFIG_BF54x
1034 bfin_write_SIC_IWR2(IWR_ENABLE_ALL); 1088 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1035# endif 1089# endif
1036#else 1090#else
1037 bfin_write_SIC_IWR(IWR_ENABLE_ALL); 1091 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1038#endif 1092#endif
1039 1093
1040 return 0; 1094 return 0;