diff options
Diffstat (limited to 'arch/blackfin/mach-bf561/smp.c')
-rw-r--r-- | arch/blackfin/mach-bf561/smp.c | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index f540ed1257d..1074a7ef81c 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c | |||
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle | |||
86 | 86 | ||
87 | spin_lock(&boot_lock); | 87 | spin_lock(&boot_lock); |
88 | 88 | ||
89 | if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { | 89 | if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { |
90 | /* CoreB already running, sending ipi to wakeup it */ | 90 | /* CoreB already running, sending ipi to wakeup it */ |
91 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); | 91 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); |
92 | } else { | 92 | } else { |
93 | /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ | 93 | /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ |
94 | bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); | 94 | bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); |
95 | SSYNC(); | 95 | SSYNC(); |
96 | } | 96 | } |
97 | 97 | ||
@@ -111,41 +111,46 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle | |||
111 | panic("CPU%u: processor failed to boot\n", cpu); | 111 | panic("CPU%u: processor failed to boot\n", cpu); |
112 | } | 112 | } |
113 | 113 | ||
114 | void __init platform_request_ipi(irq_handler_t handler) | 114 | static const char supple0[] = "IRQ_SUPPLE_0"; |
115 | static const char supple1[] = "IRQ_SUPPLE_1"; | ||
116 | void __init platform_request_ipi(int irq, void *handler) | ||
115 | { | 117 | { |
116 | int ret; | 118 | int ret; |
119 | const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1; | ||
117 | 120 | ||
118 | ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED, | 121 | ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler); |
119 | "Supplemental Interrupt0", handler); | ||
120 | if (ret) | 122 | if (ret) |
121 | panic("Cannot request supplemental interrupt 0 for IPI service"); | 123 | panic("Cannot request %s for IPI service", name); |
122 | } | 124 | } |
123 | 125 | ||
124 | void platform_send_ipi(cpumask_t callmap) | 126 | void platform_send_ipi(cpumask_t callmap, int irq) |
125 | { | 127 | { |
126 | unsigned int cpu; | 128 | unsigned int cpu; |
129 | int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8; | ||
127 | 130 | ||
128 | for_each_cpu_mask(cpu, callmap) { | 131 | for_each_cpu_mask(cpu, callmap) { |
129 | BUG_ON(cpu >= 2); | 132 | BUG_ON(cpu >= 2); |
130 | SSYNC(); | 133 | SSYNC(); |
131 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); | 134 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); |
132 | SSYNC(); | 135 | SSYNC(); |
133 | } | 136 | } |
134 | } | 137 | } |
135 | 138 | ||
136 | void platform_send_ipi_cpu(unsigned int cpu) | 139 | void platform_send_ipi_cpu(unsigned int cpu, int irq) |
137 | { | 140 | { |
141 | int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8; | ||
138 | BUG_ON(cpu >= 2); | 142 | BUG_ON(cpu >= 2); |
139 | SSYNC(); | 143 | SSYNC(); |
140 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu))); | 144 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); |
141 | SSYNC(); | 145 | SSYNC(); |
142 | } | 146 | } |
143 | 147 | ||
144 | void platform_clear_ipi(unsigned int cpu) | 148 | void platform_clear_ipi(unsigned int cpu, int irq) |
145 | { | 149 | { |
150 | int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12; | ||
146 | BUG_ON(cpu >= 2); | 151 | BUG_ON(cpu >= 2); |
147 | SSYNC(); | 152 | SSYNC(); |
148 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu))); | 153 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu))); |
149 | SSYNC(); | 154 | SSYNC(); |
150 | } | 155 | } |
151 | 156 | ||