diff options
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/defBF561.h')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 37 |
1 files changed, 17 insertions, 20 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index 6f59ac669f1..79e048d452e 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h | |||
| @@ -28,32 +28,29 @@ | |||
| 28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ | 28 | #define CHIPID 0xFFC00014 /* Chip ID Register */ |
| 29 | 29 | ||
| 30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ | 30 | /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ |
| 31 | #define SWRST SICA_SWRST | ||
| 32 | #define SYSCR SICA_SYSCR | ||
| 33 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) | 31 | #define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) |
| 34 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) | 32 | #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) |
| 35 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) | 33 | #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) |
| 36 | #define RESET_SOFTWARE (SWRST_OCCURRED) | 34 | #define RESET_SOFTWARE (SWRST_OCCURRED) |
| 37 | 35 | ||
| 38 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ | 36 | /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ |
| 39 | #define SICA_SWRST 0xFFC00100 /* Software Reset register */ | 37 | #define SWRST 0xFFC00100 /* Software Reset register */ |
| 40 | #define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */ | 38 | #define SYSCR 0xFFC00104 /* System Reset Configuration register */ |
| 41 | #define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ | 39 | #define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */ |
| 42 | #define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */ | 40 | #define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ |
| 43 | #define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */ | 41 | #define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ |
| 44 | #define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */ | 42 | #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ |
| 45 | #define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ | 43 | #define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ |
| 46 | #define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */ | 44 | #define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ |
| 47 | #define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */ | 45 | #define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ |
| 48 | #define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */ | 46 | #define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ |
| 49 | #define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */ | 47 | #define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ |
| 50 | #define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */ | 48 | #define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ |
| 51 | #define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */ | 49 | #define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ |
| 52 | #define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */ | 50 | #define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ |
| 53 | #define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */ | 51 | #define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ |
| 54 | #define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */ | 52 | #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ |
| 55 | #define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */ | 53 | #define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ |
| 56 | #define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */ | ||
| 57 | 54 | ||
| 58 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ | 55 | /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */ |
| 59 | #define SICB_SWRST 0xFFC01100 /* reserved */ | 56 | #define SICB_SWRST 0xFFC01100 /* reserved */ |