aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf548/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/blackfin/mach-bf548/include')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial.h16
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h60
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h70
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF542.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF544.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF547.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF548.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF549.h10
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h23
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF542.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h7
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h321
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h11
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/pll.h70
18 files changed, 92 insertions, 586 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
new file mode 100644
index 00000000000..a77109f9972
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
@@ -0,0 +1,16 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2006-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 4
13
14#define BFIN_UART_BF54X_STYLE
15
16#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index dd44aa75fe7..0d94edaaaa2 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -4,72 +4,14 @@
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#include <linux/serial.h>
8#include <asm/dma.h> 7#include <asm/dma.h>
9#include <asm/portmux.h> 8#include <asm/portmux.h>
10 9
11#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
12#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
13#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
14#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
15#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
16#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
17#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
18#define UART_GET_MSR(uart) bfin_read16(((uart)->port.membase + OFFSET_MSR))
19#define UART_GET_MCR(uart) bfin_read16(((uart)->port.membase + OFFSET_MCR))
20
21#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
22#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
23#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
24#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
25#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
26#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
27#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
28#define UART_CLEAR_LSR(uart) bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
29#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
30#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
31#define UART_CLEAR_SCTS(uart) bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
32
33#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
34#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
35
36#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
37#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
38#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
39#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
40#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
41
42#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \ 10#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
43 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS) 11 defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
44# define CONFIG_SERIAL_BFIN_HARD_CTSRTS 12# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
45#endif 13#endif
46 14
47#define BFIN_UART_TX_FIFO_SIZE 2
48
49/*
50 * The pin configuration is different from schematic
51 */
52struct bfin_serial_port {
53 struct uart_port port;
54 unsigned int old_status;
55 int status_irq;
56#ifdef CONFIG_SERIAL_BFIN_DMA
57 int tx_done;
58 int tx_count;
59 struct circ_buf rx_dma_buf;
60 struct timer_list rx_dma_timer;
61 int rx_dma_nrows;
62 unsigned int tx_dma_channel;
63 unsigned int rx_dma_channel;
64 struct work_struct tx_dma_workqueue;
65#endif
66#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
67 int scts;
68 int cts_pin;
69 int rts_pin;
70#endif
71};
72
73struct bfin_serial_res { 15struct bfin_serial_res {
74 unsigned long uart_base_addr; 16 unsigned long uart_base_addr;
75 int uart_irq; 17 int uart_irq;
@@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
148}; 90};
149 91
150#define DRIVER_NAME "bfin-uart" 92#define DRIVER_NAME "bfin-uart"
93
94#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 5684030ccc2..72da721a77f 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2009 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -10,58 +10,40 @@
10#include "bf548.h" 10#include "bf548.h"
11#include "anomaly.h" 11#include "anomaly.h"
12 12
13#include <asm/def_LPBlackfin.h>
13#ifdef CONFIG_BF542 14#ifdef CONFIG_BF542
14#include "defBF542.h" 15# include "defBF542.h"
15#endif 16#endif
16
17#ifdef CONFIG_BF544 17#ifdef CONFIG_BF544
18#include "defBF544.h" 18# include "defBF544.h"
19#endif 19#endif
20
21#ifdef CONFIG_BF547 20#ifdef CONFIG_BF547
22#include "defBF547.h" 21# include "defBF547.h"
23#endif 22#endif
24
25#ifdef CONFIG_BF548 23#ifdef CONFIG_BF548
26#include "defBF548.h" 24# include "defBF548.h"
27#endif 25#endif
28
29#ifdef CONFIG_BF549 26#ifdef CONFIG_BF549
30#include "defBF549.h" 27# include "defBF549.h"
31#endif 28#endif
32 29
33#if !defined(__ASSEMBLY__) 30#ifndef __ASSEMBLY__
34#ifdef CONFIG_BF542 31# include <asm/cdef_LPBlackfin.h>
35#include "cdefBF542.h" 32# ifdef CONFIG_BF542
33# include "cdefBF542.h"
34# endif
35# ifdef CONFIG_BF544
36# include "cdefBF544.h"
37# endif
38# ifdef CONFIG_BF547
39# include "cdefBF547.h"
40# endif
41# ifdef CONFIG_BF548
42# include "cdefBF548.h"
43# endif
44# ifdef CONFIG_BF549
45# include "cdefBF549.h"
46# endif
36#endif 47#endif
37#ifdef CONFIG_BF544
38#include "cdefBF544.h"
39#endif
40#ifdef CONFIG_BF547
41#include "cdefBF547.h"
42#endif
43#ifdef CONFIG_BF548
44#include "cdefBF548.h"
45#endif
46#ifdef CONFIG_BF549
47#include "cdefBF549.h"
48#endif
49
50#endif
51
52#define BFIN_UART_NR_PORTS 4
53
54#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
55#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
56#define OFFSET_GCTL 0x08 /* Global Control Register */
57#define OFFSET_LCR 0x0C /* Line Control Register */
58#define OFFSET_MCR 0x10 /* Modem Control Register */
59#define OFFSET_LSR 0x14 /* Line Status Register */
60#define OFFSET_MSR 0x18 /* Modem Status Register */
61#define OFFSET_SCR 0x1C /* SCR Scratch Register */
62#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
63#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
64#define OFFSET_THR 0x28 /* Transmit Holding register */
65#define OFFSET_RBR 0x2C /* Receive Buffer register */
66 48
67#endif 49#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
index 42f4a946954..d09c19cd1b7 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF542_H 7#ifndef _CDEF_BF542_H
8#define _CDEF_BF542_H 8#define _CDEF_BF542_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF542.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
index 2207799575f..33ec8102ced 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF544_H 7#ifndef _CDEF_BF544_H
8#define _CDEF_BF544_H 8#define _CDEF_BF544_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF544.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
index bc650e6ea48..bcb9726dea5 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF547_H 7#ifndef _CDEF_BF547_H
8#define _CDEF_BF547_H 8#define _CDEF_BF547_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF547.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index 3523e08f796..bae67a65633 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF548_H 7#ifndef _CDEF_BF548_H
8#define _CDEF_BF548_H 8#define _CDEF_BF548_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF548.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 80201ed41f8..002136ad5a4 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,14 +7,6 @@
7#ifndef _CDEF_BF549_H 7#ifndef _CDEF_BF549_H
8#define _CDEF_BF549_H 8#define _CDEF_BF549_H
9 9
10/* include all Core registers and bit definitions */
11#include "defBF549.h"
12
13/* include core sbfin_read_()ecific register pointer definitions */
14#include <asm/cdef_LPBlackfin.h>
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
17
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 10/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 11#include "cdefBF54x_base.h"
20 12
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index deaf5d6542d..50c89c8052f 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -7,10 +7,6 @@
7#ifndef _CDEF_BF54X_H 7#ifndef _CDEF_BF54X_H
8#define _CDEF_BF54X_H 8#define _CDEF_BF54X_H
9 9
10#include <asm/blackfin.h>
11
12#include "defBF54x_base.h"
13
14/* ************************************************************** */ 10/* ************************************************************** */
15/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
16/* ************************************************************** */ 12/* ************************************************************** */
@@ -2633,22 +2629,5 @@
2633 2629
2634/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ 2630/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2635 2631
2636/* legacy definitions */
2637#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0
2638#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0
2639#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1
2640#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1
2641#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST
2642#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST
2643#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST
2644#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST
2645#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST
2646#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST
2647#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2648#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2649
2650/* These need to be last due to the cdef/linux inter-dependencies */
2651#include <asm/irq.h>
2652
2653#endif /* _CDEF_BF54X_H */ 2632#endif /* _CDEF_BF54X_H */
2654 2633
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index abf5f750dd8..629bf216e2b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF542_H 7#ifndef _DEF_BF542_H
8#define _DEF_BF542_H 8#define _DEF_BF542_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index e2771094de0..642468c1bcb 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF544_H 7#ifndef _DEF_BF544_H
8#define _DEF_BF544_H 8#define _DEF_BF544_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index be21ba5b3aa..2f3337cd311 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF547_H 7#ifndef _DEF_BF547_H
8#define _DEF_BF547_H 8#define _DEF_BF547_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3fb33b040ab..3c7f1b69349 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF548_H 7#ifndef _DEF_BF548_H
8#define _DEF_BF548_H 8#define _DEF_BF548_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 5a04e6d4017..9a45cb6b30d 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -7,11 +7,6 @@
7#ifndef _DEF_BF549_H 7#ifndef _DEF_BF549_H
8#define _DEF_BF549_H 8#define _DEF_BF549_H
9 9
10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h>
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
14
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 10/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 11#include "defBF54x_base.h"
17 12
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 78f91103f17..0867c2bedb4 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2007-2008 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
@@ -1615,14 +1615,14 @@
1615#define CTYPE 0x40 /* DMA Channel Type */ 1615#define CTYPE 0x40 /* DMA Channel Type */
1616#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ 1616#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1617 1617
1618/* Bit masks for DMACx_TCPER */ 1618/* Bit masks for DMACx_TC_PER */
1619 1619
1620#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ 1620#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
1621#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ 1621#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
1622#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ 1622#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
1623#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ 1623#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
1624 1624
1625/* Bit masks for DMACx_TCCNT */ 1625/* Bit masks for DMACx_TC_CNT */
1626 1626
1627#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ 1627#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
1628#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ 1628#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
@@ -2172,68 +2172,6 @@
2172 2172
2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */ 2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2174 2174
2175/* Bit masks for UARTx_LCR */
2176
2177#if 0
2178/* conflicts with legacy one in last section */
2179#define WLS 0x3 /* Word Length Select */
2180#endif
2181#define STB 0x4 /* Stop Bits */
2182#define PEN 0x8 /* Parity Enable */
2183#define EPS 0x10 /* Even Parity Select */
2184#define STP 0x20 /* Sticky Parity */
2185#define SB 0x40 /* Set Break */
2186
2187/* Bit masks for UARTx_MCR */
2188
2189#define XOFF 0x1 /* Transmitter Off */
2190#define MRTS 0x2 /* Manual Request To Send */
2191#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
2192#define RFRT 0x8 /* Receive FIFO RTS Threshold */
2193#define LOOP_ENA 0x10 /* Loopback Mode Enable */
2194#define FCPOL 0x20 /* Flow Control Pin Polarity */
2195#define ARTS 0x40 /* Automatic Request To Send */
2196#define ACTS 0x80 /* Automatic Clear To Send */
2197
2198/* Bit masks for UARTx_LSR */
2199
2200#define DR 0x1 /* Data Ready */
2201#define OE 0x2 /* Overrun Error */
2202#define PE 0x4 /* Parity Error */
2203#define FE 0x8 /* Framing Error */
2204#define BI 0x10 /* Break Interrupt */
2205#define THRE 0x20 /* THR Empty */
2206#define TEMT 0x40 /* Transmitter Empty */
2207#define TFI 0x80 /* Transmission Finished Indicator */
2208
2209/* Bit masks for UARTx_MSR */
2210
2211#define SCTS 0x1 /* Sticky CTS */
2212#define CTS 0x10 /* Clear To Send */
2213#define RFCS 0x20 /* Receive FIFO Count Status */
2214
2215/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
2216
2217#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
2218#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
2219#define ELSI 0x4 /* Enable Receive Status Interrupt */
2220#define EDSSI 0x8 /* Enable Modem Status Interrupt */
2221#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
2222#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
2223#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
2224
2225/* Bit masks for UARTx_GCTL */
2226
2227#define UCEN 0x1 /* UART Enable */
2228#define IREN 0x2 /* IrDA Mode Enable */
2229#define TPOLC 0x4 /* IrDA TX Polarity Change */
2230#define RPOLC 0x8 /* IrDA RX Polarity Change */
2231#define FPE 0x10 /* Force Parity Error */
2232#define FFE 0x20 /* Force Framing Error */
2233#define EDBO 0x40 /* Enable Divide-by-One */
2234#define EGLSI 0x80 /* Enable Global LS Interrupt */
2235
2236
2237/* ******************************************* */ 2175/* ******************************************* */
2238/* MULTI BIT MACRO ENUMERATIONS */ 2176/* MULTI BIT MACRO ENUMERATIONS */
2239/* ******************************************* */ 2177/* ******************************************* */
@@ -2251,13 +2189,6 @@
2251#define WDTH_CAP 0x0002 2189#define WDTH_CAP 0x0002
2252#define EXT_CLK 0x0003 2190#define EXT_CLK 0x0003
2253 2191
2254/* UARTx_LCR bit field options */
2255
2256#define WLS_5 0x0000 /* 5 data bits */
2257#define WLS_6 0x0001 /* 6 data bits */
2258#define WLS_7 0x0002 /* 7 data bits */
2259#define WLS_8 0x0003 /* 8 data bits */
2260
2261/* PINTx Register Bit Definitions */ 2192/* PINTx Register Bit Definitions */
2262 2193
2263#define PIQ0 0x00000001 2194#define PIQ0 0x00000001
@@ -2300,240 +2231,6 @@
2300#define PIQ30 0x40000000 2231#define PIQ30 0x40000000
2301#define PIQ31 0x80000000 2232#define PIQ31 0x80000000
2302 2233
2303/* PORT A Bit Definitions for the registers
2304PORTA, PORTA_SET, PORTA_CLEAR,
2305PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
2306PORTA_FER registers
2307*/
2308
2309#define PA0 0x0001
2310#define PA1 0x0002
2311#define PA2 0x0004
2312#define PA3 0x0008
2313#define PA4 0x0010
2314#define PA5 0x0020
2315#define PA6 0x0040
2316#define PA7 0x0080
2317#define PA8 0x0100
2318#define PA9 0x0200
2319#define PA10 0x0400
2320#define PA11 0x0800
2321#define PA12 0x1000
2322#define PA13 0x2000
2323#define PA14 0x4000
2324#define PA15 0x8000
2325
2326/* PORT B Bit Definitions for the registers
2327PORTB, PORTB_SET, PORTB_CLEAR,
2328PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
2329PORTB_FER registers
2330*/
2331
2332#define PB0 0x0001
2333#define PB1 0x0002
2334#define PB2 0x0004
2335#define PB3 0x0008
2336#define PB4 0x0010
2337#define PB5 0x0020
2338#define PB6 0x0040
2339#define PB7 0x0080
2340#define PB8 0x0100
2341#define PB9 0x0200
2342#define PB10 0x0400
2343#define PB11 0x0800
2344#define PB12 0x1000
2345#define PB13 0x2000
2346#define PB14 0x4000
2347
2348
2349/* PORT C Bit Definitions for the registers
2350PORTC, PORTC_SET, PORTC_CLEAR,
2351PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
2352PORTC_FER registers
2353*/
2354
2355
2356#define PC0 0x0001
2357#define PC1 0x0002
2358#define PC2 0x0004
2359#define PC3 0x0008
2360#define PC4 0x0010
2361#define PC5 0x0020
2362#define PC6 0x0040
2363#define PC7 0x0080
2364#define PC8 0x0100
2365#define PC9 0x0200
2366#define PC10 0x0400
2367#define PC11 0x0800
2368#define PC12 0x1000
2369#define PC13 0x2000
2370
2371
2372/* PORT D Bit Definitions for the registers
2373PORTD, PORTD_SET, PORTD_CLEAR,
2374PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
2375PORTD_FER registers
2376*/
2377
2378#define PD0 0x0001
2379#define PD1 0x0002
2380#define PD2 0x0004
2381#define PD3 0x0008
2382#define PD4 0x0010
2383#define PD5 0x0020
2384#define PD6 0x0040
2385#define PD7 0x0080
2386#define PD8 0x0100
2387#define PD9 0x0200
2388#define PD10 0x0400
2389#define PD11 0x0800
2390#define PD12 0x1000
2391#define PD13 0x2000
2392#define PD14 0x4000
2393#define PD15 0x8000
2394
2395/* PORT E Bit Definitions for the registers
2396PORTE, PORTE_SET, PORTE_CLEAR,
2397PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
2398PORTE_FER registers
2399*/
2400
2401
2402#define PE0 0x0001
2403#define PE1 0x0002
2404#define PE2 0x0004
2405#define PE3 0x0008
2406#define PE4 0x0010
2407#define PE5 0x0020
2408#define PE6 0x0040
2409#define PE7 0x0080
2410#define PE8 0x0100
2411#define PE9 0x0200
2412#define PE10 0x0400
2413#define PE11 0x0800
2414#define PE12 0x1000
2415#define PE13 0x2000
2416#define PE14 0x4000
2417#define PE15 0x8000
2418
2419/* PORT F Bit Definitions for the registers
2420PORTF, PORTF_SET, PORTF_CLEAR,
2421PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
2422PORTF_FER registers
2423*/
2424
2425
2426#define PF0 0x0001
2427#define PF1 0x0002
2428#define PF2 0x0004
2429#define PF3 0x0008
2430#define PF4 0x0010
2431#define PF5 0x0020
2432#define PF6 0x0040
2433#define PF7 0x0080
2434#define PF8 0x0100
2435#define PF9 0x0200
2436#define PF10 0x0400
2437#define PF11 0x0800
2438#define PF12 0x1000
2439#define PF13 0x2000
2440#define PF14 0x4000
2441#define PF15 0x8000
2442
2443/* PORT G Bit Definitions for the registers
2444PORTG, PORTG_SET, PORTG_CLEAR,
2445PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
2446PORTG_FER registers
2447*/
2448
2449
2450#define PG0 0x0001
2451#define PG1 0x0002
2452#define PG2 0x0004
2453#define PG3 0x0008
2454#define PG4 0x0010
2455#define PG5 0x0020
2456#define PG6 0x0040
2457#define PG7 0x0080
2458#define PG8 0x0100
2459#define PG9 0x0200
2460#define PG10 0x0400
2461#define PG11 0x0800
2462#define PG12 0x1000
2463#define PG13 0x2000
2464#define PG14 0x4000
2465#define PG15 0x8000
2466
2467/* PORT H Bit Definitions for the registers
2468PORTH, PORTH_SET, PORTH_CLEAR,
2469PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
2470PORTH_FER registers
2471*/
2472
2473
2474#define PH0 0x0001
2475#define PH1 0x0002
2476#define PH2 0x0004
2477#define PH3 0x0008
2478#define PH4 0x0010
2479#define PH5 0x0020
2480#define PH6 0x0040
2481#define PH7 0x0080
2482#define PH8 0x0100
2483#define PH9 0x0200
2484#define PH10 0x0400
2485#define PH11 0x0800
2486#define PH12 0x1000
2487#define PH13 0x2000
2488
2489
2490/* PORT I Bit Definitions for the registers
2491PORTI, PORTI_SET, PORTI_CLEAR,
2492PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
2493PORTI_FER registers
2494*/
2495
2496
2497#define PI0 0x0001
2498#define PI1 0x0002
2499#define PI2 0x0004
2500#define PI3 0x0008
2501#define PI4 0x0010
2502#define PI5 0x0020
2503#define PI6 0x0040
2504#define PI7 0x0080
2505#define PI8 0x0100
2506#define PI9 0x0200
2507#define PI10 0x0400
2508#define PI11 0x0800
2509#define PI12 0x1000
2510#define PI13 0x2000
2511#define PI14 0x4000
2512#define PI15 0x8000
2513
2514/* PORT J Bit Definitions for the registers
2515PORTJ, PORTJ_SET, PORTJ_CLEAR,
2516PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
2517PORTJ_FER registers
2518*/
2519
2520
2521#define PJ0 0x0001
2522#define PJ1 0x0002
2523#define PJ2 0x0004
2524#define PJ3 0x0008
2525#define PJ4 0x0010
2526#define PJ5 0x0020
2527#define PJ6 0x0040
2528#define PJ7 0x0080
2529#define PJ8 0x0100
2530#define PJ9 0x0200
2531#define PJ10 0x0400
2532#define PJ11 0x0800
2533#define PJ12 0x1000
2534#define PJ13 0x2000
2535
2536
2537/* Port Muxing Bit Fields for PORTx_MUX Registers */ 2234/* Port Muxing Bit Fields for PORTx_MUX Registers */
2538 2235
2539#define MUX0 0x00000003 2236#define MUX0 0x00000003
@@ -2703,16 +2400,4 @@ PORTJ_FER registers
2703#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ 2400#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
2704#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ 2401#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
2705 2402
2706
2707/* for legacy compatibility */
2708
2709#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
2710#define W1LMAX_MAX W1LMAX_MIN
2711#define EBIU_AMCBCTL0 EBIU_AMBCTL0
2712#define EBIU_AMCBCTL1 EBIU_AMBCTL1
2713#define PINT0_IRQ PINT0_REQUEST
2714#define PINT1_IRQ PINT1_REQUEST
2715#define PINT2_IRQ PINT2_REQUEST
2716#define PINT3_IRQ PINT3_REQUEST
2717
2718#endif /* _DEF_BF54X_H */ 2403#endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 28037e33196..7db433514e3 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -200,4 +200,15 @@ struct gpio_port_s {
200 200
201#endif 201#endif
202 202
203#include <mach-common/ports-a.h>
204#include <mach-common/ports-b.h>
205#include <mach-common/ports-c.h>
206#include <mach-common/ports-d.h>
207#include <mach-common/ports-e.h>
208#include <mach-common/ports-f.h>
209#include <mach-common/ports-g.h>
210#include <mach-common/ports-h.h>
211#include <mach-common/ports-i.h>
212#include <mach-common/ports-j.h>
213
203#endif /* _MACH_GPIO_H_ */ 214#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 1f99b51a3d5..99fd1b2c53d 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -474,4 +474,26 @@ Events (highest priority) EMU 0
474#define IRQ_PINT2_POS 24 474#define IRQ_PINT2_POS 24
475#define IRQ_PINT3_POS 28 475#define IRQ_PINT3_POS 28
476 476
477#ifndef __ASSEMBLY__
478#include <linux/types.h>
479
480/*
481 * bfin pint registers layout
482 */
483struct bfin_pint_regs {
484 u32 mask_set;
485 u32 mask_clear;
486 u32 irq;
487 u32 assign;
488 u32 edge_set;
489 u32 edge_clear;
490 u32 invert_set;
491 u32 invert_clear;
492 u32 pinstate;
493 u32 latch;
494 u32 __pad0[2];
495};
496
497#endif
498
477#endif /* _BF548_IRQ_H_ */ 499#endif /* _BF548_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 7865a090d33..94cca674d83 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -1,69 +1 @@
1/* #include <mach-common/pll.h>
2 * Copyright 2007-2008 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_PLL_H
8#define _MACH_PLL_H
9
10#include <asm/blackfin.h>
11#include <asm/irqflags.h>
12
13/* Writing to PLL_CTL initiates a PLL relock sequence. */
14static __inline__ void bfin_write_PLL_CTL(unsigned int val)
15{
16 unsigned long flags, iwr0, iwr1, iwr2;
17
18 if (val == bfin_read_PLL_CTL())
19 return;
20
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
30
31 bfin_write16(PLL_CTL, val);
32 SSYNC();
33 asm("IDLE;");
34
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 hard_local_irq_restore(flags);
39}
40
41/* Writing to VR_CTL initiates a PLL relock sequence. */
42static __inline__ void bfin_write_VR_CTL(unsigned int val)
43{
44 unsigned long flags, iwr0, iwr1, iwr2;
45
46 if (val == bfin_read_VR_CTL())
47 return;
48
49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
58
59 bfin_write16(VR_CTL, val);
60 SSYNC();
61 asm("IDLE;");
62
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 hard_local_irq_restore(flags);
67}
68
69#endif /* _MACH_PLL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 22:52:08 -0400