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-rw-r--r--arch/blackfin/mach-bf548/head.S133
1 files changed, 3 insertions, 130 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 832a8d7212a..cf94e1e222b 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -30,145 +30,18 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34#ifdef CONFIG_BFIN_KERNEL_CLOCK 33#ifdef CONFIG_BFIN_KERNEL_CLOCK
35#include <asm/mach-common/clocks.h> 34#include <asm/mach-common/clocks.h>
36#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
37#endif 36#endif
38 37
39.extern ___bss_stop
40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem 38.extern _bf53x_relocate_l1_mem
42 39
43#define INITIAL_STACK 0xFFB01000
44
45__INIT 40__INIT
46 41
47ENTRY(__start) 42ENTRY(_mach_early_start)
48 /* R0: argument of command line string, passed from uboot, save it */ 43 rts;
49 R7 = R0; 44ENDPROC(_mach_early_start)
50 /* Enable Cycle Counter and Nesting Of Interrupts */
51#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
52 R0 = SYSCFG_SNEN;
53#else
54 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
55#endif
56 SYSCFG = R0;
57 R0 = 0;
58
59 /* Clear Out All the data and pointer Registers*/
60 R1 = R0;
61 R2 = R0;
62 R3 = R0;
63 R4 = R0;
64 R5 = R0;
65 R6 = R0;
66
67 P0 = R0;
68 P1 = R0;
69 P2 = R0;
70 P3 = R0;
71 P4 = R0;
72 P5 = R0;
73
74 LC0 = r0;
75 LC1 = r0;
76 L0 = r0;
77 L1 = r0;
78 L2 = r0;
79 L3 = r0;
80
81 /* Clear Out All the DAG Registers*/
82 B0 = r0;
83 B1 = r0;
84 B2 = r0;
85 B3 = r0;
86
87 I0 = r0;
88 I1 = r0;
89 I2 = r0;
90 I3 = r0;
91
92 M0 = r0;
93 M1 = r0;
94 M2 = r0;
95 M3 = r0;
96
97 trace_buffer_init(p0,r0);
98 P0 = R1;
99 R0 = R1;
100
101 /* Turn off the icache */
102 p0.l = LO(IMEM_CONTROL);
103 p0.h = HI(IMEM_CONTROL);
104 R1 = [p0];
105 R0 = ~ENICPLB;
106 R0 = R0 & R1;
107 [p0] = R0;
108 SSYNC;
109
110 /* Turn off the dcache */
111 p0.l = LO(DMEM_CONTROL);
112 p0.h = HI(DMEM_CONTROL);
113 R1 = [p0];
114 R0 = ~ENDCPLB;
115 R0 = R0 & R1;
116 [p0] = R0;
117 SSYNC;
118
119 /* Initialize stack pointer */
120 SP.L = LO(INITIAL_STACK);
121 SP.H = HI(INITIAL_STACK);
122 FP = SP;
123 USP = SP;
124
125#ifdef CONFIG_EARLY_PRINTK
126 SP += -12;
127 call _init_early_exception_vectors;
128 SP += 12;
129#endif
130
131 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
132 call _bf53x_relocate_l1_mem;
133#ifdef CONFIG_BFIN_KERNEL_CLOCK
134 call _start_dma_code;
135#endif
136
137 /* This section keeps the processor in supervisor mode
138 * during kernel boot. Switches to user mode at end of boot.
139 * See page 3-9 of Hardware Reference manual for documentation.
140 */
141
142 /* EVT15 = _real_start */
143
144 p0.l = lo(EVT15);
145 p0.h = hi(EVT15);
146 p1.l = _real_start;
147 p1.h = _real_start;
148 [p0] = p1;
149 csync;
150
151 p0.l = lo(IMASK);
152 p0.h = hi(IMASK);
153 p1.l = IMASK_IVG15;
154 p1.h = 0x0;
155 [p0] = p1;
156 csync;
157
158 raise 15;
159 p0.l = .LWAIT_HERE;
160 p0.h = .LWAIT_HERE;
161 reti = p0;
162#if ANOMALY_05000281
163 nop;
164 nop;
165 nop;
166#endif
167 rti;
168
169.LWAIT_HERE:
170 jump .LWAIT_HERE;
171ENDPROC(__start)
172 45
173__FINIT 46__FINIT
174 47