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-rw-r--r--arch/blackfin/mach-bf538/Makefile1
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c42
-rw-r--r--arch/blackfin/mach-bf538/ext-gpio.c123
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h1261
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h7
-rw-r--r--arch/blackfin/mach-bf538/include/mach/portmux.h2
7 files changed, 190 insertions, 1252 deletions
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
index 8cd2719684d..c0be54f2cd2 100644
--- a/arch/blackfin/mach-bf538/Makefile
+++ b/arch/blackfin/mach-bf538/Makefile
@@ -3,3 +3,4 @@
3# 3#
4 4
5obj-y := ints-priority.o dma.o 5obj-y := ints-priority.o dma.o
6obj-$(CONFIG_GPIOLIB) += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 14af5c2088d..c296bb1ed50 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -151,6 +151,44 @@ static struct platform_device bfin_sir2_device = {
151#endif 151#endif
152#endif 152#endif
153 153
154#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
155unsigned short bfin_can_peripherals[] = {
156 P_CAN0_RX, P_CAN0_TX, 0
157};
158
159static struct resource bfin_can_resources[] = {
160 {
161 .start = 0xFFC02A00,
162 .end = 0xFFC02FFF,
163 .flags = IORESOURCE_MEM,
164 },
165 {
166 .start = IRQ_CAN_RX,
167 .end = IRQ_CAN_RX,
168 .flags = IORESOURCE_IRQ,
169 },
170 {
171 .start = IRQ_CAN_TX,
172 .end = IRQ_CAN_TX,
173 .flags = IORESOURCE_IRQ,
174 },
175 {
176 .start = IRQ_CAN_ERROR,
177 .end = IRQ_CAN_ERROR,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static struct platform_device bfin_can_device = {
183 .name = "bfin_can",
184 .num_resources = ARRAY_SIZE(bfin_can_resources),
185 .resource = bfin_can_resources,
186 .dev = {
187 .platform_data = &bfin_can_peripherals, /* Passed to driver */
188 },
189};
190#endif
191
154/* 192/*
155 * USB-LAN EzExtender board 193 * USB-LAN EzExtender board
156 * Driver needs to know address, irq and flag pin. 194 * Driver needs to know address, irq and flag pin.
@@ -610,6 +648,10 @@ static struct platform_device *cm_bf538_devices[] __initdata = {
610#endif 648#endif
611#endif 649#endif
612 650
651#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
652 &bfin_can_device,
653#endif
654
613#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 655#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
614 &smc91x_device, 656 &smc91x_device,
615#endif 657#endif
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
new file mode 100644
index 00000000000..180b1252679
--- /dev/null
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -0,0 +1,123 @@
1/*
2 * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
3 *
4 * Copyright 2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/err.h>
11#include <asm/blackfin.h>
12#include <asm/gpio.h>
13#include <asm/portmux.h>
14
15#define DEFINE_REG(reg, off) \
16static inline u16 read_##reg(void __iomem *port) \
17 { return bfin_read16(port + off); } \
18static inline void write_##reg(void __iomem *port, u16 v) \
19 { bfin_write16(port + off, v); }
20
21DEFINE_REG(PORTIO, 0x00)
22DEFINE_REG(PORTIO_CLEAR, 0x10)
23DEFINE_REG(PORTIO_SET, 0x20)
24DEFINE_REG(PORTIO_DIR, 0x40)
25DEFINE_REG(PORTIO_INEN, 0x50)
26
27static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
28{
29 switch (chip->base) {
30 default: /* not really needed, but keeps gcc happy */
31 case GPIO_PC0: return (void __iomem *)PORTCIO;
32 case GPIO_PD0: return (void __iomem *)PORTDIO;
33 case GPIO_PE0: return (void __iomem *)PORTEIO;
34 }
35}
36
37static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
38{
39 void __iomem *port = gpio_chip_to_mmr(chip);
40 return !!(read_PORTIO(port) & (1u << gpio));
41}
42
43static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
44{
45 void __iomem *port = gpio_chip_to_mmr(chip);
46 if (value)
47 write_PORTIO_SET(port, (1u << gpio));
48 else
49 write_PORTIO_CLEAR(port, (1u << gpio));
50}
51
52static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
53{
54 void __iomem *port = gpio_chip_to_mmr(chip);
55 write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
56 write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
57 return 0;
58}
59
60static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
61{
62 void __iomem *port = gpio_chip_to_mmr(chip);
63 write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
64 bf538_gpio_set_value(port, gpio, value);
65 write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
66 return 0;
67}
68
69static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
70{
71 return bfin_special_gpio_request(chip->base + gpio, chip->label);
72}
73
74static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
75{
76 return bfin_special_gpio_free(chip->base + gpio);
77}
78
79/* We don't set the irq fields as these banks cannot generate interrupts */
80
81static struct gpio_chip bf538_portc_chip = {
82 .label = "GPIO-PC",
83 .direction_input = bf538_gpio_direction_input,
84 .get = bf538_gpio_get_value,
85 .direction_output = bf538_gpio_direction_output,
86 .set = bf538_gpio_set_value,
87 .request = bf538_gpio_request,
88 .free = bf538_gpio_free,
89 .base = GPIO_PC0,
90 .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
91};
92
93static struct gpio_chip bf538_portd_chip = {
94 .label = "GPIO-PD",
95 .direction_input = bf538_gpio_direction_input,
96 .get = bf538_gpio_get_value,
97 .direction_output = bf538_gpio_direction_output,
98 .set = bf538_gpio_set_value,
99 .request = bf538_gpio_request,
100 .free = bf538_gpio_free,
101 .base = GPIO_PD0,
102 .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
103};
104
105static struct gpio_chip bf538_porte_chip = {
106 .label = "GPIO-PE",
107 .direction_input = bf538_gpio_direction_input,
108 .get = bf538_gpio_get_value,
109 .direction_output = bf538_gpio_direction_output,
110 .set = bf538_gpio_set_value,
111 .request = bf538_gpio_request,
112 .free = bf538_gpio_free,
113 .base = GPIO_PE0,
114 .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
115};
116
117static int __init bf538_extgpio_setup(void)
118{
119 return gpiochip_add(&bf538_portc_chip) |
120 gpiochip_add(&bf538_portd_chip) |
121 gpiochip_add(&bf538_porte_chip);
122}
123arch_initcall(bf538_extgpio_setup);
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 278e8942eef..08b5eabb1ed 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -37,10 +37,4 @@
37#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 37#define OFFSET_SCR 0x1C /* SCR Scratch Register */
38#define OFFSET_GCTL 0x24 /* Global Control Register */ 38#define OFFSET_GCTL 0x24 /* Global Control Register */
39 39
40/* PLL_DIV Masks */
41#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
42#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
43#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
44#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
45
46#endif 40#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 5f6c34dfd08..fac563e6f62 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -468,31 +468,31 @@
468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ 468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
469 469
470/* GPIO Port C Register Names */ 470/* GPIO Port C Register Names */
471#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */ 471#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
472#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */ 472#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
473#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */ 473#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
474#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */ 474#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
475#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */ 475#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
476#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ 476#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
477#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ 477#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
478 478
479/* GPIO Port D Register Names */ 479/* GPIO Port D Register Names */
480#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */ 480#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
481#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */ 481#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
482#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */ 482#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
483#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */ 483#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
484#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */ 484#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
485#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ 485#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
486#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ 486#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
487 487
488/* GPIO Port E Register Names */ 488/* GPIO Port E Register Names */
489#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */ 489#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
490#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */ 490#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
491#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */ 491#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
492#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */ 492#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
493#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */ 493#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
494#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ 494#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
495#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ 495#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
496 496
497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ 497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
498 498
@@ -1422,81 +1422,6 @@
1422/* System MMR Register Bits and Macros */ 1422/* System MMR Register Bits and Macros */
1423/******************************************************************************* */ 1423/******************************************************************************* */
1424 1424
1425/* ********************* PLL AND RESET MASKS ************************ */
1426/* PLL_CTL Masks */
1427#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
1428#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
1429#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
1430#define PLL_OFF 0x0002 /* Shut off PLL clocks */
1431
1432#define STOPCK 0x0008 /* Core Clock Off */
1433#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
1434#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
1435#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
1436#define BYPASS 0x0100 /* Bypass the PLL */
1437#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
1438
1439/* PLL_CTL Macros */
1440#ifdef _MISRA_RULES
1441#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1442#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
1443#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
1444#else
1445#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
1446#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
1447#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
1448#endif /* _MISRA_RULES */
1449
1450/* PLL_DIV Masks */
1451#define SSEL 0x000F /* System Select */
1452#define CSEL 0x0030 /* Core Select */
1453#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
1454#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
1455#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
1456#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
1457
1458#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
1459
1460/* PLL_DIV Macros */
1461#ifdef _MISRA_RULES
1462#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1463#else
1464#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
1465#endif /* _MISRA_RULES */
1466
1467/* PLL_STAT Masks */
1468#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
1469#define FULL_ON 0x0002 /* Processor In Full On Mode */
1470#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
1471#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
1472
1473/* VR_CTL Masks */
1474#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
1475#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
1476#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
1477#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
1478#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
1479
1480#define GAIN 0x000C /* Voltage Level Gain */
1481#define GAIN_5 0x0000 /* GAIN = 5 */
1482#define GAIN_10 0x0004 /* GAIN = 10 */
1483#define GAIN_20 0x0008 /* GAIN = 20 */
1484#define GAIN_50 0x000C /* GAIN = 50 */
1485
1486#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
1487#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
1488#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
1489#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
1490#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
1491#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
1492#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
1493#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
1494
1495#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1496#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1497#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
1498#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
1499
1500/* SWRST Mask */ 1425/* SWRST Mask */
1501#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1426#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
1502#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1427#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
@@ -1609,91 +1534,6 @@
1609#endif /* _MISRA_RULES */ 1534#endif /* _MISRA_RULES */
1610 1535
1611 1536
1612/* ********* WATCHDOG TIMER MASKS ******************** */
1613/* Watchdog Timer WDOG_CTL Register Masks */
1614#ifdef _MISRA_RULES
1615#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
1616#else
1617#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
1618#endif /* _MISRA_RULES */
1619#define WDEV_RESET 0x0000 /* generate reset event on roll over */
1620#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
1621#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
1622#define WDEV_NONE 0x0006 /* no event on roll over */
1623#define WDEN 0x0FF0 /* enable watchdog */
1624#define WDDIS 0x0AD0 /* disable watchdog */
1625#define WDRO 0x8000 /* watchdog rolled over latch */
1626
1627/* deprecated WDOG_CTL Register Masks for legacy code */
1628#define ICTL WDEV
1629#define ENABLE_RESET WDEV_RESET
1630#define WDOG_RESET WDEV_RESET
1631#define ENABLE_NMI WDEV_NMI
1632#define WDOG_NMI WDEV_NMI
1633#define ENABLE_GPI WDEV_GPI
1634#define WDOG_GPI WDEV_GPI
1635#define DISABLE_EVT WDEV_NONE
1636#define WDOG_NONE WDEV_NONE
1637
1638#define TMR_EN WDEN
1639#define WDOG_DISABLE WDDIS
1640#define TRO WDRO
1641
1642#define ICTL_P0 0x01
1643#define ICTL_P1 0x02
1644#define TRO_P 0x0F
1645
1646
1647/* *************** REAL TIME CLOCK MASKS **************************/
1648/* RTC_STAT and RTC_ALARM register */
1649#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
1650#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
1651#define RTHR 0x0001F000 /* Real-Time Clock Hours */
1652#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
1653
1654/* RTC_ICTL register */
1655#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
1656#define AIE 0x0002 /* Alarm Interrupt Enable */
1657#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
1658#define MIE 0x0008 /* Minutes Interrupt Enable */
1659#define HIE 0x0010 /* Hours Interrupt Enable */
1660#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
1661#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1662#define WCIE 0x8000 /* Write Complete Interrupt Enable */
1663
1664/* RTC_ISTAT register */
1665#define SWEF 0x0001 /* Stopwatch Event Flag */
1666#define AEF 0x0002 /* Alarm Event Flag */
1667#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
1668#define MEF 0x0008 /* Minutes Event Flag */
1669#define HEF 0x0010 /* Hours Event Flag */
1670#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
1671#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
1672#define WPS 0x4000 /* Write Pending Status (RO) */
1673#define WCOM 0x8000 /* Write Complete */
1674
1675/* RTC_FAST Mask (RTC_PREN Mask) */
1676#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
1677#define PREN 0x00000001
1678 /* ** Must be set after power-up for proper operation of RTC */
1679
1680/* Deprecated RTC_STAT and RTC_ALARM Masks */
1681#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
1682#define RTC_MIN RTMIN /* Real-Time Clock Minutes */
1683#define RTC_HR RTHR /* Real-Time Clock Hours */
1684#define RTC_DAY RTDAY /* Real-Time Clock Days */
1685
1686/* Deprecated RTC_ICTL/RTC_ISTAT Masks */
1687#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
1688#define ALARM AIE /* Alarm Interrupt Enable */
1689#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
1690#define MINUTE MIE /* Minutes Interrupt Enable */
1691#define HOUR HIE /* Hours Interrupt Enable */
1692#define DAY DIE /* 24 Hours (Days) Interrupt Enable */
1693#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
1694#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
1695
1696
1697/* ***************************** UART CONTROLLER MASKS ********************** */ 1537/* ***************************** UART CONTROLLER MASKS ********************** */
1698/* UARTx_LCR Register */ 1538/* UARTx_LCR Register */
1699#ifdef _MISRA_RULES 1539#ifdef _MISRA_RULES
@@ -1917,52 +1757,6 @@
1917 1757
1918 1758
1919/* ********** DMA CONTROLLER MASKS ***********************/ 1759/* ********** DMA CONTROLLER MASKS ***********************/
1920/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1921#define DMAEN 0x0001 /* Channel Enable */
1922#define WNR 0x0002 /* Channel Direction (W/R*) */
1923#define WDSIZE_8 0x0000 /* Word Size 8 bits */
1924#define WDSIZE_16 0x0004 /* Word Size 16 bits */
1925#define WDSIZE_32 0x0008 /* Word Size 32 bits */
1926#define DMA2D 0x0010 /* 2D/1D* Mode */
1927#define RESTART 0x0020 /* Restart */
1928#define DI_SEL 0x0040 /* Data Interrupt Select */
1929#define DI_EN 0x0080 /* Data Interrupt Enable */
1930#define NDSIZE 0x0900 /* Next Descriptor Size */
1931#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1932#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1933#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1934#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1935#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1936#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1937#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1938#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1939#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1940#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1941
1942#define DMAFLOW 0x7000 /* Flow Control */
1943#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1944#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1945#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1946#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1947#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1948
1949#define DMAEN_P 0x0 /* Channel Enable */
1950#define WNR_P 0x1 /* Channel Direction (W/R*) */
1951#define DMA2D_P 0x4 /* 2D/1D* Mode */
1952#define RESTART_P 0x5 /* Restart */
1953#define DI_SEL_P 0x6 /* Data Interrupt Select */
1954#define DI_EN_P 0x7 /* Data Interrupt Enable */
1955
1956/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1957#define DMA_DONE 0x0001 /* DMA Done Indicator */
1958#define DMA_ERR 0x0002 /* DMA Error Indicator */
1959#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
1960#define DMA_RUN 0x0008 /* DMA Running Indicator */
1961
1962#define DMA_DONE_P 0x0 /* DMA Done Indicator */
1963#define DMA_ERR_P 0x1 /* DMA Error Indicator */
1964#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
1965#define DMA_RUN_P 0x3 /* DMA Running Indicator */
1966 1760
1967/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1761/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1968 1762
@@ -2625,1019 +2419,6 @@
2625#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 2419#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
2626 2420
2627 2421
2628/********************************* MXVR MASKS ****************************************/
2629
2630/* MXVR_CONFIG Masks */
2631
2632#define MXVREN 0x00000001lu
2633#define MMSM 0x00000002lu
2634#define ACTIVE 0x00000004lu
2635#define SDELAY 0x00000008lu
2636#define NCMRXEN 0x00000010lu
2637#define RWRRXEN 0x00000020lu
2638#define MTXEN 0x00000040lu
2639#define MTXON 0x00000080lu /*legacy*/
2640#define MTXONB 0x00000080lu
2641#define EPARITY 0x00000100lu
2642#define MSB 0x00001E00lu
2643#define APRXEN 0x00002000lu
2644#define WAKEUP 0x00004000lu
2645#define LMECH 0x00008000lu
2646
2647#ifdef _MISRA_RULES
2648#define SET_MSB(x) (((x)&0xFu) << 0x9)
2649#else
2650#define SET_MSB(x) (((x)&0xF) << 0x9)
2651#endif /* _MISRA_RULES */
2652
2653
2654/* MXVR_PLL_CTL_0 Masks */
2655
2656#define MXTALCEN 0x00000001lu
2657#define MXTALFEN 0x00000002lu
2658#define MPLLMS 0x00000008lu
2659#define MXTALMUL 0x00000030lu
2660#define MPLLEN 0x00000040lu
2661#define MPLLEN0 0x00000040lu /* legacy */
2662#define MPLLEN1 0x00000080lu /* legacy */
2663#define MMCLKEN 0x00000100lu
2664#define MMCLKMUL 0x00001E00lu
2665#define MPLLRSTB 0x00002000lu
2666#define MPLLRSTB0 0x00002000lu /* legacy */
2667#define MPLLRSTB1 0x00004000lu /* legacy */
2668#define MBCLKEN 0x00010000lu
2669#define MBCLKDIV 0x001E0000lu
2670#define MPLLCDR 0x00200000lu
2671#define MPLLCDR0 0x00200000lu /* legacy */
2672#define MPLLCDR1 0x00400000lu /* legacy */
2673#define INVRX 0x00800000lu
2674#define MFSEN 0x01000000lu
2675#define MFSDIV 0x1E000000lu
2676#define MFSSEL 0x60000000lu
2677#define MFSSYNC 0x80000000lu
2678
2679#define MXTALMUL_256FS 0x00000000lu /* legacy */
2680#define MXTALMUL_384FS 0x00000010lu /* legacy */
2681#define MXTALMUL_512FS 0x00000020lu /* legacy */
2682#define MXTALMUL_1024FS 0x00000030lu
2683
2684#define MMCLKMUL_1024FS 0x00000000lu
2685#define MMCLKMUL_512FS 0x00000200lu
2686#define MMCLKMUL_256FS 0x00000400lu
2687#define MMCLKMUL_128FS 0x00000600lu
2688#define MMCLKMUL_64FS 0x00000800lu
2689#define MMCLKMUL_32FS 0x00000A00lu
2690#define MMCLKMUL_16FS 0x00000C00lu
2691#define MMCLKMUL_8FS 0x00000E00lu
2692#define MMCLKMUL_4FS 0x00001000lu
2693#define MMCLKMUL_2FS 0x00001200lu
2694#define MMCLKMUL_1FS 0x00001400lu
2695#define MMCLKMUL_1536FS 0x00001A00lu
2696#define MMCLKMUL_768FS 0x00001C00lu
2697#define MMCLKMUL_384FS 0x00001E00lu
2698
2699#define MBCLKDIV_DIV2 0x00020000lu
2700#define MBCLKDIV_DIV4 0x00040000lu
2701#define MBCLKDIV_DIV8 0x00060000lu
2702#define MBCLKDIV_DIV16 0x00080000lu
2703#define MBCLKDIV_DIV32 0x000A0000lu
2704#define MBCLKDIV_DIV64 0x000C0000lu
2705#define MBCLKDIV_DIV128 0x000E0000lu
2706#define MBCLKDIV_DIV256 0x00100000lu
2707#define MBCLKDIV_DIV512 0x00120000lu
2708#define MBCLKDIV_DIV1024 0x00140000lu
2709
2710#define MFSDIV_DIV2 0x02000000lu
2711#define MFSDIV_DIV4 0x04000000lu
2712#define MFSDIV_DIV8 0x06000000lu
2713#define MFSDIV_DIV16 0x08000000lu
2714#define MFSDIV_DIV32 0x0A000000lu
2715#define MFSDIV_DIV64 0x0C000000lu
2716#define MFSDIV_DIV128 0x0E000000lu
2717#define MFSDIV_DIV256 0x10000000lu
2718#define MFSDIV_DIV512 0x12000000lu
2719#define MFSDIV_DIV1024 0x14000000lu
2720
2721#define MFSSEL_CLOCK 0x00000000lu
2722#define MFSSEL_PULSE_HI 0x20000000lu
2723#define MFSSEL_PULSE_LO 0x40000000lu
2724
2725
2726/* MXVR_PLL_CTL_1 Masks */
2727
2728#define MSTO 0x00000001lu
2729#define MSTO0 0x00000001lu /* legacy */
2730#define MHOGGD 0x00000004lu
2731#define MHOGGD0 0x00000004lu /* legacy */
2732#define MHOGGD1 0x00000008lu /* legacy */
2733#define MSHAPEREN 0x00000010lu
2734#define MSHAPEREN0 0x00000010lu /* legacy */
2735#define MSHAPEREN1 0x00000020lu /* legacy */
2736#define MPLLCNTEN 0x00008000lu
2737#define MPLLCNT 0xFFFF0000lu
2738
2739#ifdef _MISRA_RULES
2740#define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10)
2741#else
2742#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10)
2743#endif /* _MISRA_RULES */
2744
2745
2746/* MXVR_PLL_CTL_2 Masks */
2747
2748#define MSHAPERSEL 0x00000007lu
2749#define MCPSEL 0x000000E0lu
2750
2751/* MXVR_INT_STAT_0 Masks */
2752
2753#define NI2A 0x00000001lu
2754#define NA2I 0x00000002lu
2755#define SBU2L 0x00000004lu
2756#define SBL2U 0x00000008lu
2757#define PRU 0x00000010lu
2758#define MPRU 0x00000020lu
2759#define DRU 0x00000040lu
2760#define MDRU 0x00000080lu
2761#define SBU 0x00000100lu
2762#define ATU 0x00000200lu
2763#define FCZ0 0x00000400lu
2764#define FCZ1 0x00000800lu
2765#define PERR 0x00001000lu
2766#define MH2L 0x00002000lu
2767#define ML2H 0x00004000lu
2768#define WUP 0x00008000lu
2769#define FU2L 0x00010000lu
2770#define FL2U 0x00020000lu
2771#define BU2L 0x00040000lu
2772#define BL2U 0x00080000lu
2773#define PCZ 0x00400000lu
2774#define FERR 0x00800000lu
2775#define CMR 0x01000000lu
2776#define CMROF 0x02000000lu
2777#define CMTS 0x04000000lu
2778#define CMTC 0x08000000lu
2779#define RWRC 0x10000000lu
2780#define BCZ 0x20000000lu
2781#define BMERR 0x40000000lu
2782#define DERR 0x80000000lu
2783
2784
2785/* MXVR_INT_EN_0 Masks */
2786
2787#define NI2AEN NI2A
2788#define NA2IEN NA2I
2789#define SBU2LEN SBU2L
2790#define SBL2UEN SBL2U
2791#define PRUEN PRU
2792#define MPRUEN MPRU
2793#define DRUEN DRU
2794#define MDRUEN MDRU
2795#define SBUEN SBU
2796#define ATUEN ATU
2797#define FCZ0EN FCZ0
2798#define FCZ1EN FCZ1
2799#define PERREN PERR
2800#define MH2LEN MH2L
2801#define ML2HEN ML2H
2802#define WUPEN WUP
2803#define FU2LEN FU2L
2804#define FL2UEN FL2U
2805#define BU2LEN BU2L
2806#define BL2UEN BL2U
2807#define PCZEN PCZ
2808#define FERREN FERR
2809#define CMREN CMR
2810#define CMROFEN CMROF
2811#define CMTSEN CMTS
2812#define CMTCEN CMTC
2813#define RWRCEN RWRC
2814#define BCZEN BCZ
2815#define BMERREN BMERR
2816#define DERREN DERR
2817
2818
2819/* MXVR_INT_STAT_1 Masks */
2820
2821#define APR 0x00000004lu
2822#define APROF 0x00000008lu
2823#define APTS 0x00000040lu
2824#define APTC 0x00000080lu
2825#define APRCE 0x00000400lu
2826#define APRPE 0x00000800lu
2827
2828#define HDONE0 0x00000001lu
2829#define DONE0 0x00000002lu
2830#define HDONE1 0x00000010lu
2831#define DONE1 0x00000020lu
2832#define HDONE2 0x00000100lu
2833#define DONE2 0x00000200lu
2834#define HDONE3 0x00001000lu
2835#define DONE3 0x00002000lu
2836#define HDONE4 0x00010000lu
2837#define DONE4 0x00020000lu
2838#define HDONE5 0x00100000lu
2839#define DONE5 0x00200000lu
2840#define HDONE6 0x01000000lu
2841#define DONE6 0x02000000lu
2842#define HDONE7 0x10000000lu
2843#define DONE7 0x20000000lu
2844
2845#define DONEX(x) (0x00000002 << (4 * (x)))
2846#define HDONEX(x) (0x00000001 << (4 * (x)))
2847
2848
2849/* MXVR_INT_EN_1 Masks */
2850
2851#define APREN APR
2852#define APROFEN APROF
2853#define APTSEN APTS
2854#define APTCEN APTC
2855#define APRCEEN APRCE
2856#define APRPEEN APRPE
2857
2858#define HDONEEN0 HDONE0
2859#define DONEEN0 DONE0
2860#define HDONEEN1 HDONE1
2861#define DONEEN1 DONE1
2862#define HDONEEN2 HDONE2
2863#define DONEEN2 DONE2
2864#define HDONEEN3 HDONE3
2865#define DONEEN3 DONE3
2866#define HDONEEN4 HDONE4
2867#define DONEEN4 DONE4
2868#define HDONEEN5 HDONE5
2869#define DONEEN5 DONE5
2870#define HDONEEN6 HDONE6
2871#define DONEEN6 DONE6
2872#define HDONEEN7 HDONE7
2873#define DONEEN7 DONE7
2874
2875#define DONEENX(x) (0x00000002 << (4 * (x)))
2876#define HDONEENX(x) (0x00000001 << (4 * (x)))
2877
2878
2879/* MXVR_STATE_0 Masks */
2880
2881#define NACT 0x00000001lu
2882#define SBLOCK 0x00000002lu
2883#define PFDLOCK 0x00000004lu
2884#define PFDLOCK0 0x00000004lu /* legacy */
2885#define PDD 0x00000008lu
2886#define PDD0 0x00000008lu /* legacy */
2887#define PVCO 0x00000010lu
2888#define PVCO0 0x00000010lu /* legacy */
2889#define PFDLOCK1 0x00000020lu /* legacy */
2890#define PDD1 0x00000040lu /* legacy */
2891#define PVCO1 0x00000080lu /* legacy */
2892#define APBSY 0x00000100lu
2893#define APARB 0x00000200lu
2894#define APTX 0x00000400lu
2895#define APRX 0x00000800lu
2896#define CMBSY 0x00001000lu
2897#define CMARB 0x00002000lu
2898#define CMTX 0x00004000lu
2899#define CMRX 0x00008000lu
2900#define MRXONB 0x00010000lu
2901#define RGSIP 0x00020000lu
2902#define DALIP 0x00040000lu
2903#define ALIP 0x00080000lu
2904#define RRDIP 0x00100000lu
2905#define RWRIP 0x00200000lu
2906#define FLOCK 0x00400000lu
2907#define BLOCK 0x00800000lu
2908#define RSB 0x0F000000lu
2909#define DERRNUM 0xF0000000lu
2910
2911
2912/* MXVR_STATE_1 Masks */
2913
2914#define STXNUMB 0x0000000Flu
2915#define SRXNUMB 0x000000F0lu
2916#define APCONT 0x00000100lu
2917#define DMAACTIVEX 0x00FF0000lu
2918#define DMAACTIVE0 0x00010000lu
2919#define DMAACTIVE1 0x00020000lu
2920#define DMAACTIVE2 0x00040000lu
2921#define DMAACTIVE3 0x00080000lu
2922#define DMAACTIVE4 0x00100000lu
2923#define DMAACTIVE5 0x00200000lu
2924#define DMAACTIVE6 0x00400000lu
2925#define DMAACTIVE7 0x00800000lu
2926#define DMAPMENX 0xFF000000lu
2927#define DMAPMEN0 0x01000000lu
2928#define DMAPMEN1 0x02000000lu
2929#define DMAPMEN2 0x04000000lu
2930#define DMAPMEN3 0x08000000lu
2931#define DMAPMEN4 0x10000000lu
2932#define DMAPMEN5 0x20000000lu
2933#define DMAPMEN6 0x40000000lu
2934#define DMAPMEN7 0x80000000lu
2935
2936
2937/* MXVR_POSITION Masks */
2938
2939#define PVALID 0x8000
2940#define POSITION 0x003F
2941
2942
2943/* MXVR_MAX_POSITION Masks */
2944
2945#define MPVALID 0x8000
2946#define MPOSITION 0x003F
2947
2948
2949/* MXVR_DELAY Masks */
2950
2951#define DVALID 0x8000
2952#define DELAY 0x003F
2953
2954
2955/* MXVR_MAX_DELAY Masks */
2956
2957#define MDVALID 0x8000
2958#define MDELAY 0x003F
2959
2960
2961/* MXVR_LADDR Masks */
2962
2963#define LVALID 0x80000000lu
2964#define LADDR 0x0000FFFFlu
2965
2966
2967/* MXVR_GADDR Masks */
2968
2969#define GVALID 0x8000
2970#define GADDRL 0x00FF
2971
2972
2973/* MXVR_AADDR Masks */
2974
2975#define AVALID 0x80000000lu
2976#define AADDR 0x0000FFFFlu
2977
2978
2979/* MXVR_ALLOC_0 Masks */
2980
2981#define CIU0 0x00000080lu
2982#define CIU1 0x00008000lu
2983#define CIU2 0x00800000lu
2984#define CIU3 0x80000000lu
2985
2986#define CL0 0x0000007Flu
2987#define CL1 0x00007F00lu
2988#define CL2 0x007F0000lu
2989#define CL3 0x7F000000lu
2990
2991
2992/* MXVR_ALLOC_1 Masks */
2993
2994#define CIU4 0x00000080lu
2995#define CIU5 0x00008000lu
2996#define CIU6 0x00800000lu
2997#define CIU7 0x80000000lu
2998
2999#define CL4 0x0000007Flu
3000#define CL5 0x00007F00lu
3001#define CL6 0x007F0000lu
3002#define CL7 0x7F000000lu
3003
3004
3005/* MXVR_ALLOC_2 Masks */
3006
3007#define CIU8 0x00000080lu
3008#define CIU9 0x00008000lu
3009#define CIU10 0x00800000lu
3010#define CIU11 0x80000000lu
3011
3012#define CL8 0x0000007Flu
3013#define CL9 0x00007F00lu
3014#define CL10 0x007F0000lu
3015#define CL11 0x7F000000lu
3016
3017
3018/* MXVR_ALLOC_3 Masks */
3019
3020#define CIU12 0x00000080lu
3021#define CIU13 0x00008000lu
3022#define CIU14 0x00800000lu
3023#define CIU15 0x80000000lu
3024
3025#define CL12 0x0000007Flu
3026#define CL13 0x00007F00lu
3027#define CL14 0x007F0000lu
3028#define CL15 0x7F000000lu
3029
3030
3031/* MXVR_ALLOC_4 Masks */
3032
3033#define CIU16 0x00000080lu
3034#define CIU17 0x00008000lu
3035#define CIU18 0x00800000lu
3036#define CIU19 0x80000000lu
3037
3038#define CL16 0x0000007Flu
3039#define CL17 0x00007F00lu
3040#define CL18 0x007F0000lu
3041#define CL19 0x7F000000lu
3042
3043
3044/* MXVR_ALLOC_5 Masks */
3045
3046#define CIU20 0x00000080lu
3047#define CIU21 0x00008000lu
3048#define CIU22 0x00800000lu
3049#define CIU23 0x80000000lu
3050
3051#define CL20 0x0000007Flu
3052#define CL21 0x00007F00lu
3053#define CL22 0x007F0000lu
3054#define CL23 0x7F000000lu
3055
3056
3057/* MXVR_ALLOC_6 Masks */
3058
3059#define CIU24 0x00000080lu
3060#define CIU25 0x00008000lu
3061#define CIU26 0x00800000lu
3062#define CIU27 0x80000000lu
3063
3064#define CL24 0x0000007Flu
3065#define CL25 0x00007F00lu
3066#define CL26 0x007F0000lu
3067#define CL27 0x7F000000lu
3068
3069
3070/* MXVR_ALLOC_7 Masks */
3071
3072#define CIU28 0x00000080lu
3073#define CIU29 0x00008000lu
3074#define CIU30 0x00800000lu
3075#define CIU31 0x80000000lu
3076
3077#define CL28 0x0000007Flu
3078#define CL29 0x00007F00lu
3079#define CL30 0x007F0000lu
3080#define CL31 0x7F000000lu
3081
3082
3083/* MXVR_ALLOC_8 Masks */
3084
3085#define CIU32 0x00000080lu
3086#define CIU33 0x00008000lu
3087#define CIU34 0x00800000lu
3088#define CIU35 0x80000000lu
3089
3090#define CL32 0x0000007Flu
3091#define CL33 0x00007F00lu
3092#define CL34 0x007F0000lu
3093#define CL35 0x7F000000lu
3094
3095
3096/* MXVR_ALLOC_9 Masks */
3097
3098#define CIU36 0x00000080lu
3099#define CIU37 0x00008000lu
3100#define CIU38 0x00800000lu
3101#define CIU39 0x80000000lu
3102
3103#define CL36 0x0000007Flu
3104#define CL37 0x00007F00lu
3105#define CL38 0x007F0000lu
3106#define CL39 0x7F000000lu
3107
3108
3109/* MXVR_ALLOC_10 Masks */
3110
3111#define CIU40 0x00000080lu
3112#define CIU41 0x00008000lu
3113#define CIU42 0x00800000lu
3114#define CIU43 0x80000000lu
3115
3116#define CL40 0x0000007Flu
3117#define CL41 0x00007F00lu
3118#define CL42 0x007F0000lu
3119#define CL43 0x7F000000lu
3120
3121
3122/* MXVR_ALLOC_11 Masks */
3123
3124#define CIU44 0x00000080lu
3125#define CIU45 0x00008000lu
3126#define CIU46 0x00800000lu
3127#define CIU47 0x80000000lu
3128
3129#define CL44 0x0000007Flu
3130#define CL45 0x00007F00lu
3131#define CL46 0x007F0000lu
3132#define CL47 0x7F000000lu
3133
3134
3135/* MXVR_ALLOC_12 Masks */
3136
3137#define CIU48 0x00000080lu
3138#define CIU49 0x00008000lu
3139#define CIU50 0x00800000lu
3140#define CIU51 0x80000000lu
3141
3142#define CL48 0x0000007Flu
3143#define CL49 0x00007F00lu
3144#define CL50 0x007F0000lu
3145#define CL51 0x7F000000lu
3146
3147
3148/* MXVR_ALLOC_13 Masks */
3149
3150#define CIU52 0x00000080lu
3151#define CIU53 0x00008000lu
3152#define CIU54 0x00800000lu
3153#define CIU55 0x80000000lu
3154
3155#define CL52 0x0000007Flu
3156#define CL53 0x00007F00lu
3157#define CL54 0x007F0000lu
3158#define CL55 0x7F000000lu
3159
3160
3161/* MXVR_ALLOC_14 Masks */
3162
3163#define CIU56 0x00000080lu
3164#define CIU57 0x00008000lu
3165#define CIU58 0x00800000lu
3166#define CIU59 0x80000000lu
3167
3168#define CL56 0x0000007Flu
3169#define CL57 0x00007F00lu
3170#define CL58 0x007F0000lu
3171#define CL59 0x7F000000lu
3172
3173
3174/* MXVR_SYNC_LCHAN_0 Masks */
3175
3176#define LCHANPC0 0x0000000Flu
3177#define LCHANPC1 0x000000F0lu
3178#define LCHANPC2 0x00000F00lu
3179#define LCHANPC3 0x0000F000lu
3180#define LCHANPC4 0x000F0000lu
3181#define LCHANPC5 0x00F00000lu
3182#define LCHANPC6 0x0F000000lu
3183#define LCHANPC7 0xF0000000lu
3184
3185
3186/* MXVR_SYNC_LCHAN_1 Masks */
3187
3188#define LCHANPC8 0x0000000Flu
3189#define LCHANPC9 0x000000F0lu
3190#define LCHANPC10 0x00000F00lu
3191#define LCHANPC11 0x0000F000lu
3192#define LCHANPC12 0x000F0000lu
3193#define LCHANPC13 0x00F00000lu
3194#define LCHANPC14 0x0F000000lu
3195#define LCHANPC15 0xF0000000lu
3196
3197
3198/* MXVR_SYNC_LCHAN_2 Masks */
3199
3200#define LCHANPC16 0x0000000Flu
3201#define LCHANPC17 0x000000F0lu
3202#define LCHANPC18 0x00000F00lu
3203#define LCHANPC19 0x0000F000lu
3204#define LCHANPC20 0x000F0000lu
3205#define LCHANPC21 0x00F00000lu
3206#define LCHANPC22 0x0F000000lu
3207#define LCHANPC23 0xF0000000lu
3208
3209
3210/* MXVR_SYNC_LCHAN_3 Masks */
3211
3212#define LCHANPC24 0x0000000Flu
3213#define LCHANPC25 0x000000F0lu
3214#define LCHANPC26 0x00000F00lu
3215#define LCHANPC27 0x0000F000lu
3216#define LCHANPC28 0x000F0000lu
3217#define LCHANPC29 0x00F00000lu
3218#define LCHANPC30 0x0F000000lu
3219#define LCHANPC31 0xF0000000lu
3220
3221
3222/* MXVR_SYNC_LCHAN_4 Masks */
3223
3224#define LCHANPC32 0x0000000Flu
3225#define LCHANPC33 0x000000F0lu
3226#define LCHANPC34 0x00000F00lu
3227#define LCHANPC35 0x0000F000lu
3228#define LCHANPC36 0x000F0000lu
3229#define LCHANPC37 0x00F00000lu
3230#define LCHANPC38 0x0F000000lu
3231#define LCHANPC39 0xF0000000lu
3232
3233
3234/* MXVR_SYNC_LCHAN_5 Masks */
3235
3236#define LCHANPC40 0x0000000Flu
3237#define LCHANPC41 0x000000F0lu
3238#define LCHANPC42 0x00000F00lu
3239#define LCHANPC43 0x0000F000lu
3240#define LCHANPC44 0x000F0000lu
3241#define LCHANPC45 0x00F00000lu
3242#define LCHANPC46 0x0F000000lu
3243#define LCHANPC47 0xF0000000lu
3244
3245
3246/* MXVR_SYNC_LCHAN_6 Masks */
3247
3248#define LCHANPC48 0x0000000Flu
3249#define LCHANPC49 0x000000F0lu
3250#define LCHANPC50 0x00000F00lu
3251#define LCHANPC51 0x0000F000lu
3252#define LCHANPC52 0x000F0000lu
3253#define LCHANPC53 0x00F00000lu
3254#define LCHANPC54 0x0F000000lu
3255#define LCHANPC55 0xF0000000lu
3256
3257
3258/* MXVR_SYNC_LCHAN_7 Masks */
3259
3260#define LCHANPC56 0x0000000Flu
3261#define LCHANPC57 0x000000F0lu
3262#define LCHANPC58 0x00000F00lu
3263#define LCHANPC59 0x0000F000lu
3264
3265
3266/* MXVR_DMAx_CONFIG Masks */
3267
3268#define MDMAEN 0x00000001lu
3269#define DD 0x00000002lu
3270#define LCHAN 0x000003C0lu
3271#define BITSWAPEN 0x00000400lu
3272#define BYSWAPEN 0x00000800lu
3273#define MFLOW 0x00007000lu
3274#define FIXEDPM 0x00080000lu
3275#define STARTPAT 0x00300000lu
3276#define STOPPAT 0x00C00000lu
3277#define COUNTPOS 0x1C000000lu
3278
3279#define DD_TX 0x00000000lu
3280#define DD_RX 0x00000002lu
3281
3282#define LCHAN_0 0x00000000lu
3283#define LCHAN_1 0x00000040lu
3284#define LCHAN_2 0x00000080lu
3285#define LCHAN_3 0x000000C0lu
3286#define LCHAN_4 0x00000100lu
3287#define LCHAN_5 0x00000140lu
3288#define LCHAN_6 0x00000180lu
3289#define LCHAN_7 0x000001C0lu
3290
3291#define MFLOW_STOP 0x00000000lu
3292#define MFLOW_AUTO 0x00001000lu
3293#define MFLOW_PVC 0x00002000lu
3294#define MFLOW_PSS 0x00003000lu
3295#define MFLOW_PFC 0x00004000lu
3296
3297#define STARTPAT_0 0x00000000lu
3298#define STARTPAT_1 0x00100000lu
3299
3300#define STOPPAT_0 0x00000000lu
3301#define STOPPAT_1 0x00400000lu
3302
3303#define COUNTPOS_0 0x00000000lu
3304#define COUNTPOS_1 0x04000000lu
3305#define COUNTPOS_2 0x08000000lu
3306#define COUNTPOS_3 0x0C000000lu
3307#define COUNTPOS_4 0x10000000lu
3308#define COUNTPOS_5 0x14000000lu
3309#define COUNTPOS_6 0x18000000lu
3310#define COUNTPOS_7 0x1C000000lu
3311
3312
3313/* MXVR_AP_CTL Masks */
3314
3315#define STARTAP 0x00000001lu
3316#define CANCELAP 0x00000002lu
3317#define RESETAP 0x00000004lu
3318#define APRBE0 0x00004000lu
3319#define APRBE1 0x00008000lu
3320#define APRBEX 0x0000C000lu
3321
3322
3323/* MXVR_CM_CTL Masks */
3324
3325#define STARTCM 0x00000001lu
3326#define CANCELCM 0x00000002lu
3327#define CMRBEX 0xFFFF0000lu
3328#define CMRBE0 0x00010000lu
3329#define CMRBE1 0x00020000lu
3330#define CMRBE2 0x00040000lu
3331#define CMRBE3 0x00080000lu
3332#define CMRBE4 0x00100000lu
3333#define CMRBE5 0x00200000lu
3334#define CMRBE6 0x00400000lu
3335#define CMRBE7 0x00800000lu
3336#define CMRBE8 0x01000000lu
3337#define CMRBE9 0x02000000lu
3338#define CMRBE10 0x04000000lu
3339#define CMRBE11 0x08000000lu
3340#define CMRBE12 0x10000000lu
3341#define CMRBE13 0x20000000lu
3342#define CMRBE14 0x40000000lu
3343#define CMRBE15 0x80000000lu
3344
3345
3346/* MXVR_PAT_DATA_x Masks */
3347
3348#define MATCH_DATA_0 0x000000FFlu
3349#define MATCH_DATA_1 0x0000FF00lu
3350#define MATCH_DATA_2 0x00FF0000lu
3351#define MATCH_DATA_3 0xFF000000lu
3352
3353
3354
3355/* MXVR_PAT_EN_x Masks */
3356
3357#define MATCH_EN_0_0 0x00000001lu
3358#define MATCH_EN_0_1 0x00000002lu
3359#define MATCH_EN_0_2 0x00000004lu
3360#define MATCH_EN_0_3 0x00000008lu
3361#define MATCH_EN_0_4 0x00000010lu
3362#define MATCH_EN_0_5 0x00000020lu
3363#define MATCH_EN_0_6 0x00000040lu
3364#define MATCH_EN_0_7 0x00000080lu
3365
3366#define MATCH_EN_1_0 0x00000100lu
3367#define MATCH_EN_1_1 0x00000200lu
3368#define MATCH_EN_1_2 0x00000400lu
3369#define MATCH_EN_1_3 0x00000800lu
3370#define MATCH_EN_1_4 0x00001000lu
3371#define MATCH_EN_1_5 0x00002000lu
3372#define MATCH_EN_1_6 0x00004000lu
3373#define MATCH_EN_1_7 0x00008000lu
3374
3375#define MATCH_EN_2_0 0x00010000lu
3376#define MATCH_EN_2_1 0x00020000lu
3377#define MATCH_EN_2_2 0x00040000lu
3378#define MATCH_EN_2_3 0x00080000lu
3379#define MATCH_EN_2_4 0x00100000lu
3380#define MATCH_EN_2_5 0x00200000lu
3381#define MATCH_EN_2_6 0x00400000lu
3382#define MATCH_EN_2_7 0x00800000lu
3383
3384#define MATCH_EN_3_0 0x01000000lu
3385#define MATCH_EN_3_1 0x02000000lu
3386#define MATCH_EN_3_2 0x04000000lu
3387#define MATCH_EN_3_3 0x08000000lu
3388#define MATCH_EN_3_4 0x10000000lu
3389#define MATCH_EN_3_5 0x20000000lu
3390#define MATCH_EN_3_6 0x40000000lu
3391#define MATCH_EN_3_7 0x80000000lu
3392
3393
3394/* MXVR_ROUTING_0 Masks */
3395
3396#define MUTE_CH0 0x00000080lu
3397#define MUTE_CH1 0x00008000lu
3398#define MUTE_CH2 0x00800000lu
3399#define MUTE_CH3 0x80000000lu
3400
3401#define TX_CH0 0x0000007Flu
3402#define TX_CH1 0x00007F00lu
3403#define TX_CH2 0x007F0000lu
3404#define TX_CH3 0x7F000000lu
3405
3406
3407/* MXVR_ROUTING_1 Masks */
3408
3409#define MUTE_CH4 0x00000080lu
3410#define MUTE_CH5 0x00008000lu
3411#define MUTE_CH6 0x00800000lu
3412#define MUTE_CH7 0x80000000lu
3413
3414#define TX_CH4 0x0000007Flu
3415#define TX_CH5 0x00007F00lu
3416#define TX_CH6 0x007F0000lu
3417#define TX_CH7 0x7F000000lu
3418
3419
3420/* MXVR_ROUTING_2 Masks */
3421
3422#define MUTE_CH8 0x00000080lu
3423#define MUTE_CH9 0x00008000lu
3424#define MUTE_CH10 0x00800000lu
3425#define MUTE_CH11 0x80000000lu
3426
3427#define TX_CH8 0x0000007Flu
3428#define TX_CH9 0x00007F00lu
3429#define TX_CH10 0x007F0000lu
3430#define TX_CH11 0x7F000000lu
3431
3432/* MXVR_ROUTING_3 Masks */
3433
3434#define MUTE_CH12 0x00000080lu
3435#define MUTE_CH13 0x00008000lu
3436#define MUTE_CH14 0x00800000lu
3437#define MUTE_CH15 0x80000000lu
3438
3439#define TX_CH12 0x0000007Flu
3440#define TX_CH13 0x00007F00lu
3441#define TX_CH14 0x007F0000lu
3442#define TX_CH15 0x7F000000lu
3443
3444
3445/* MXVR_ROUTING_4 Masks */
3446
3447#define MUTE_CH16 0x00000080lu
3448#define MUTE_CH17 0x00008000lu
3449#define MUTE_CH18 0x00800000lu
3450#define MUTE_CH19 0x80000000lu
3451
3452#define TX_CH16 0x0000007Flu
3453#define TX_CH17 0x00007F00lu
3454#define TX_CH18 0x007F0000lu
3455#define TX_CH19 0x7F000000lu
3456
3457
3458/* MXVR_ROUTING_5 Masks */
3459
3460#define MUTE_CH20 0x00000080lu
3461#define MUTE_CH21 0x00008000lu
3462#define MUTE_CH22 0x00800000lu
3463#define MUTE_CH23 0x80000000lu
3464
3465#define TX_CH20 0x0000007Flu
3466#define TX_CH21 0x00007F00lu
3467#define TX_CH22 0x007F0000lu
3468#define TX_CH23 0x7F000000lu
3469
3470
3471/* MXVR_ROUTING_6 Masks */
3472
3473#define MUTE_CH24 0x00000080lu
3474#define MUTE_CH25 0x00008000lu
3475#define MUTE_CH26 0x00800000lu
3476#define MUTE_CH27 0x80000000lu
3477
3478#define TX_CH24 0x0000007Flu
3479#define TX_CH25 0x00007F00lu
3480#define TX_CH26 0x007F0000lu
3481#define TX_CH27 0x7F000000lu
3482
3483
3484/* MXVR_ROUTING_7 Masks */
3485
3486#define MUTE_CH28 0x00000080lu
3487#define MUTE_CH29 0x00008000lu
3488#define MUTE_CH30 0x00800000lu
3489#define MUTE_CH31 0x80000000lu
3490
3491#define TX_CH28 0x0000007Flu
3492#define TX_CH29 0x00007F00lu
3493#define TX_CH30 0x007F0000lu
3494#define TX_CH31 0x7F000000lu
3495
3496
3497/* MXVR_ROUTING_8 Masks */
3498
3499#define MUTE_CH32 0x00000080lu
3500#define MUTE_CH33 0x00008000lu
3501#define MUTE_CH34 0x00800000lu
3502#define MUTE_CH35 0x80000000lu
3503
3504#define TX_CH32 0x0000007Flu
3505#define TX_CH33 0x00007F00lu
3506#define TX_CH34 0x007F0000lu
3507#define TX_CH35 0x7F000000lu
3508
3509
3510/* MXVR_ROUTING_9 Masks */
3511
3512#define MUTE_CH36 0x00000080lu
3513#define MUTE_CH37 0x00008000lu
3514#define MUTE_CH38 0x00800000lu
3515#define MUTE_CH39 0x80000000lu
3516
3517#define TX_CH36 0x0000007Flu
3518#define TX_CH37 0x00007F00lu
3519#define TX_CH38 0x007F0000lu
3520#define TX_CH39 0x7F000000lu
3521
3522
3523/* MXVR_ROUTING_10 Masks */
3524
3525#define MUTE_CH40 0x00000080lu
3526#define MUTE_CH41 0x00008000lu
3527#define MUTE_CH42 0x00800000lu
3528#define MUTE_CH43 0x80000000lu
3529
3530#define TX_CH40 0x0000007Flu
3531#define TX_CH41 0x00007F00lu
3532#define TX_CH42 0x007F0000lu
3533#define TX_CH43 0x7F000000lu
3534
3535
3536/* MXVR_ROUTING_11 Masks */
3537
3538#define MUTE_CH44 0x00000080lu
3539#define MUTE_CH45 0x00008000lu
3540#define MUTE_CH46 0x00800000lu
3541#define MUTE_CH47 0x80000000lu
3542
3543#define TX_CH44 0x0000007Flu
3544#define TX_CH45 0x00007F00lu
3545#define TX_CH46 0x007F0000lu
3546#define TX_CH47 0x7F000000lu
3547
3548
3549/* MXVR_ROUTING_12 Masks */
3550
3551#define MUTE_CH48 0x00000080lu
3552#define MUTE_CH49 0x00008000lu
3553#define MUTE_CH50 0x00800000lu
3554#define MUTE_CH51 0x80000000lu
3555
3556#define TX_CH48 0x0000007Flu
3557#define TX_CH49 0x00007F00lu
3558#define TX_CH50 0x007F0000lu
3559#define TX_CH51 0x7F000000lu
3560
3561
3562/* MXVR_ROUTING_13 Masks */
3563
3564#define MUTE_CH52 0x00000080lu
3565#define MUTE_CH53 0x00008000lu
3566#define MUTE_CH54 0x00800000lu
3567#define MUTE_CH55 0x80000000lu
3568
3569#define TX_CH52 0x0000007Flu
3570#define TX_CH53 0x00007F00lu
3571#define TX_CH54 0x007F0000lu
3572#define TX_CH55 0x7F000000lu
3573
3574
3575/* MXVR_ROUTING_14 Masks */
3576
3577#define MUTE_CH56 0x00000080lu
3578#define MUTE_CH57 0x00008000lu
3579#define MUTE_CH58 0x00800000lu
3580#define MUTE_CH59 0x80000000lu
3581
3582#define TX_CH56 0x0000007Flu
3583#define TX_CH57 0x00007F00lu
3584#define TX_CH58 0x007F0000lu
3585#define TX_CH59 0x7F000000lu
3586
3587
3588/* Control Message Receive Buffer (CMRB) Address Offsets */
3589
3590#define CMRB_STRIDE 0x00000016lu
3591
3592#define CMRB_DST_OFFSET 0x00000000lu
3593#define CMRB_SRC_OFFSET 0x00000002lu
3594#define CMRB_DATA_OFFSET 0x00000005lu
3595
3596
3597/* Control Message Transmit Buffer (CMTB) Address Offsets */
3598
3599#define CMTB_PRIO_OFFSET 0x00000000lu
3600#define CMTB_DST_OFFSET 0x00000002lu
3601#define CMTB_SRC_OFFSET 0x00000004lu
3602#define CMTB_TYPE_OFFSET 0x00000006lu
3603#define CMTB_DATA_OFFSET 0x00000007lu
3604
3605#define CMTB_ANSWER_OFFSET 0x0000000Alu
3606
3607#define CMTB_STAT_N_OFFSET 0x00000018lu
3608#define CMTB_STAT_A_OFFSET 0x00000016lu
3609#define CMTB_STAT_D_OFFSET 0x0000000Elu
3610#define CMTB_STAT_R_OFFSET 0x00000014lu
3611#define CMTB_STAT_W_OFFSET 0x00000014lu
3612#define CMTB_STAT_G_OFFSET 0x00000014lu
3613
3614
3615/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
3616
3617#define APRB_STRIDE 0x00000400lu
3618
3619#define APRB_DST_OFFSET 0x00000000lu
3620#define APRB_LEN_OFFSET 0x00000002lu
3621#define APRB_SRC_OFFSET 0x00000004lu
3622#define APRB_DATA_OFFSET 0x00000006lu
3623
3624
3625/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
3626
3627#define APTB_PRIO_OFFSET 0x00000000lu
3628#define APTB_DST_OFFSET 0x00000002lu
3629#define APTB_LEN_OFFSET 0x00000004lu
3630#define APTB_SRC_OFFSET 0x00000006lu
3631#define APTB_DATA_OFFSET 0x00000008lu
3632
3633
3634/* Remote Read Buffer (RRDB) Address Offsets */
3635
3636#define RRDB_WADDR_OFFSET 0x00000100lu
3637#define RRDB_WLEN_OFFSET 0x00000101lu
3638
3639
3640
3641/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ 2422/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
3642/* CAN_CONTROL Masks */ 2423/* CAN_CONTROL Masks */
3643#define SRS 0x0001 /* Software Reset */ 2424#define SRS 0x0001 /* Software Reset */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 295c78a465c..0c346fba961 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008 Analog Devices Inc. 2 * Copyright (C) 2008-2009 Analog Devices Inc.
3 * Licensed under the GPL-2 or later. 3 * Licensed under the GPL-2 or later.
4 */ 4 */
5 5
@@ -7,11 +7,8 @@
7#ifndef _MACH_GPIO_H_ 7#ifndef _MACH_GPIO_H_
8#define _MACH_GPIO_H_ 8#define _MACH_GPIO_H_
9 9
10 /* FIXME:
11 * For now only support PORTF GPIOs.
12 * PORT C,D and E are for peripheral usage only
13 */
14#define MAX_BLACKFIN_GPIOS 16 10#define MAX_BLACKFIN_GPIOS 16
11#define BFIN_SPECIAL_GPIO_BANKS 3
15 12
16#define GPIO_PF0 0 /* PF */ 13#define GPIO_PF0 0 /* PF */
17#define GPIO_PF1 1 14#define GPIO_PF1 1
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
index 6121cf8b587..0083ba13ee9 100644
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf538/include/mach/portmux.h
@@ -7,7 +7,7 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS 10#define MAX_RESOURCES 64
11 11
12#define P_TMR2 (P_DONTCARE) 12#define P_TMR2 (P_DONTCARE)
13#define P_TMR1 (P_DONTCARE) 13#define P_TMR1 (P_DONTCARE)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 16:55:37 -0400