diff options
Diffstat (limited to 'arch/blackfin/mach-bf533/include')
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/bfin_serial.h | 14 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | 74 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/blackfin.h | 30 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/cdefBF532.h | 63 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/defBF532.h | 128 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/fio_flag.h | 55 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/gpio.h | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/include/mach/pll.h | 58 |
8 files changed, 77 insertions, 347 deletions
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h new file mode 100644 index 00000000000..08072c86d5d --- /dev/null +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h | |||
@@ -0,0 +1,14 @@ | |||
1 | /* | ||
2 | * mach/bfin_serial.h - Blackfin UART/Serial definitions | ||
3 | * | ||
4 | * Copyright 2006-2010 Analog Devices Inc. | ||
5 | * | ||
6 | * Licensed under the GPL-2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __BFIN_MACH_SERIAL_H__ | ||
10 | #define __BFIN_MACH_SERIAL_H__ | ||
11 | |||
12 | #define BFIN_UART_NR_PORTS 1 | ||
13 | |||
14 | #endif | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h index 9e1f3defb6b..45dcaa4f3e4 100644 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | |||
@@ -4,36 +4,9 @@ | |||
4 | * Licensed under the GPL-2 or later | 4 | * Licensed under the GPL-2 or later |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #include <linux/serial.h> | ||
8 | #include <asm/dma.h> | 7 | #include <asm/dma.h> |
9 | #include <asm/portmux.h> | 8 | #include <asm/portmux.h> |
10 | 9 | ||
11 | #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR)) | ||
12 | #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL)) | ||
13 | #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER)) | ||
14 | #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH)) | ||
15 | #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR)) | ||
16 | #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR)) | ||
17 | #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL)) | ||
18 | |||
19 | #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) | ||
20 | #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) | ||
21 | #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) | ||
22 | #define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) | ||
23 | #define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) | ||
24 | #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) | ||
25 | #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) | ||
26 | #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) | ||
27 | |||
28 | #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) | ||
29 | #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) | ||
30 | |||
31 | #define UART_GET_CTS(x) gpio_get_value(x->cts_pin) | ||
32 | #define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) | ||
33 | #define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) | ||
34 | #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) | ||
35 | #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) | ||
36 | |||
37 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 10 | #ifdef CONFIG_BFIN_UART0_CTSRTS |
38 | # define CONFIG_SERIAL_BFIN_CTSRTS | 11 | # define CONFIG_SERIAL_BFIN_CTSRTS |
39 | # ifndef CONFIG_UART0_CTS_PIN | 12 | # ifndef CONFIG_UART0_CTS_PIN |
@@ -44,51 +17,6 @@ | |||
44 | # endif | 17 | # endif |
45 | #endif | 18 | #endif |
46 | 19 | ||
47 | #define BFIN_UART_TX_FIFO_SIZE 2 | ||
48 | |||
49 | struct bfin_serial_port { | ||
50 | struct uart_port port; | ||
51 | unsigned int old_status; | ||
52 | int status_irq; | ||
53 | unsigned int lsr; | ||
54 | #ifdef CONFIG_SERIAL_BFIN_DMA | ||
55 | int tx_done; | ||
56 | int tx_count; | ||
57 | struct circ_buf rx_dma_buf; | ||
58 | struct timer_list rx_dma_timer; | ||
59 | int rx_dma_nrows; | ||
60 | unsigned int tx_dma_channel; | ||
61 | unsigned int rx_dma_channel; | ||
62 | struct work_struct tx_dma_workqueue; | ||
63 | #else | ||
64 | # if ANOMALY_05000363 | ||
65 | unsigned int anomaly_threshold; | ||
66 | # endif | ||
67 | #endif | ||
68 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
69 | struct timer_list cts_timer; | ||
70 | int cts_pin; | ||
71 | int rts_pin; | ||
72 | #endif | ||
73 | }; | ||
74 | |||
75 | /* The hardware clears the LSR bits upon read, so we need to cache | ||
76 | * some of the more fun bits in software so they don't get lost | ||
77 | * when checking the LSR in other code paths (TX). | ||
78 | */ | ||
79 | static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart) | ||
80 | { | ||
81 | unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR); | ||
82 | uart->lsr |= (lsr & (BI|FE|PE|OE)); | ||
83 | return lsr | uart->lsr; | ||
84 | } | ||
85 | |||
86 | static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart) | ||
87 | { | ||
88 | uart->lsr = 0; | ||
89 | bfin_write16(uart->port.membase + OFFSET_LSR, -1); | ||
90 | } | ||
91 | |||
92 | struct bfin_serial_res { | 20 | struct bfin_serial_res { |
93 | unsigned long uart_base_addr; | 21 | unsigned long uart_base_addr; |
94 | int uart_irq; | 22 | int uart_irq; |
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
120 | }; | 48 | }; |
121 | 49 | ||
122 | #define DRIVER_NAME "bfin-uart" | 50 | #define DRIVER_NAME "bfin-uart" |
51 | |||
52 | #include <asm/bfin_serial.h> | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h index f4bd6df5d96..e366207fbf1 100644 --- a/arch/blackfin/mach-bf533/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2005-2009 Analog Devices Inc. | 2 | * Copyright 2005-2010 Analog Devices Inc. |
3 | * | 3 | * |
4 | * Licensed under the GPL-2 or later | 4 | * Licensed under the GPL-2 or later. |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #ifndef _MACH_BLACKFIN_H_ | 7 | #ifndef _MACH_BLACKFIN_H_ |
@@ -10,26 +10,14 @@ | |||
10 | #define BF533_FAMILY | 10 | #define BF533_FAMILY |
11 | 11 | ||
12 | #include "bf533.h" | 12 | #include "bf533.h" |
13 | #include "defBF532.h" | ||
14 | #include "anomaly.h" | 13 | #include "anomaly.h" |
15 | 14 | ||
16 | #if !defined(__ASSEMBLY__) | 15 | #include <asm/def_LPBlackfin.h> |
17 | #include "cdefBF532.h" | 16 | #include "defBF532.h" |
18 | #endif | ||
19 | |||
20 | #define BFIN_UART_NR_PORTS 1 | ||
21 | 17 | ||
22 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | 18 | #ifndef __ASSEMBLY__ |
23 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | 19 | # include <asm/cdef_LPBlackfin.h> |
24 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | 20 | # include "cdefBF532.h" |
25 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | 21 | #endif |
26 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | ||
27 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | ||
28 | #define OFFSET_LCR 0x0C /* Line Control Register */ | ||
29 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | ||
30 | #define OFFSET_LSR 0x14 /* Line Status Register */ | ||
31 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | ||
32 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | ||
33 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | ||
34 | 22 | ||
35 | #endif /* _MACH_BLACKFIN_H_ */ | 23 | #endif |
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h index 401e524f532..fd0cbe4df21 100644 --- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2005-2008 Analog Devices Inc. | 2 | * Copyright 2005-2010 Analog Devices Inc. |
3 | * | 3 | * |
4 | * Licensed under the GPL-2 or later | 4 | * Licensed under the GPL-2 or later |
5 | */ | 5 | */ |
@@ -7,9 +7,6 @@ | |||
7 | #ifndef _CDEF_BF532_H | 7 | #ifndef _CDEF_BF532_H |
8 | #define _CDEF_BF532_H | 8 | #define _CDEF_BF532_H |
9 | 9 | ||
10 | /*include core specific register pointer definitions*/ | ||
11 | #include <asm/cdef_LPBlackfin.h> | ||
12 | |||
13 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ | 10 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ |
14 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | 11 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
15 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) | 12 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
@@ -66,16 +63,10 @@ | |||
66 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) | 63 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) |
67 | 64 | ||
68 | /* DMA Traffic controls */ | 65 | /* DMA Traffic controls */ |
69 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | 66 | #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER) |
70 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | 67 | #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val) |
71 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | 68 | #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT) |
72 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | 69 | #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val) |
73 | |||
74 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
75 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | ||
76 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | ||
77 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | ||
78 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | ||
79 | 70 | ||
80 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ | 71 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ |
81 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) | 72 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) |
@@ -105,6 +96,47 @@ | |||
105 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) | 96 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) |
106 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) | 97 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) |
107 | 98 | ||
99 | #if ANOMALY_05000311 | ||
100 | /* Keep at the CPP expansion to avoid circular header dependency loops */ | ||
101 | #define BFIN_WRITE_FIO_FLAG(name, val) \ | ||
102 | do { \ | ||
103 | unsigned long __flags; \ | ||
104 | __flags = hard_local_irq_save(); \ | ||
105 | bfin_write16(FIO_FLAG_##name, val); \ | ||
106 | bfin_read_CHIPID(); \ | ||
107 | hard_local_irq_restore(__flags); \ | ||
108 | } while (0) | ||
109 | #define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val) | ||
110 | #define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val) | ||
111 | #define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val) | ||
112 | #define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val) | ||
113 | |||
114 | #define BFIN_READ_FIO_FLAG(name) \ | ||
115 | ({ \ | ||
116 | unsigned long __flags; \ | ||
117 | u16 __ret; \ | ||
118 | __flags = hard_local_irq_save(); \ | ||
119 | __ret = bfin_read16(FIO_FLAG_##name); \ | ||
120 | bfin_read_CHIPID(); \ | ||
121 | hard_local_irq_restore(__flags); \ | ||
122 | __ret; \ | ||
123 | }) | ||
124 | #define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D) | ||
125 | #define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C) | ||
126 | #define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S) | ||
127 | #define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T) | ||
128 | |||
129 | #else | ||
130 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) | ||
131 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) | ||
132 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) | ||
133 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) | ||
134 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) | ||
135 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) | ||
136 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) | ||
137 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) | ||
138 | #endif | ||
139 | |||
108 | /* DMA Controller */ | 140 | /* DMA Controller */ |
109 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | 141 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
110 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) | 142 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) |
@@ -647,7 +679,4 @@ | |||
647 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | 679 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
648 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) | 680 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) |
649 | 681 | ||
650 | /* These need to be last due to the cdef/linux inter-dependencies */ | ||
651 | #include <asm/irq.h> | ||
652 | |||
653 | #endif /* _CDEF_BF532_H */ | 682 | #endif /* _CDEF_BF532_H */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h index 3adb0b44e59..2376d539351 100644 --- a/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * System & MMR bit and Address definitions for ADSP-BF532 | 2 | * System & MMR bit and Address definitions for ADSP-BF532 |
3 | * | 3 | * |
4 | * Copyright 2005-2008 Analog Devices Inc. | 4 | * Copyright 2005-2010 Analog Devices Inc. |
5 | * | 5 | * |
6 | * Licensed under the ADI BSD license or the GPL-2 (or later) | 6 | * Licensed under the ADI BSD license or the GPL-2 (or later) |
7 | */ | 7 | */ |
@@ -9,9 +9,6 @@ | |||
9 | #ifndef _DEF_BF532_H | 9 | #ifndef _DEF_BF532_H |
10 | #define _DEF_BF532_H | 10 | #define _DEF_BF532_H |
11 | 11 | ||
12 | /* include all Core registers and bit definitions */ | ||
13 | #include <asm/def_LPBlackfin.h> | ||
14 | |||
15 | /*********************************************************************************** */ | 12 | /*********************************************************************************** */ |
16 | /* System MMR Register Map */ | 13 | /* System MMR Register Map */ |
17 | /*********************************************************************************** */ | 14 | /*********************************************************************************** */ |
@@ -182,12 +179,8 @@ | |||
182 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ | 179 | #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ |
183 | 180 | ||
184 | /* DMA Traffic controls */ | 181 | /* DMA Traffic controls */ |
185 | #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ | 182 | #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ |
186 | #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | 183 | #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ |
187 | |||
188 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | ||
189 | #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ | ||
190 | #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ | ||
191 | 184 | ||
192 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ | 185 | /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ |
193 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ | 186 | #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ |
@@ -432,83 +425,6 @@ | |||
432 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ | 425 | #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ |
433 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ | 426 | #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ |
434 | 427 | ||
435 | /* ***************************** UART CONTROLLER MASKS ********************** */ | ||
436 | |||
437 | /* UART_LCR Register */ | ||
438 | |||
439 | #define DLAB 0x80 | ||
440 | #define SB 0x40 | ||
441 | #define STP 0x20 | ||
442 | #define EPS 0x10 | ||
443 | #define PEN 0x08 | ||
444 | #define STB 0x04 | ||
445 | #define WLS(x) ((x-5) & 0x03) | ||
446 | |||
447 | #define DLAB_P 0x07 | ||
448 | #define SB_P 0x06 | ||
449 | #define STP_P 0x05 | ||
450 | #define EPS_P 0x04 | ||
451 | #define PEN_P 0x03 | ||
452 | #define STB_P 0x02 | ||
453 | #define WLS_P1 0x01 | ||
454 | #define WLS_P0 0x00 | ||
455 | |||
456 | /* UART_MCR Register */ | ||
457 | #define LOOP_ENA 0x10 | ||
458 | #define LOOP_ENA_P 0x04 | ||
459 | |||
460 | /* UART_LSR Register */ | ||
461 | #define TEMT 0x40 | ||
462 | #define THRE 0x20 | ||
463 | #define BI 0x10 | ||
464 | #define FE 0x08 | ||
465 | #define PE 0x04 | ||
466 | #define OE 0x02 | ||
467 | #define DR 0x01 | ||
468 | |||
469 | #define TEMP_P 0x06 | ||
470 | #define THRE_P 0x05 | ||
471 | #define BI_P 0x04 | ||
472 | #define FE_P 0x03 | ||
473 | #define PE_P 0x02 | ||
474 | #define OE_P 0x01 | ||
475 | #define DR_P 0x00 | ||
476 | |||
477 | /* UART_IER Register */ | ||
478 | #define ELSI 0x04 | ||
479 | #define ETBEI 0x02 | ||
480 | #define ERBFI 0x01 | ||
481 | |||
482 | #define ELSI_P 0x02 | ||
483 | #define ETBEI_P 0x01 | ||
484 | #define ERBFI_P 0x00 | ||
485 | |||
486 | /* UART_IIR Register */ | ||
487 | #define STATUS(x) ((x << 1) & 0x06) | ||
488 | #define NINT 0x01 | ||
489 | #define STATUS_P1 0x02 | ||
490 | #define STATUS_P0 0x01 | ||
491 | #define NINT_P 0x00 | ||
492 | #define IIR_TX_READY 0x02 /* UART_THR empty */ | ||
493 | #define IIR_RX_READY 0x04 /* Receive data ready */ | ||
494 | #define IIR_LINE_CHANGE 0x06 /* Receive line status */ | ||
495 | #define IIR_STATUS 0x06 | ||
496 | |||
497 | /* UART_GCTL Register */ | ||
498 | #define FFE 0x20 | ||
499 | #define FPE 0x10 | ||
500 | #define RPOLC 0x08 | ||
501 | #define TPOLC 0x04 | ||
502 | #define IREN 0x02 | ||
503 | #define UCEN 0x01 | ||
504 | |||
505 | #define FFE_P 0x05 | ||
506 | #define FPE_P 0x04 | ||
507 | #define RPOLC_P 0x03 | ||
508 | #define TPOLC_P 0x02 | ||
509 | #define IREN_P 0x01 | ||
510 | #define UCEN_P 0x00 | ||
511 | |||
512 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ | 428 | /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ |
513 | 429 | ||
514 | /* PPI_CONTROL Masks */ | 430 | /* PPI_CONTROL Masks */ |
@@ -643,44 +559,6 @@ | |||
643 | #define ERR_TYP_P0 0x0E | 559 | #define ERR_TYP_P0 0x0E |
644 | #define ERR_TYP_P1 0x0F | 560 | #define ERR_TYP_P1 0x0F |
645 | 561 | ||
646 | /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */ | ||
647 | |||
648 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ | ||
649 | #define PF0 0x0001 | ||
650 | #define PF1 0x0002 | ||
651 | #define PF2 0x0004 | ||
652 | #define PF3 0x0008 | ||
653 | #define PF4 0x0010 | ||
654 | #define PF5 0x0020 | ||
655 | #define PF6 0x0040 | ||
656 | #define PF7 0x0080 | ||
657 | #define PF8 0x0100 | ||
658 | #define PF9 0x0200 | ||
659 | #define PF10 0x0400 | ||
660 | #define PF11 0x0800 | ||
661 | #define PF12 0x1000 | ||
662 | #define PF13 0x2000 | ||
663 | #define PF14 0x4000 | ||
664 | #define PF15 0x8000 | ||
665 | |||
666 | /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ | ||
667 | #define PF0_P 0 | ||
668 | #define PF1_P 1 | ||
669 | #define PF2_P 2 | ||
670 | #define PF3_P 3 | ||
671 | #define PF4_P 4 | ||
672 | #define PF5_P 5 | ||
673 | #define PF6_P 6 | ||
674 | #define PF7_P 7 | ||
675 | #define PF8_P 8 | ||
676 | #define PF9_P 9 | ||
677 | #define PF10_P 10 | ||
678 | #define PF11_P 11 | ||
679 | #define PF12_P 12 | ||
680 | #define PF13_P 13 | ||
681 | #define PF14_P 14 | ||
682 | #define PF15_P 15 | ||
683 | |||
684 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ | 562 | /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ |
685 | 563 | ||
686 | /* AMGCTL Masks */ | 564 | /* AMGCTL Masks */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h deleted file mode 100644 index d0bfba0b083..00000000000 --- a/arch/blackfin/mach-bf533/include/mach/fio_flag.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2005-2008 Analog Devices Inc. | ||
3 | * | ||
4 | * Licensed under the GPL-2 or later | ||
5 | */ | ||
6 | |||
7 | #ifndef _MACH_FIO_FLAG_H | ||
8 | #define _MACH_FIO_FLAG_H | ||
9 | |||
10 | #include <asm/blackfin.h> | ||
11 | #include <asm/irqflags.h> | ||
12 | |||
13 | #if ANOMALY_05000311 | ||
14 | #define BFIN_WRITE_FIO_FLAG(name) \ | ||
15 | static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ | ||
16 | { \ | ||
17 | unsigned long flags; \ | ||
18 | flags = hard_local_irq_save(); \ | ||
19 | bfin_write16(FIO_FLAG_##name, val); \ | ||
20 | bfin_read_CHIPID(); \ | ||
21 | hard_local_irq_restore(flags); \ | ||
22 | } | ||
23 | BFIN_WRITE_FIO_FLAG(D) | ||
24 | BFIN_WRITE_FIO_FLAG(C) | ||
25 | BFIN_WRITE_FIO_FLAG(S) | ||
26 | BFIN_WRITE_FIO_FLAG(T) | ||
27 | |||
28 | #define BFIN_READ_FIO_FLAG(name) \ | ||
29 | static inline u16 bfin_read_FIO_FLAG_##name(void) \ | ||
30 | { \ | ||
31 | unsigned long flags; \ | ||
32 | u16 ret; \ | ||
33 | flags = hard_local_irq_save(); \ | ||
34 | ret = bfin_read16(FIO_FLAG_##name); \ | ||
35 | bfin_read_CHIPID(); \ | ||
36 | hard_local_irq_restore(flags); \ | ||
37 | return ret; \ | ||
38 | } | ||
39 | BFIN_READ_FIO_FLAG(D) | ||
40 | BFIN_READ_FIO_FLAG(C) | ||
41 | BFIN_READ_FIO_FLAG(S) | ||
42 | BFIN_READ_FIO_FLAG(T) | ||
43 | |||
44 | #else | ||
45 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) | ||
46 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) | ||
47 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) | ||
48 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) | ||
49 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) | ||
50 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) | ||
51 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) | ||
52 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) | ||
53 | #endif | ||
54 | |||
55 | #endif /* _MACH_FIO_FLAG_H */ | ||
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h index e02416db4b0..cce4f8fb378 100644 --- a/arch/blackfin/mach-bf533/include/mach/gpio.h +++ b/arch/blackfin/mach-bf533/include/mach/gpio.h | |||
@@ -28,4 +28,6 @@ | |||
28 | 28 | ||
29 | #define PORT_F GPIO_PF0 | 29 | #define PORT_F GPIO_PF0 |
30 | 30 | ||
31 | #include <mach-common/ports-f.h> | ||
32 | |||
31 | #endif /* _MACH_GPIO_H_ */ | 33 | #endif /* _MACH_GPIO_H_ */ |
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h index 169c106d0ed..94cca674d83 100644 --- a/arch/blackfin/mach-bf533/include/mach/pll.h +++ b/arch/blackfin/mach-bf533/include/mach/pll.h | |||
@@ -1,57 +1 @@ | |||
1 | /* | #include <mach-common/pll.h> | |
2 | * Copyright 2005-2008 Analog Devices Inc. | ||
3 | * | ||
4 | * Licensed under the GPL-2 or later | ||
5 | */ | ||
6 | |||
7 | #ifndef _MACH_PLL_H | ||
8 | #define _MACH_PLL_H | ||
9 | |||
10 | #include <asm/blackfin.h> | ||
11 | #include <asm/irqflags.h> | ||
12 | |||
13 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
14 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
15 | { | ||
16 | unsigned long flags, iwr; | ||
17 | |||
18 | if (val == bfin_read_PLL_CTL()) | ||
19 | return; | ||
20 | |||
21 | flags = hard_local_irq_save(); | ||
22 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
23 | iwr = bfin_read32(SIC_IWR); | ||
24 | /* Only allow PPL Wakeup) */ | ||
25 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
26 | |||
27 | bfin_write16(PLL_CTL, val); | ||
28 | SSYNC(); | ||
29 | asm("IDLE;"); | ||
30 | |||
31 | bfin_write32(SIC_IWR, iwr); | ||
32 | hard_local_irq_restore(flags); | ||
33 | } | ||
34 | |||
35 | /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
36 | static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
37 | { | ||
38 | unsigned long flags, iwr; | ||
39 | |||
40 | if (val == bfin_read_VR_CTL()) | ||
41 | return; | ||
42 | |||
43 | flags = hard_local_irq_save(); | ||
44 | /* Enable the PLL Wakeup bit in SIC IWR */ | ||
45 | iwr = bfin_read32(SIC_IWR); | ||
46 | /* Only allow PPL Wakeup) */ | ||
47 | bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
48 | |||
49 | bfin_write16(VR_CTL, val); | ||
50 | SSYNC(); | ||
51 | asm("IDLE;"); | ||
52 | |||
53 | bfin_write32(SIC_IWR, iwr); | ||
54 | hard_local_irq_restore(flags); | ||
55 | } | ||
56 | |||
57 | #endif /* _MACH_PLL_H */ | ||