aboutsummaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf533/head.S
diff options
context:
space:
mode:
Diffstat (limited to 'arch/blackfin/mach-bf533/head.S')
-rw-r--r--arch/blackfin/mach-bf533/head.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 1ded945a6fa..d9ba2b11e01 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -151,26 +151,26 @@ ENTRY(__start)
151 151
152 /* Initialise UART - when booting from u-boot, the UART is not disabled 152 /* Initialise UART - when booting from u-boot, the UART is not disabled
153 * so if we dont initalize here, our serial console gets hosed */ 153 * so if we dont initalize here, our serial console gets hosed */
154 p0.h = hi(UART_LCR); 154 p0.h = hi(BFIN_UART_LCR);
155 p0.l = lo(UART_LCR); 155 p0.l = lo(BFIN_UART_LCR);
156 r0 = 0x0(Z); 156 r0 = 0x0(Z);
157 w[p0] = r0.L; /* To enable DLL writes */ 157 w[p0] = r0.L; /* To enable DLL writes */
158 ssync; 158 ssync;
159 159
160 p0.h = hi(UART_DLL); 160 p0.h = hi(BFIN_UART_DLL);
161 p0.l = lo(UART_DLL); 161 p0.l = lo(BFIN_UART_DLL);
162 r0 = 0x0(Z); 162 r0 = 0x0(Z);
163 w[p0] = r0.L; 163 w[p0] = r0.L;
164 ssync; 164 ssync;
165 165
166 p0.h = hi(UART_DLH); 166 p0.h = hi(BFIN_UART_DLH);
167 p0.l = lo(UART_DLH); 167 p0.l = lo(BFIN_UART_DLH);
168 r0 = 0x00(Z); 168 r0 = 0x00(Z);
169 w[p0] = r0.L; 169 w[p0] = r0.L;
170 ssync; 170 ssync;
171 171
172 p0.h = hi(UART_GCTL); 172 p0.h = hi(BFIN_UART_GCTL);
173 p0.l = lo(UART_GCTL); 173 p0.l = lo(BFIN_UART_GCTL);
174 r0 = 0x0(Z); 174 r0 = 0x0(Z);
175 w[p0] = r0.L; /* To enable UART clock */ 175 w[p0] = r0.L; /* To enable UART clock */
176 ssync; 176 ssync;