1 files changed, 275 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 00000000000..1ff9f1468c0
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,275 @@
+/*
+ * bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __BFIN_ASM_SERIAL_H__
+#define __BFIN_ASM_SERIAL_H__
+#include <linux/serial_core.h>
+#include <mach/anomaly.h>
+#include <mach/bfin_serial.h>
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
+    defined(CONFIG_BFIN_UART1_CTSRTS) || \
+    defined(CONFIG_BFIN_UART2_CTSRTS) || \
+    defined(CONFIG_BFIN_UART3_CTSRTS)
+# ifdef BFIN_UART_BF54X_STYLE
+#  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
+# else
+#  define CONFIG_SERIAL_BFIN_CTSRTS
+# endif
+#endif
+struct circ_buf;
+struct timer_list;
+struct work_struct;
+struct bfin_serial_port {
+        struct uart_port port;
+        unsigned int old_status;
+        int status_irq;
+#ifndef BFIN_UART_BF54X_STYLE
+        unsigned int lsr;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int tx_done;
+        int tx_count;
+        struct circ_buf rx_dma_buf;
+        struct timer_list rx_dma_timer;
+        int rx_dma_nrows;
+        unsigned int tx_dma_channel;
+        unsigned int rx_dma_channel;
+        struct work_struct tx_dma_workqueue;
+#elif ANOMALY_05000363
+        unsigned int anomaly_threshold;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        int scts;
+#endif
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+        int cts_pin;
+        int rts_pin;
+#endif
+};
+/* UART_LCR Masks */
+#define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
+#define STB                      0x04  /* Stop Bits */
+#define PEN                      0x08  /* Parity Enable */
+#define EPS                      0x10  /* Even Parity Select */
+#define STP                      0x20  /* Stick Parity */
+#define SB                       0x40  /* Set Break */
+#define DLAB                     0x80  /* Divisor Latch Access */
+/* UART_LSR Masks */
+#define DR                       0x01  /* Data Ready */
+#define OE                       0x02  /* Overrun Error */
+#define PE                       0x04  /* Parity Error */
+#define FE                       0x08  /* Framing Error */
+#define BI                       0x10  /* Break Interrupt */
+#define THRE                     0x20  /* THR Empty */
+#define TEMT                     0x40  /* TSR and UART_THR Empty */
+#define TFI                      0x80  /* Transmission Finished Indicator */
+/* UART_IER Masks */
+#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
+#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI                     0x04  /* Enable RX Status Interrupt */
+#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
+#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
+#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
+#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
+/* UART_MCR Masks */
+#define XOFF                     0x01  /* Transmitter Off */
+#define MRTS                     0x02  /* Manual Request To Send */
+#define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
+#define RFRT                     0x08  /* Receive FIFO RTS Threshold */
+#define LOOP_ENA                 0x10  /* Loopback Mode Enable */
+#define FCPOL                    0x20  /* Flow Control Pin Polarity */
+#define ARTS                     0x40  /* Automatic Request To Send */
+#define ACTS                     0x80  /* Automatic Clear To Send */
+/* UART_MSR Masks */
+#define SCTS                     0x01  /* Sticky CTS */
+#define CTS                      0x10  /* Clear To Send */
+#define RFCS                     0x20  /* Receive FIFO Count Status */
+/* UART_GCTL Masks */
+#define UCEN                     0x01  /* Enable UARTx Clocks */
+#define IREN                     0x02  /* Enable IrDA Mode */
+#define TPOLC                    0x04  /* IrDA TX Polarity Change */
+#define RPOLC                    0x08  /* IrDA RX Polarity Change */
+#define FPE                      0x10  /* Force Parity Error On Transmit */
+#define FFE                      0x20  /* Force Framing Error On Transmit */
+#ifdef BFIN_UART_BF54X_STYLE
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
+# define OFFSET_GCTL             0x08  /* Global Control Register         */
+# define OFFSET_LCR              0x0C  /* Line Control Register           */
+# define OFFSET_MCR              0x10  /* Modem Control Register          */
+# define OFFSET_LSR              0x14  /* Line Status Register            */
+# define OFFSET_MSR              0x18  /* Modem Status Register           */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
+# define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
+# define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
+# define OFFSET_THR              0x28  /* Transmit Holding register       */
+# define OFFSET_RBR              0x2C  /* Receive Buffer register         */
+#else /* BF533 style */
+# define OFFSET_THR              0x00  /* Transmit Holding register         */
+# define OFFSET_RBR              0x00  /* Receive Buffer register           */
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
+# define OFFSET_IER              0x04  /* Interrupt Enable Register         */
+# define OFFSET_IIR              0x08  /* Interrupt Identification Register */
+# define OFFSET_LCR              0x0C  /* Line Control Register             */
+# define OFFSET_MCR              0x10  /* Modem Control Register            */
+# define OFFSET_LSR              0x14  /* Line Status Register              */
+# define OFFSET_MSR              0x18  /* Modem Status Register             */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
+# define OFFSET_GCTL             0x24  /* Global Control Register           */
+/* code should not need IIR, so force build error if they use it */
+# undef OFFSET_IIR
+#endif
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+struct bfin_uart_regs {
+#ifdef BFIN_UART_BF54X_STYLE
+        __BFP(dll);
+        __BFP(dlh);
+        __BFP(gctl);
+        __BFP(lcr);
+        __BFP(mcr);
+        __BFP(lsr);
+        __BFP(msr);
+        __BFP(scr);
+        __BFP(ier_set);
+        __BFP(ier_clear);
+        __BFP(thr);
+        __BFP(rbr);
+#else
+        union {
+                u16 dll;
+                u16 thr;
+                const u16 rbr;
+        };
+        const u16 __pad0;
+        union {
+                u16 dlh;
+                u16 ier;
+        };
+        const u16 __pad1;
+        const __BFP(iir);
+        __BFP(lcr);
+        __BFP(mcr);
+        __BFP(lsr);
+        __BFP(msr);
+        __BFP(scr);
+        const u32 __pad2;
+        __BFP(gctl);
+#endif
+};
+#undef __BFP
+#ifndef port_membase
+# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
+#endif
+#define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
+#define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
+#define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
+#define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
+#define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
+#define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
+#define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
+#define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
+#define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
+#define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
+#define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
+#define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
+#define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
+#ifdef BFIN_UART_BF54X_STYLE
+#define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
+#define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
+#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
+#define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
+#define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
+#define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
+#define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
+/* This handles hard CTS/RTS */
+#define BFIN_UART_CTSRTS_HARD
+#define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
+#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
+#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
+#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
+#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
+#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
+#else /* BF533 style */
+#define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
+#define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
+#define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
+#define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
+#define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
+#ifndef put_lsr_cache
+# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
+#endif
+#ifndef get_lsr_cache
+# define get_lsr_cache(p)    (((struct bfin_serial_port *)(p))->lsr)
+#endif
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline void UART_CLEAR_LSR(void *p)
+{
+        put_lsr_cache(p, 0);
+        bfin_write16(port_membase(p) + OFFSET_LSR, -1);
+}
+static inline unsigned int UART_GET_LSR(void *p)
+{
+        unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
+        put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
+        return lsr | get_lsr_cache(p);
+}
+static inline void UART_PUT_LSR(void *p, uint16_t val)
+{
+        put_lsr_cache(p, get_lsr_cache(p) & ~val);
+}
+/* This handles soft CTS/RTS */
+#define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
+#define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
+#define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
+#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+#define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
+#endif
+#ifndef BFIN_UART_TX_FIFO_SIZE
+# define BFIN_UART_TX_FIFO_SIZE 2
+#endif
+#endif /* __BFIN_ASM_SERIAL_H__ */

diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h new file mode 100644 index 00000000000..1ff9f1468c0 --- /dev/null +++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,275 @@
	1	/*
	2	* bfin_serial.h - Blackfin UART/Serial definitions
	3	*
	4	* Copyright 2006-2010 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#ifndef __BFIN_ASM_SERIAL_H__
	10	#define __BFIN_ASM_SERIAL_H__
	11
	12	#include <linux/serial_core.h>
	13	#include <mach/anomaly.h>
	14	#include <mach/bfin_serial.h>
	15
	16	#if defined(CONFIG_BFIN_UART0_CTSRTS) \|\| \
	17	defined(CONFIG_BFIN_UART1_CTSRTS) \|\| \
	18	defined(CONFIG_BFIN_UART2_CTSRTS) \|\| \
	19	defined(CONFIG_BFIN_UART3_CTSRTS)
	20	# ifdef BFIN_UART_BF54X_STYLE
	21	# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
	22	# else
	23	# define CONFIG_SERIAL_BFIN_CTSRTS
	24	# endif
	25	#endif
	26
	27	struct circ_buf;
	28	struct timer_list;
	29	struct work_struct;
	30
	31	struct bfin_serial_port {
	32	struct uart_port port;
	33	unsigned int old_status;
	34	int status_irq;
	35	#ifndef BFIN_UART_BF54X_STYLE
	36	unsigned int lsr;
	37	#endif
	38	#ifdef CONFIG_SERIAL_BFIN_DMA
	39	int tx_done;
	40	int tx_count;
	41	struct circ_buf rx_dma_buf;
	42	struct timer_list rx_dma_timer;
	43	int rx_dma_nrows;
	44	unsigned int tx_dma_channel;
	45	unsigned int rx_dma_channel;
	46	struct work_struct tx_dma_workqueue;
	47	#elif ANOMALY_05000363
	48	unsigned int anomaly_threshold;
	49	#endif
	50	#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
	51	int scts;
	52	#endif
	53	#if defined(CONFIG_SERIAL_BFIN_CTSRTS) \|\| \
	54	defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
	55	int cts_pin;
	56	int rts_pin;
	57	#endif
	58	};
	59
	60	/* UART_LCR Masks */
	61	#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
	62	#define STB 0x04 /* Stop Bits */
	63	#define PEN 0x08 /* Parity Enable */
	64	#define EPS 0x10 /* Even Parity Select */
	65	#define STP 0x20 /* Stick Parity */
	66	#define SB 0x40 /* Set Break */
	67	#define DLAB 0x80 /* Divisor Latch Access */
	68
	69	/* UART_LSR Masks */
	70	#define DR 0x01 /* Data Ready */
	71	#define OE 0x02 /* Overrun Error */
	72	#define PE 0x04 /* Parity Error */
	73	#define FE 0x08 /* Framing Error */
	74	#define BI 0x10 /* Break Interrupt */
	75	#define THRE 0x20 /* THR Empty */
	76	#define TEMT 0x40 /* TSR and UART_THR Empty */
	77	#define TFI 0x80 /* Transmission Finished Indicator */
	78
	79	/* UART_IER Masks */
	80	#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
	81	#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
	82	#define ELSI 0x04 /* Enable RX Status Interrupt */
	83	#define EDSSI 0x08 /* Enable Modem Status Interrupt */
	84	#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
	85	#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
	86	#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
	87
	88	/* UART_MCR Masks */
	89	#define XOFF 0x01 /* Transmitter Off */
	90	#define MRTS 0x02 /* Manual Request To Send */
	91	#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
	92	#define RFRT 0x08 /* Receive FIFO RTS Threshold */
	93	#define LOOP_ENA 0x10 /* Loopback Mode Enable */
	94	#define FCPOL 0x20 /* Flow Control Pin Polarity */
	95	#define ARTS 0x40 /* Automatic Request To Send */
	96	#define ACTS 0x80 /* Automatic Clear To Send */
	97
	98	/* UART_MSR Masks */
	99	#define SCTS 0x01 /* Sticky CTS */
	100	#define CTS 0x10 /* Clear To Send */
	101	#define RFCS 0x20 /* Receive FIFO Count Status */
	102
	103	/* UART_GCTL Masks */
	104	#define UCEN 0x01 /* Enable UARTx Clocks */
	105	#define IREN 0x02 /* Enable IrDA Mode */
	106	#define TPOLC 0x04 /* IrDA TX Polarity Change */
	107	#define RPOLC 0x08 /* IrDA RX Polarity Change */
	108	#define FPE 0x10 /* Force Parity Error On Transmit */
	109	#define FFE 0x20 /* Force Framing Error On Transmit */
	110
	111	#ifdef BFIN_UART_BF54X_STYLE
	112	# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
	113	# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
	114	# define OFFSET_GCTL 0x08 /* Global Control Register */
	115	# define OFFSET_LCR 0x0C /* Line Control Register */
	116	# define OFFSET_MCR 0x10 /* Modem Control Register */
	117	# define OFFSET_LSR 0x14 /* Line Status Register */
	118	# define OFFSET_MSR 0x18 /* Modem Status Register */
	119	# define OFFSET_SCR 0x1C /* SCR Scratch Register */
	120	# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
	121	# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
	122	# define OFFSET_THR 0x28 /* Transmit Holding register */
	123	# define OFFSET_RBR 0x2C /* Receive Buffer register */
	124	#else /* BF533 style */
	125	# define OFFSET_THR 0x00 /* Transmit Holding register */
	126	# define OFFSET_RBR 0x00 /* Receive Buffer register */
	127	# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
	128	# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
	129	# define OFFSET_IER 0x04 /* Interrupt Enable Register */
	130	# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
	131	# define OFFSET_LCR 0x0C /* Line Control Register */
	132	# define OFFSET_MCR 0x10 /* Modem Control Register */
	133	# define OFFSET_LSR 0x14 /* Line Status Register */
	134	# define OFFSET_MSR 0x18 /* Modem Status Register */
	135	# define OFFSET_SCR 0x1C /* SCR Scratch Register */
	136	# define OFFSET_GCTL 0x24 /* Global Control Register */
	137	/* code should not need IIR, so force build error if they use it */
	138	# undef OFFSET_IIR
	139	#endif
	140
	141	/*
	142	* All Blackfin system MMRs are padded to 32bits even if the register
	143	* itself is only 16bits. So use a helper macro to streamline this.
	144	*/
	145	#define __BFP(m) u16 m; u16 __pad_##m
	146	struct bfin_uart_regs {
	147	#ifdef BFIN_UART_BF54X_STYLE
	148	__BFP(dll);
	149	__BFP(dlh);
	150	__BFP(gctl);
	151	__BFP(lcr);
	152	__BFP(mcr);
	153	__BFP(lsr);
	154	__BFP(msr);
	155	__BFP(scr);
	156	__BFP(ier_set);
	157	__BFP(ier_clear);
	158	__BFP(thr);
	159	__BFP(rbr);
	160	#else
	161	union {
	162	u16 dll;
	163	u16 thr;
	164	const u16 rbr;
	165	};
	166	const u16 __pad0;
	167	union {
	168	u16 dlh;
	169	u16 ier;
	170	};
	171	const u16 __pad1;
	172	const __BFP(iir);
	173	__BFP(lcr);
	174	__BFP(mcr);
	175	__BFP(lsr);
	176	__BFP(msr);
	177	__BFP(scr);
	178	const u32 __pad2;
	179	__BFP(gctl);
	180	#endif
	181	};
	182	#undef __BFP
	183
	184	#ifndef port_membase
	185	# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
	186	#endif
	187
	188	#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
	189	#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
	190	#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
	191	#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
	192	#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
	193	#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
	194	#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
	195
	196	#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
	197	#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
	198	#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
	199	#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
	200	#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
	201	#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
	202
	203	#ifdef BFIN_UART_BF54X_STYLE
	204
	205	#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
	206	#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
	207	#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
	208
	209	#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
	210	#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
	211
	212	#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
	213	#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
	214	#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
	215
	216	/* This handles hard CTS/RTS */
	217	#define BFIN_UART_CTSRTS_HARD
	218	#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
	219	#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
	220	#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS \| MRTS))
	221	#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) \| MRTS \| ARTS)
	222	#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
	223	#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
	224
	225	#else /* BF533 style */
	226
	227	#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
	228	#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
	229	#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
	230	#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) \| (v))
	231
	232	#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
	233	#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) \| DLAB); SSYNC(); } while (0)
	234
	235	#ifndef put_lsr_cache
	236	# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
	237	#endif
	238	#ifndef get_lsr_cache
	239	# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr)
	240	#endif
	241
	242	/* The hardware clears the LSR bits upon read, so we need to cache
	243	* some of the more fun bits in software so they don't get lost
	244	* when checking the LSR in other code paths (TX).
	245	*/
	246	static inline void UART_CLEAR_LSR(void *p)
	247	{
	248	put_lsr_cache(p, 0);
	249	bfin_write16(port_membase(p) + OFFSET_LSR, -1);
	250	}
	251	static inline unsigned int UART_GET_LSR(void *p)
	252	{
	253	unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
	254	put_lsr_cache(p, get_lsr_cache(p) \| (lsr & (BI\|FE\|PE\|OE)));
	255	return lsr \| get_lsr_cache(p);
	256	}
	257	static inline void UART_PUT_LSR(void *p, uint16_t val)
	258	{
	259	put_lsr_cache(p, get_lsr_cache(p) & ~val);
	260	}
	261
	262	/* This handles soft CTS/RTS */
	263	#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
	264	#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
	265	#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
	266	#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
	267	#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
	268
	269	#endif
	270
	271	#ifndef BFIN_UART_TX_FIFO_SIZE
	272	# define BFIN_UART_TX_FIFO_SIZE 2
	273	#endif
	274
	275	#endif /* __BFIN_ASM_SERIAL_H__ */