7 files changed, 67 insertions, 121 deletions

diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index cd2062fe0f6..49642b59f73 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -6,6 +6,11 @@ config AVR32
         select HAVE_CLK
         select HAVE_OPROFILE
         select HAVE_KPROBES
+        select HAVE_GENERIC_HARDIRQS
+        select GENERIC_IRQ_PROBE
+        select HARDIRQS_SW_RESEND
+        select GENERIC_IRQ_SHOW
+        select GENERIC_HARDIRQS_NO_DEPRECATED
         help
           AVR32 is a high-performance 32-bit RISC microprocessor core,
           designed for cost-sensitive embedded applications, with particular
@@ -17,9 +22,6 @@ config AVR32
 config GENERIC_GPIO
         def_bool y
 
-config GENERIC_HARDIRQS
-        def_bool y
-
 config STACKTRACE_SUPPORT
         def_bool y
 
@@ -29,12 +31,6 @@ config LOCKDEP_SUPPORT
 config TRACE_IRQFLAGS_SUPPORT
         def_bool y
 
-config HARDIRQS_SW_RESEND
-        def_bool y
-
-config GENERIC_IRQ_PROBE
-        def_bool y
-
 config RWSEM_GENERIC_SPINLOCK
         def_bool y
 
diff --git a/arch/avr32/boards/atngw100/mrmt.c b/arch/avr32/boards/atngw100/mrmt.c
index 7919be311f4..f9143196345 100644
--- a/arch/avr32/boards/atngw100/mrmt.c
+++ b/arch/avr32/boards/atngw100/mrmt.c
@@ -301,7 +301,7 @@ static int __init mrmt1_init(void)
         /* Select the Touchscreen interrupt pin mode */
         at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ),
                         GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
-        set_irq_type( AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING );
+        irq_set_irq_type(AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING);
         at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info));
         spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info));
 #endif
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index 659d119ce71..fafed4c38fd 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -322,6 +322,6 @@ static int __init atngw100_arch_init(void)
         /* set_irq_type() after the arch_initcall for EIC has run, and
          * before the I2C subsystem could try using this IRQ.
          */
-        return set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING);
+        return irq_set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING);
 }
 arch_initcall(atngw100_arch_init);
diff --git a/arch/avr32/kernel/irq.c b/arch/avr32/kernel/irq.c
index 9604f7758f9..bc3aa18293d 100644
--- a/arch/avr32/kernel/irq.c
+++ b/arch/avr32/kernel/irq.c
@@ -26,40 +26,3 @@ void __weak nmi_disable(void)
 {
 
 }
-
-#ifdef CONFIG_PROC_FS
-int show_interrupts(struct seq_file *p, void *v)
-{
-        int i = *(loff_t *)v, cpu;
-        struct irqaction *action;
-        unsigned long flags;
-
-        if (i == 0) {
-                seq_puts(p, "           ");
-                for_each_online_cpu(cpu)
-                        seq_printf(p, "CPU%d       ", cpu);
-                seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
-                if (!action)
-                        goto unlock;
-
-                seq_printf(p, "%3d: ", i);
-                for_each_online_cpu(cpu)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-");
-                seq_printf(p, "  %s", action->name);
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-        unlock:
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        }
-
-        return 0;
-}
-#endif
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
index e9d12058ffd..47ba4b9b6db 100644
--- a/arch/avr32/mach-at32ap/extint.c
+++ b/arch/avr32/mach-at32ap/extint.c
@@ -61,45 +61,42 @@ struct eic {
 static struct eic *nmi_eic;
 static bool nmi_enabled;
 
-static void eic_ack_irq(unsigned int irq)
+static void eic_ack_irq(struct irq_chip *d)
 {
-        struct eic *eic = get_irq_chip_data(irq);
-        eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
+        struct eic *eic = irq_data_get_irq_chip_data(data);
+        eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
 }
 
-static void eic_mask_irq(unsigned int irq)
+static void eic_mask_irq(struct irq_chip *d)
 {
-        struct eic *eic = get_irq_chip_data(irq);
-        eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
+        struct eic *eic = irq_data_get_irq_chip_data(data);
+        eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
 }
 
-static void eic_mask_ack_irq(unsigned int irq)
+static void eic_mask_ack_irq(struct irq_chip *d)
 {
-        struct eic *eic = get_irq_chip_data(irq);
-        eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
-        eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
+        struct eic *eic = irq_data_get_irq_chip_data(data);
+        eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
+        eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
 }
 
-static void eic_unmask_irq(unsigned int irq)
+static void eic_unmask_irq(struct irq_chip *d)
 {
-        struct eic *eic = get_irq_chip_data(irq);
-        eic_writel(eic, IER, 1 << (irq - eic->first_irq));
+        struct eic *eic = irq_data_get_irq_chip_data(data);
+        eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
 }
 
-static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
+static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type)
 {
-        struct eic *eic = get_irq_chip_data(irq);
-        struct irq_desc *desc;
+        struct eic *eic = irq_data_get_irq_chip_data(data);
+        unsigned int irq = d->irq;
         unsigned int i = irq - eic->first_irq;
         u32 mode, edge, level;
-        int ret = 0;
 
         flow_type &= IRQ_TYPE_SENSE_MASK;
         if (flow_type == IRQ_TYPE_NONE)
                 flow_type = IRQ_TYPE_LEVEL_LOW;
 
-        desc = &irq_desc[irq];
-
         mode = eic_readl(eic, MODE);
         edge = eic_readl(eic, EDGE);
         level = eic_readl(eic, LEVEL);
@@ -122,39 +119,34 @@ static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
                 edge &= ~(1 << i);
                 break;
         default:
-                ret = -EINVAL;
-                break;
+                return -EINVAL;
         }
 
-        if (ret == 0) {
-                eic_writel(eic, MODE, mode);
-                eic_writel(eic, EDGE, edge);
-                eic_writel(eic, LEVEL, level);
-
-                if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
-                        flow_type |= IRQ_LEVEL;
-                        __set_irq_handler_unlocked(irq, handle_level_irq);
-                } else
-                        __set_irq_handler_unlocked(irq, handle_edge_irq);
-                desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-                desc->status |= flow_type;
-        }
+        eic_writel(eic, MODE, mode);
+        eic_writel(eic, EDGE, edge);
+        eic_writel(eic, LEVEL, level);
 
-        return ret;
+        irqd_set_trigger_type(d, flow_type);
+        if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+                __irq_set_handler_locked(irq, handle_level_irq);
+        else
+                __irq_set_handler_locked(irq, handle_edge_irq);
+
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 
 static struct irq_chip eic_chip = {
         .name           = "eic",
-        .ack            = eic_ack_irq,
-        .mask           = eic_mask_irq,
-        .mask_ack       = eic_mask_ack_irq,
-        .unmask         = eic_unmask_irq,
-        .set_type       = eic_set_irq_type,
+        .irq_ack        = eic_ack_irq,
+        .irq_mask       = eic_mask_irq,
+        .irq_mask_ack   = eic_mask_ack_irq,
+        .irq_unmask     = eic_unmask_irq,
+        .irq_set_type   = eic_set_irq_type,
 };
 
 static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
 {
-        struct eic *eic = desc->handler_data;
+        struct eic *eic = irq_desc_get_handler_data(desc);
         unsigned long status, pending;
         unsigned int i;
 
@@ -234,13 +226,13 @@ static int __init eic_probe(struct platform_device *pdev)
         eic->chip = &eic_chip;
 
         for (i = 0; i < nr_of_irqs; i++) {
-                set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
+                irq_set_chip_and_handler(eic->first_irq + i, &eic_chip,
                                          handle_level_irq);
-                set_irq_chip_data(eic->first_irq + i, eic);
+                irq_set_chip_data(eic->first_irq + i, eic);
         }
 
-        set_irq_chained_handler(int_irq, demux_eic_irq);
-        set_irq_data(int_irq, eic);
+        irq_set_chained_handler(int_irq, demux_eic_irq);
+        irq_set_handler_data(int_irq, eic);
 
         if (pdev->id == 0) {
                 nmi_eic = eic;
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 994c4545e2b..21ce35f33aa 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -34,12 +34,12 @@ extern struct platform_device at32_intc0_device;
  * TODO: We may be able to implement mask/unmask by setting IxM flags
  * in the status register.
  */
-static void intc_mask_irq(unsigned int irq)
+static void intc_mask_irq(struct irq_data *d)
 {
 
 }
 
-static void intc_unmask_irq(unsigned int irq)
+static void intc_unmask_irq(struct irq_data *d)
 {
 
 }
@@ -47,8 +47,8 @@ static void intc_unmask_irq(unsigned int irq)
 static struct intc intc0 = {
         .chip = {
                 .name           = "intc",
-                .mask           = intc_mask_irq,
-                .unmask         = intc_unmask_irq,
+                .irq_mask       = intc_mask_irq,
+                .irq_unmask     = intc_unmask_irq,
         },
 };
 
@@ -57,7 +57,6 @@ static struct intc intc0 = {
  */
 asmlinkage void do_IRQ(int level, struct pt_regs *regs)
 {
-        struct irq_desc *desc;
         struct pt_regs *old_regs;
         unsigned int irq;
         unsigned long status_reg;
@@ -69,8 +68,7 @@ asmlinkage void do_IRQ(int level, struct pt_regs *regs)
         irq_enter();
 
         irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
-        desc = irq_desc + irq;
-        desc->handle_irq(irq, desc);
+        generic_handle_irq(irq);
 
         /*
          * Clear all interrupt level masks so that we may handle
@@ -128,7 +126,7 @@ void __init init_IRQ(void)
                 intc_writel(&intc0, INTPR0 + 4 * i, offset);
                 readback = intc_readl(&intc0, INTPR0 + 4 * i);
                 if (readback == offset)
-                        set_irq_chip_and_handler(i, &intc0.chip,
+                        irq_set_chip_and_handler(i, &intc0.chip,
                                                  handle_simple_irq);
         }
 
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
index 09a274c9d0b..37534103574 100644
--- a/arch/avr32/mach-at32ap/pio.c
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -249,23 +249,23 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 
 /* GPIO IRQ support */
 
-static void gpio_irq_mask(unsigned irq)
+static void gpio_irq_mask(struct irq_data *d)
 {
-        unsigned                gpio = irq_to_gpio(irq);
+        unsigned                gpio = irq_to_gpio(d->irq);
         struct pio_device       *pio = &pio_dev[gpio >> 5];
 
         pio_writel(pio, IDR, 1 << (gpio & 0x1f));
 }
 
-static void gpio_irq_unmask(unsigned irq)
+static void gpio_irq_unmask(struct irq_data *d))
 {
-        unsigned                gpio = irq_to_gpio(irq);
+        unsigned                gpio = irq_to_gpio(d->irq);
         struct pio_device       *pio = &pio_dev[gpio >> 5];
 
         pio_writel(pio, IER, 1 << (gpio & 0x1f));
 }
 
-static int gpio_irq_type(unsigned irq, unsigned type)
+static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
         if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE)
                 return -EINVAL;
@@ -275,20 +275,19 @@ static int gpio_irq_type(unsigned irq, unsigned type)
 
 static struct irq_chip gpio_irqchip = {
         .name           = "gpio",
-        .mask           = gpio_irq_mask,
-        .unmask         = gpio_irq_unmask,
-        .set_type       = gpio_irq_type,
+        .irq_mask       = gpio_irq_mask,
+        .irq_unmask     = gpio_irq_unmask,
+        .irq_set_type   = gpio_irq_type,
 };
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        struct pio_device       *pio = get_irq_chip_data(irq);
+        struct pio_device       *pio = get_irq_desc_chip_data(desc);
         unsigned                gpio_irq;
 
-        gpio_irq = (unsigned) get_irq_data(irq);
+        gpio_irq = (unsigned) irq_get_handler_data(irq);
         for (;;) {
                 u32             isr;
-                struct irq_desc *d;
 
                 /* ack pending GPIO interrupts */
                 isr = pio_readl(pio, ISR) & pio_readl(pio, IMR);
@@ -301,9 +300,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         isr &= ~(1 << i);
 
                         i += gpio_irq;
-                        d = &irq_desc[i];
-
-                        d->handle_irq(i, d);
+                        generic_handle_irq(i);
                 } while (isr);
         }
 }
@@ -313,16 +310,16 @@ gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
 {
         unsigned        i;
 
-        set_irq_chip_data(irq, pio);
-        set_irq_data(irq, (void *) gpio_irq);
+        irq_set_chip_data(irq, pio);
+        irq_set_handler_data(irq, (void *)gpio_irq);
 
         for (i = 0; i < 32; i++, gpio_irq++) {
-                set_irq_chip_data(gpio_irq, pio);
-                set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
-                                handle_simple_irq);
+                irq_set_chip_data(gpio_irq, pio);
+                irq_set_chip_and_handler(gpio_irq, &gpio_irqchip,
+                                         handle_simple_irq);
         }
 
-        set_irq_chained_handler(irq, gpio_irq_handler);
+        irq_set_chained_handler(irq, gpio_irq_handler);
 }
 
 /*--------------------------------------------------------------------------*/