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-rw-r--r--arch/arm/common/gic.c2
-rw-r--r--arch/arm/common/locomo.c84
-rw-r--r--arch/arm/common/sa1111.c30
-rw-r--r--arch/arm/common/vic.c8
-rw-r--r--arch/arm/kernel/ecard.c10
-rw-r--r--arch/arm/kernel/irq.c8
-rw-r--r--arch/arm/mach-aaec2000/core.c4
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c8
-rw-r--r--arch/arm/mach-at91rm9200/irq.c2
-rw-r--r--arch/arm/mach-clps711x/irq.c8
-rw-r--r--arch/arm/mach-clps7500/core.c28
-rw-r--r--arch/arm/mach-ebsa110/core.c4
-rw-r--r--arch/arm/mach-ep93xx/core.c6
-rw-r--r--arch/arm/mach-footbridge/common.c4
-rw-r--r--arch/arm/mach-footbridge/isa-irq.c10
-rw-r--r--arch/arm/mach-h720x/common.c22
-rw-r--r--arch/arm/mach-h720x/cpu-h7202.c6
-rw-r--r--arch/arm/mach-imx/irq.c14
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c8
-rw-r--r--arch/arm/mach-iop32x/irq.c2
-rw-r--r--arch/arm/mach-iop33x/irq.c2
-rw-r--r--arch/arm/mach-ixp2000/core.c20
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c8
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c8
-rw-r--r--arch/arm/mach-ixp23xx/core.c16
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c16
-rw-r--r--arch/arm/mach-ixp4xx/common.c4
-rw-r--r--arch/arm/mach-l7200/core.c4
-rw-r--r--arch/arm/mach-lh7a40x/arch-kev7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/arch-lpd7a40x.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-kev7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a400.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a404.c4
-rw-r--r--arch/arm/mach-lh7a40x/irq-lpd7a40x.c4
-rw-r--r--arch/arm/mach-netx/generic.c6
-rw-r--r--arch/arm/mach-omap1/fpga.c6
-rw-r--r--arch/arm/mach-omap1/irq.c2
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-pnx4008/irq.c10
-rw-r--r--arch/arm/mach-pxa/irq.c10
-rw-r--r--arch/arm/mach-pxa/lpd270.c4
-rw-r--r--arch/arm/mach-pxa/lubbock.c4
-rw-r--r--arch/arm/mach-pxa/mainstone.c4
-rw-r--r--arch/arm/mach-rpc/irq.c14
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c8
-rw-r--r--arch/arm/mach-s3c2410/irq.c48
-rw-r--r--arch/arm/mach-s3c2410/irq.h2
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-irq.c4
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c10
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c12
-rw-r--r--arch/arm/mach-sa1100/h3600.c6
-rw-r--r--arch/arm/mach-sa1100/irq.c8
-rw-r--r--arch/arm/mach-sa1100/neponset.c8
-rw-r--r--arch/arm/mach-shark/irq.c2
-rw-r--r--arch/arm/mach-versatile/core.c4
-rw-r--r--arch/arm/plat-omap/gpio.c8
57 files changed, 277 insertions, 277 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f3e020f2227..09b9d1b6844 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -160,7 +160,7 @@ void __init gic_dist_init(void __iomem *base)
160 */ 160 */
161 for (i = 29; i < max_irq; i++) { 161 for (i = 29; i < max_irq; i++) {
162 set_irq_chip(i, &gic_chip); 162 set_irq_chip(i, &gic_chip);
163 set_irq_handler(i, do_level_IRQ); 163 set_irq_handler(i, handle_level_irq);
164 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 164 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
165 } 165 }
166 166
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index 80a72c75214..cfe6f4650bc 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -163,11 +163,11 @@ static struct locomo_dev_info locomo_devices[] = {
163#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT) 163#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT)
164#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR) 164#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR)
165 165
166static void locomo_handler(unsigned int irq, struct irqdesc *desc) 166static void locomo_handler(unsigned int irq, struct irq_desc *desc)
167{ 167{
168 int req, i; 168 int req, i;
169 struct irqdesc *d; 169 struct irq_desc *d;
170 void __iomem *mapbase = get_irq_chipdata(irq); 170 void __iomem *mapbase = get_irq_chip_data(irq);
171 171
172 /* Acknowledge the parent IRQ */ 172 /* Acknowledge the parent IRQ */
173 desc->chip->ack(irq); 173 desc->chip->ack(irq);
@@ -194,7 +194,7 @@ static void locomo_ack_irq(unsigned int irq)
194 194
195static void locomo_mask_irq(unsigned int irq) 195static void locomo_mask_irq(unsigned int irq)
196{ 196{
197 void __iomem *mapbase = get_irq_chipdata(irq); 197 void __iomem *mapbase = get_irq_chip_data(irq);
198 unsigned int r; 198 unsigned int r;
199 r = locomo_readl(mapbase + LOCOMO_ICR); 199 r = locomo_readl(mapbase + LOCOMO_ICR);
200 r &= ~(0x0010 << (irq - LOCOMO_IRQ_START)); 200 r &= ~(0x0010 << (irq - LOCOMO_IRQ_START));
@@ -203,7 +203,7 @@ static void locomo_mask_irq(unsigned int irq)
203 203
204static void locomo_unmask_irq(unsigned int irq) 204static void locomo_unmask_irq(unsigned int irq)
205{ 205{
206 void __iomem *mapbase = get_irq_chipdata(irq); 206 void __iomem *mapbase = get_irq_chip_data(irq);
207 unsigned int r; 207 unsigned int r;
208 r = locomo_readl(mapbase + LOCOMO_ICR); 208 r = locomo_readl(mapbase + LOCOMO_ICR);
209 r |= (0x0010 << (irq - LOCOMO_IRQ_START)); 209 r |= (0x0010 << (irq - LOCOMO_IRQ_START));
@@ -217,10 +217,10 @@ static struct irq_chip locomo_chip = {
217 .unmask = locomo_unmask_irq, 217 .unmask = locomo_unmask_irq,
218}; 218};
219 219
220static void locomo_key_handler(unsigned int irq, struct irqdesc *desc) 220static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
221{ 221{
222 struct irqdesc *d; 222 struct irq_desc *d;
223 void __iomem *mapbase = get_irq_chipdata(irq); 223 void __iomem *mapbase = get_irq_chip_data(irq);
224 224
225 if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { 225 if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
226 d = irq_desc + LOCOMO_IRQ_KEY_START; 226 d = irq_desc + LOCOMO_IRQ_KEY_START;
@@ -230,7 +230,7 @@ static void locomo_key_handler(unsigned int irq, struct irqdesc *desc)
230 230
231static void locomo_key_ack_irq(unsigned int irq) 231static void locomo_key_ack_irq(unsigned int irq)
232{ 232{
233 void __iomem *mapbase = get_irq_chipdata(irq); 233 void __iomem *mapbase = get_irq_chip_data(irq);
234 unsigned int r; 234 unsigned int r;
235 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 235 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
236 r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); 236 r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START));
@@ -239,7 +239,7 @@ static void locomo_key_ack_irq(unsigned int irq)
239 239
240static void locomo_key_mask_irq(unsigned int irq) 240static void locomo_key_mask_irq(unsigned int irq)
241{ 241{
242 void __iomem *mapbase = get_irq_chipdata(irq); 242 void __iomem *mapbase = get_irq_chip_data(irq);
243 unsigned int r; 243 unsigned int r;
244 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 244 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
245 r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); 245 r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -248,7 +248,7 @@ static void locomo_key_mask_irq(unsigned int irq)
248 248
249static void locomo_key_unmask_irq(unsigned int irq) 249static void locomo_key_unmask_irq(unsigned int irq)
250{ 250{
251 void __iomem *mapbase = get_irq_chipdata(irq); 251 void __iomem *mapbase = get_irq_chip_data(irq);
252 unsigned int r; 252 unsigned int r;
253 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); 253 r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC);
254 r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); 254 r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START));
@@ -262,11 +262,11 @@ static struct irq_chip locomo_key_chip = {
262 .unmask = locomo_key_unmask_irq, 262 .unmask = locomo_key_unmask_irq,
263}; 263};
264 264
265static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc) 265static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
266{ 266{
267 int req, i; 267 int req, i;
268 struct irqdesc *d; 268 struct irq_desc *d;
269 void __iomem *mapbase = get_irq_chipdata(irq); 269 void __iomem *mapbase = get_irq_chip_data(irq);
270 270
271 req = locomo_readl(mapbase + LOCOMO_GIR) & 271 req = locomo_readl(mapbase + LOCOMO_GIR) &
272 locomo_readl(mapbase + LOCOMO_GPD) & 272 locomo_readl(mapbase + LOCOMO_GPD) &
@@ -285,7 +285,7 @@ static void locomo_gpio_handler(unsigned int irq, struct irqdesc *desc)
285 285
286static void locomo_gpio_ack_irq(unsigned int irq) 286static void locomo_gpio_ack_irq(unsigned int irq)
287{ 287{
288 void __iomem *mapbase = get_irq_chipdata(irq); 288 void __iomem *mapbase = get_irq_chip_data(irq);
289 unsigned int r; 289 unsigned int r;
290 r = locomo_readl(mapbase + LOCOMO_GWE); 290 r = locomo_readl(mapbase + LOCOMO_GWE);
291 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 291 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -302,7 +302,7 @@ static void locomo_gpio_ack_irq(unsigned int irq)
302 302
303static void locomo_gpio_mask_irq(unsigned int irq) 303static void locomo_gpio_mask_irq(unsigned int irq)
304{ 304{
305 void __iomem *mapbase = get_irq_chipdata(irq); 305 void __iomem *mapbase = get_irq_chip_data(irq);
306 unsigned int r; 306 unsigned int r;
307 r = locomo_readl(mapbase + LOCOMO_GIE); 307 r = locomo_readl(mapbase + LOCOMO_GIE);
308 r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 308 r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -311,7 +311,7 @@ static void locomo_gpio_mask_irq(unsigned int irq)
311 311
312static void locomo_gpio_unmask_irq(unsigned int irq) 312static void locomo_gpio_unmask_irq(unsigned int irq)
313{ 313{
314 void __iomem *mapbase = get_irq_chipdata(irq); 314 void __iomem *mapbase = get_irq_chip_data(irq);
315 unsigned int r; 315 unsigned int r;
316 r = locomo_readl(mapbase + LOCOMO_GIE); 316 r = locomo_readl(mapbase + LOCOMO_GIE);
317 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); 317 r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START));
@@ -325,10 +325,10 @@ static struct irq_chip locomo_gpio_chip = {
325 .unmask = locomo_gpio_unmask_irq, 325 .unmask = locomo_gpio_unmask_irq,
326}; 326};
327 327
328static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc) 328static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
329{ 329{
330 struct irqdesc *d; 330 struct irq_desc *d;
331 void __iomem *mapbase = get_irq_chipdata(irq); 331 void __iomem *mapbase = get_irq_chip_data(irq);
332 332
333 if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { 333 if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
334 d = irq_desc + LOCOMO_IRQ_LT_START; 334 d = irq_desc + LOCOMO_IRQ_LT_START;
@@ -338,7 +338,7 @@ static void locomo_lt_handler(unsigned int irq, struct irqdesc *desc)
338 338
339static void locomo_lt_ack_irq(unsigned int irq) 339static void locomo_lt_ack_irq(unsigned int irq)
340{ 340{
341 void __iomem *mapbase = get_irq_chipdata(irq); 341 void __iomem *mapbase = get_irq_chip_data(irq);
342 unsigned int r; 342 unsigned int r;
343 r = locomo_readl(mapbase + LOCOMO_LTINT); 343 r = locomo_readl(mapbase + LOCOMO_LTINT);
344 r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START)); 344 r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START));
@@ -347,7 +347,7 @@ static void locomo_lt_ack_irq(unsigned int irq)
347 347
348static void locomo_lt_mask_irq(unsigned int irq) 348static void locomo_lt_mask_irq(unsigned int irq)
349{ 349{
350 void __iomem *mapbase = get_irq_chipdata(irq); 350 void __iomem *mapbase = get_irq_chip_data(irq);
351 unsigned int r; 351 unsigned int r;
352 r = locomo_readl(mapbase + LOCOMO_LTINT); 352 r = locomo_readl(mapbase + LOCOMO_LTINT);
353 r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START)); 353 r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -356,7 +356,7 @@ static void locomo_lt_mask_irq(unsigned int irq)
356 356
357static void locomo_lt_unmask_irq(unsigned int irq) 357static void locomo_lt_unmask_irq(unsigned int irq)
358{ 358{
359 void __iomem *mapbase = get_irq_chipdata(irq); 359 void __iomem *mapbase = get_irq_chip_data(irq);
360 unsigned int r; 360 unsigned int r;
361 r = locomo_readl(mapbase + LOCOMO_LTINT); 361 r = locomo_readl(mapbase + LOCOMO_LTINT);
362 r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START)); 362 r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START));
@@ -370,11 +370,11 @@ static struct irq_chip locomo_lt_chip = {
370 .unmask = locomo_lt_unmask_irq, 370 .unmask = locomo_lt_unmask_irq,
371}; 371};
372 372
373static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc) 373static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
374{ 374{
375 int req, i; 375 int req, i;
376 struct irqdesc *d; 376 struct irq_desc *d;
377 void __iomem *mapbase = get_irq_chipdata(irq); 377 void __iomem *mapbase = get_irq_chip_data(irq);
378 378
379 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F; 379 req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
380 if (req) { 380 if (req) {
@@ -391,7 +391,7 @@ static void locomo_spi_handler(unsigned int irq, struct irqdesc *desc)
391 391
392static void locomo_spi_ack_irq(unsigned int irq) 392static void locomo_spi_ack_irq(unsigned int irq)
393{ 393{
394 void __iomem *mapbase = get_irq_chipdata(irq); 394 void __iomem *mapbase = get_irq_chip_data(irq);
395 unsigned int r; 395 unsigned int r;
396 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); 396 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE);
397 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 397 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -408,7 +408,7 @@ static void locomo_spi_ack_irq(unsigned int irq)
408 408
409static void locomo_spi_mask_irq(unsigned int irq) 409static void locomo_spi_mask_irq(unsigned int irq)
410{ 410{
411 void __iomem *mapbase = get_irq_chipdata(irq); 411 void __iomem *mapbase = get_irq_chip_data(irq);
412 unsigned int r; 412 unsigned int r;
413 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); 413 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
414 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 414 r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -417,7 +417,7 @@ static void locomo_spi_mask_irq(unsigned int irq)
417 417
418static void locomo_spi_unmask_irq(unsigned int irq) 418static void locomo_spi_unmask_irq(unsigned int irq)
419{ 419{
420 void __iomem *mapbase = get_irq_chipdata(irq); 420 void __iomem *mapbase = get_irq_chip_data(irq);
421 unsigned int r; 421 unsigned int r;
422 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); 422 r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE);
423 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); 423 r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START));
@@ -440,55 +440,55 @@ static void locomo_setup_irq(struct locomo *lchip)
440 * Install handler for IRQ_LOCOMO_HW. 440 * Install handler for IRQ_LOCOMO_HW.
441 */ 441 */
442 set_irq_type(lchip->irq, IRQT_FALLING); 442 set_irq_type(lchip->irq, IRQT_FALLING);
443 set_irq_chipdata(lchip->irq, irqbase); 443 set_irq_chip_data(lchip->irq, irqbase);
444 set_irq_chained_handler(lchip->irq, locomo_handler); 444 set_irq_chained_handler(lchip->irq, locomo_handler);
445 445
446 /* Install handlers for IRQ_LOCOMO_*_BASE */ 446 /* Install handlers for IRQ_LOCOMO_*_BASE */
447 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); 447 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
448 set_irq_chipdata(IRQ_LOCOMO_KEY_BASE, irqbase); 448 set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
449 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); 449 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
450 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE); 450 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
451 451
452 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); 452 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
453 set_irq_chipdata(IRQ_LOCOMO_GPIO_BASE, irqbase); 453 set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
454 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler); 454 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
455 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE); 455 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
456 456
457 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip); 457 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
458 set_irq_chipdata(IRQ_LOCOMO_LT_BASE, irqbase); 458 set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
459 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler); 459 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
460 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE); 460 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
461 461
462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip); 462 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
463 set_irq_chipdata(IRQ_LOCOMO_SPI_BASE, irqbase); 463 set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); 464 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
465 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE); 465 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
466 466
467 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ 467 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
468 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); 468 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
469 set_irq_chipdata(LOCOMO_IRQ_KEY_START, irqbase); 469 set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase);
470 set_irq_handler(LOCOMO_IRQ_KEY_START, do_edge_IRQ); 470 set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq);
471 set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE); 471 set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE);
472 472
473 /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */ 473 /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */
474 for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) { 474 for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) {
475 set_irq_chip(irq, &locomo_gpio_chip); 475 set_irq_chip(irq, &locomo_gpio_chip);
476 set_irq_chipdata(irq, irqbase); 476 set_irq_chip_data(irq, irqbase);
477 set_irq_handler(irq, do_edge_IRQ); 477 set_irq_handler(irq, handle_edge_irq);
478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 478 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
479 } 479 }
480 480
481 /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */ 481 /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */
482 set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip); 482 set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip);
483 set_irq_chipdata(LOCOMO_IRQ_LT_START, irqbase); 483 set_irq_chip_data(LOCOMO_IRQ_LT_START, irqbase);
484 set_irq_handler(LOCOMO_IRQ_LT_START, do_edge_IRQ); 484 set_irq_handler(LOCOMO_IRQ_LT_START, handle_edge_irq);
485 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE); 485 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
486 486
487 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */ 487 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
488 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) { 488 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) {
489 set_irq_chip(irq, &locomo_spi_chip); 489 set_irq_chip(irq, &locomo_spi_chip);
490 set_irq_chipdata(irq, irqbase); 490 set_irq_chip_data(irq, irqbase);
491 set_irq_handler(irq, do_edge_IRQ); 491 set_irq_handler(irq, handle_edge_irq);
492 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 492 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
493 } 493 }
494} 494}
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index d5f72010a6f..fe3f05901a2 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -147,7 +147,7 @@ void __init sa1111_adjust_zones(int node, unsigned long *size, unsigned long *ho
147 * will call us again if there are more interrupts to process. 147 * will call us again if there are more interrupts to process.
148 */ 148 */
149static void 149static void
150sa1111_irq_handler(unsigned int irq, struct irqdesc *desc) 150sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
151{ 151{
152 unsigned int stat0, stat1, i; 152 unsigned int stat0, stat1, i;
153 void __iomem *base = get_irq_data(irq); 153 void __iomem *base = get_irq_data(irq);
@@ -187,7 +187,7 @@ static void sa1111_ack_irq(unsigned int irq)
187 187
188static void sa1111_mask_lowirq(unsigned int irq) 188static void sa1111_mask_lowirq(unsigned int irq)
189{ 189{
190 void __iomem *mapbase = get_irq_chipdata(irq); 190 void __iomem *mapbase = get_irq_chip_data(irq);
191 unsigned long ie0; 191 unsigned long ie0;
192 192
193 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 193 ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -197,7 +197,7 @@ static void sa1111_mask_lowirq(unsigned int irq)
197 197
198static void sa1111_unmask_lowirq(unsigned int irq) 198static void sa1111_unmask_lowirq(unsigned int irq)
199{ 199{
200 void __iomem *mapbase = get_irq_chipdata(irq); 200 void __iomem *mapbase = get_irq_chip_data(irq);
201 unsigned long ie0; 201 unsigned long ie0;
202 202
203 ie0 = sa1111_readl(mapbase + SA1111_INTEN0); 203 ie0 = sa1111_readl(mapbase + SA1111_INTEN0);
@@ -215,7 +215,7 @@ static void sa1111_unmask_lowirq(unsigned int irq)
215static int sa1111_retrigger_lowirq(unsigned int irq) 215static int sa1111_retrigger_lowirq(unsigned int irq)
216{ 216{
217 unsigned int mask = SA1111_IRQMASK_LO(irq); 217 unsigned int mask = SA1111_IRQMASK_LO(irq);
218 void __iomem *mapbase = get_irq_chipdata(irq); 218 void __iomem *mapbase = get_irq_chip_data(irq);
219 unsigned long ip0; 219 unsigned long ip0;
220 int i; 220 int i;
221 221
@@ -236,7 +236,7 @@ static int sa1111_retrigger_lowirq(unsigned int irq)
236static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) 236static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
237{ 237{
238 unsigned int mask = SA1111_IRQMASK_LO(irq); 238 unsigned int mask = SA1111_IRQMASK_LO(irq);
239 void __iomem *mapbase = get_irq_chipdata(irq); 239 void __iomem *mapbase = get_irq_chip_data(irq);
240 unsigned long ip0; 240 unsigned long ip0;
241 241
242 if (flags == IRQT_PROBE) 242 if (flags == IRQT_PROBE)
@@ -259,7 +259,7 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags)
259static int sa1111_wake_lowirq(unsigned int irq, unsigned int on) 259static int sa1111_wake_lowirq(unsigned int irq, unsigned int on)
260{ 260{
261 unsigned int mask = SA1111_IRQMASK_LO(irq); 261 unsigned int mask = SA1111_IRQMASK_LO(irq);
262 void __iomem *mapbase = get_irq_chipdata(irq); 262 void __iomem *mapbase = get_irq_chip_data(irq);
263 unsigned long we0; 263 unsigned long we0;
264 264
265 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); 265 we0 = sa1111_readl(mapbase + SA1111_WAKEEN0);
@@ -284,7 +284,7 @@ static struct irq_chip sa1111_low_chip = {
284 284
285static void sa1111_mask_highirq(unsigned int irq) 285static void sa1111_mask_highirq(unsigned int irq)
286{ 286{
287 void __iomem *mapbase = get_irq_chipdata(irq); 287 void __iomem *mapbase = get_irq_chip_data(irq);
288 unsigned long ie1; 288 unsigned long ie1;
289 289
290 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 290 ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -294,7 +294,7 @@ static void sa1111_mask_highirq(unsigned int irq)
294 294
295static void sa1111_unmask_highirq(unsigned int irq) 295static void sa1111_unmask_highirq(unsigned int irq)
296{ 296{
297 void __iomem *mapbase = get_irq_chipdata(irq); 297 void __iomem *mapbase = get_irq_chip_data(irq);
298 unsigned long ie1; 298 unsigned long ie1;
299 299
300 ie1 = sa1111_readl(mapbase + SA1111_INTEN1); 300 ie1 = sa1111_readl(mapbase + SA1111_INTEN1);
@@ -312,7 +312,7 @@ static void sa1111_unmask_highirq(unsigned int irq)
312static int sa1111_retrigger_highirq(unsigned int irq) 312static int sa1111_retrigger_highirq(unsigned int irq)
313{ 313{
314 unsigned int mask = SA1111_IRQMASK_HI(irq); 314 unsigned int mask = SA1111_IRQMASK_HI(irq);
315 void __iomem *mapbase = get_irq_chipdata(irq); 315 void __iomem *mapbase = get_irq_chip_data(irq);
316 unsigned long ip1; 316 unsigned long ip1;
317 int i; 317 int i;
318 318
@@ -333,7 +333,7 @@ static int sa1111_retrigger_highirq(unsigned int irq)
333static int sa1111_type_highirq(unsigned int irq, unsigned int flags) 333static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
334{ 334{
335 unsigned int mask = SA1111_IRQMASK_HI(irq); 335 unsigned int mask = SA1111_IRQMASK_HI(irq);
336 void __iomem *mapbase = get_irq_chipdata(irq); 336 void __iomem *mapbase = get_irq_chip_data(irq);
337 unsigned long ip1; 337 unsigned long ip1;
338 338
339 if (flags == IRQT_PROBE) 339 if (flags == IRQT_PROBE)
@@ -356,7 +356,7 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags)
356static int sa1111_wake_highirq(unsigned int irq, unsigned int on) 356static int sa1111_wake_highirq(unsigned int irq, unsigned int on)
357{ 357{
358 unsigned int mask = SA1111_IRQMASK_HI(irq); 358 unsigned int mask = SA1111_IRQMASK_HI(irq);
359 void __iomem *mapbase = get_irq_chipdata(irq); 359 void __iomem *mapbase = get_irq_chip_data(irq);
360 unsigned long we1; 360 unsigned long we1;
361 361
362 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); 362 we1 = sa1111_readl(mapbase + SA1111_WAKEEN1);
@@ -410,15 +410,15 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
410 410
411 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { 411 for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
412 set_irq_chip(irq, &sa1111_low_chip); 412 set_irq_chip(irq, &sa1111_low_chip);
413 set_irq_chipdata(irq, irqbase); 413 set_irq_chip_data(irq, irqbase);
414 set_irq_handler(irq, do_edge_IRQ); 414 set_irq_handler(irq, handle_edge_irq);
415 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 415 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
416 } 416 }
417 417
418 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { 418 for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
419 set_irq_chip(irq, &sa1111_high_chip); 419 set_irq_chip(irq, &sa1111_high_chip);
420 set_irq_chipdata(irq, irqbase); 420 set_irq_chip_data(irq, irqbase);
421 set_irq_handler(irq, do_edge_IRQ); 421 set_irq_handler(irq, handle_edge_irq);
422 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 422 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
423 } 423 }
424 424
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 43d27813452..c026fa2214a 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -27,14 +27,14 @@
27 27
28static void vic_mask_irq(unsigned int irq) 28static void vic_mask_irq(unsigned int irq)
29{ 29{
30 void __iomem *base = get_irq_chipdata(irq); 30 void __iomem *base = get_irq_chip_data(irq);
31 irq &= 31; 31 irq &= 31;
32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); 32 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
33} 33}
34 34
35static void vic_unmask_irq(unsigned int irq) 35static void vic_unmask_irq(unsigned int irq)
36{ 36{
37 void __iomem *base = get_irq_chipdata(irq); 37 void __iomem *base = get_irq_chip_data(irq);
38 irq &= 31; 38 irq &= 31;
39 writel(1 << irq, base + VIC_INT_ENABLE); 39 writel(1 << irq, base + VIC_INT_ENABLE);
40} 40}
@@ -88,10 +88,10 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
88 unsigned int irq = irq_start + i; 88 unsigned int irq = irq_start + i;
89 89
90 set_irq_chip(irq, &vic_chip); 90 set_irq_chip(irq, &vic_chip);
91 set_irq_chipdata(irq, base); 91 set_irq_chip_data(irq, base);
92 92
93 if (vic_sources & (1 << i)) { 93 if (vic_sources & (1 << i)) {
94 set_irq_handler(irq, do_level_IRQ); 94 set_irq_handler(irq, handle_level_irq);
95 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 95 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
96 } 96 }
97 } 97 }
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index b27513a0f11..a786f769035 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -529,7 +529,7 @@ static void ecard_dump_irq_state(void)
529 } 529 }
530} 530}
531 531
532static void ecard_check_lockup(struct irqdesc *desc) 532static void ecard_check_lockup(struct irq_desc *desc)
533{ 533{
534 static unsigned long last; 534 static unsigned long last;
535 static int lockup; 535 static int lockup;
@@ -567,7 +567,7 @@ static void ecard_check_lockup(struct irqdesc *desc)
567} 567}
568 568
569static void 569static void
570ecard_irq_handler(unsigned int irq, struct irqdesc *desc) 570ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
571{ 571{
572 ecard_t *ec; 572 ecard_t *ec;
573 int called = 0; 573 int called = 0;
@@ -585,7 +585,7 @@ ecard_irq_handler(unsigned int irq, struct irqdesc *desc)
585 pending = ecard_default_ops.irqpending(ec); 585 pending = ecard_default_ops.irqpending(ec);
586 586
587 if (pending) { 587 if (pending) {
588 struct irqdesc *d = irq_desc + ec->irq; 588 struct irq_desc *d = irq_desc + ec->irq;
589 desc_handle_irq(ec->irq, d); 589 desc_handle_irq(ec->irq, d);
590 called ++; 590 called ++;
591 } 591 }
@@ -609,7 +609,7 @@ static unsigned char first_set[] =
609}; 609};
610 610
611static void 611static void
612ecard_irqexp_handler(unsigned int irq, struct irqdesc *desc) 612ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
613{ 613{
614 const unsigned int statusmask = 15; 614 const unsigned int statusmask = 15;
615 unsigned int status; 615 unsigned int status;
@@ -1022,7 +1022,7 @@ ecard_probe(int slot, card_type_t type)
1022 if (slot < 8) { 1022 if (slot < 8) {
1023 ec->irq = 32 + slot; 1023 ec->irq = 32 + slot;
1024 set_irq_chip(ec->irq, &ecard_chip); 1024 set_irq_chip(ec->irq, &ecard_chip);
1025 set_irq_handler(ec->irq, do_level_IRQ); 1025 set_irq_handler(ec->irq, handle_level_irq);
1026 set_irq_flags(ec->irq, IRQF_VALID); 1026 set_irq_flags(ec->irq, IRQF_VALID);
1027 } 1027 }
1028 1028
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c4ff1cbe33..ec01f08f564 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -112,7 +112,7 @@ static struct irq_desc bad_irq_desc = {
112asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) 112asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
113{ 113{
114 struct pt_regs *old_regs = set_irq_regs(regs); 114 struct pt_regs *old_regs = set_irq_regs(regs);
115 struct irqdesc *desc = irq_desc + irq; 115 struct irq_desc *desc = irq_desc + irq;
116 116
117 /* 117 /*
118 * Some hardware gives randomly wrong interrupts. Rather 118 * Some hardware gives randomly wrong interrupts. Rather
@@ -134,7 +134,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
134 134
135void set_irq_flags(unsigned int irq, unsigned int iflags) 135void set_irq_flags(unsigned int irq, unsigned int iflags)
136{ 136{
137 struct irqdesc *desc; 137 struct irq_desc *desc;
138 unsigned long flags; 138 unsigned long flags;
139 139
140 if (irq >= NR_IRQS) { 140 if (irq >= NR_IRQS) {
@@ -171,7 +171,7 @@ void __init init_IRQ(void)
171 171
172#ifdef CONFIG_HOTPLUG_CPU 172#ifdef CONFIG_HOTPLUG_CPU
173 173
174static void route_irq(struct irqdesc *desc, unsigned int irq, unsigned int cpu) 174static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
175{ 175{
176 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu); 176 pr_debug("IRQ%u: moving from cpu%u to cpu%u\n", irq, desc->cpu, cpu);
177 177
@@ -190,7 +190,7 @@ void migrate_irqs(void)
190 unsigned int i, cpu = smp_processor_id(); 190 unsigned int i, cpu = smp_processor_id();
191 191
192 for (i = 0; i < NR_IRQS; i++) { 192 for (i = 0; i < NR_IRQS; i++) {
193 struct irqdesc *desc = irq_desc + i; 193 struct irq_desc *desc = irq_desc + i;
194 194
195 if (desc->cpu == cpu) { 195 if (desc->cpu == cpu) {
196 unsigned int newcpu = any_online_cpu(desc->affinity); 196 unsigned int newcpu = any_online_cpu(desc->affinity);
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
index fe3d297d682..a950160fcfb 100644
--- a/arch/arm/mach-aaec2000/core.c
+++ b/arch/arm/mach-aaec2000/core.c
@@ -82,7 +82,7 @@ static void aaec2000_int_unmask(unsigned int irq)
82 IRQ_INTENS |= (1 << irq); 82 IRQ_INTENS |= (1 << irq);
83} 83}
84 84
85static struct irqchip aaec2000_irq_chip = { 85static struct irq_chip aaec2000_irq_chip = {
86 .ack = aaec2000_int_ack, 86 .ack = aaec2000_int_ack,
87 .mask = aaec2000_int_mask, 87 .mask = aaec2000_int_mask,
88 .unmask = aaec2000_int_unmask, 88 .unmask = aaec2000_int_unmask,
@@ -93,7 +93,7 @@ void __init aaec2000_init_irq(void)
93 unsigned int i; 93 unsigned int i;
94 94
95 for (i = 0; i < NR_IRQS; i++) { 95 for (i = 0; i < NR_IRQS; i++) {
96 set_irq_handler(i, do_level_IRQ); 96 set_irq_handler(i, handle_level_irq);
97 set_irq_chip(i, &aaec2000_irq_chip); 97 set_irq_chip(i, &aaec2000_irq_chip);
98 set_irq_flags(i, IRQF_VALID); 98 set_irq_flags(i, IRQF_VALID);
99 } 99 }
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index 7467d644f0a..cec3862651d 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -332,10 +332,10 @@ static struct irq_chip gpio_irqchip = {
332 .set_wake = gpio_irq_set_wake, 332 .set_wake = gpio_irq_set_wake,
333}; 333};
334 334
335static void gpio_irq_handler(unsigned irq, struct irqdesc *desc) 335static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
336{ 336{
337 unsigned pin; 337 unsigned pin;
338 struct irqdesc *gpio; 338 struct irq_desc *gpio;
339 void __iomem *pio; 339 void __iomem *pio;
340 u32 isr; 340 u32 isr;
341 341
@@ -396,7 +396,7 @@ void __init at91_gpio_irq_setup(void)
396 __raw_writel(~0, controller + PIO_IDR); 396 __raw_writel(~0, controller + PIO_IDR);
397 397
398 set_irq_data(id, (void *) pin); 398 set_irq_data(id, (void *) pin);
399 set_irq_chipdata(id, controller); 399 set_irq_chip_data(id, controller);
400 400
401 for (i = 0; i < 32; i++, pin++) { 401 for (i = 0; i < 32; i++, pin++) {
402 /* 402 /*
@@ -404,7 +404,7 @@ void __init at91_gpio_irq_setup(void)
404 * shorter, and the AIC handles interupts sanely. 404 * shorter, and the AIC handles interupts sanely.
405 */ 405 */
406 set_irq_chip(pin, &gpio_irqchip); 406 set_irq_chip(pin, &gpio_irqchip);
407 set_irq_handler(pin, do_simple_IRQ); 407 set_irq_handler(pin, handle_simple_irq);
408 set_irq_flags(pin, IRQF_VALID); 408 set_irq_flags(pin, IRQF_VALID);
409 } 409 }
410 410
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index 3e488117ca9..cab0de9b8fa 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -139,7 +139,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
139 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 139 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
140 140
141 set_irq_chip(i, &at91_aic_chip); 141 set_irq_chip(i, &at91_aic_chip);
142 set_irq_handler(i, do_level_IRQ); 142 set_irq_handler(i, handle_level_irq);
143 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 143 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
144 144
145 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ 145 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 7ee926e5bad..ca102960f52 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -63,7 +63,7 @@ static void int1_unmask(unsigned int irq)
63 clps_writel(intmr1, INTMR1); 63 clps_writel(intmr1, INTMR1);
64} 64}
65 65
66static struct irqchip int1_chip = { 66static struct irq_chip int1_chip = {
67 .ack = int1_ack, 67 .ack = int1_ack,
68 .mask = int1_mask, 68 .mask = int1_mask,
69 .unmask = int1_unmask, 69 .unmask = int1_unmask,
@@ -100,7 +100,7 @@ static void int2_unmask(unsigned int irq)
100 clps_writel(intmr2, INTMR2); 100 clps_writel(intmr2, INTMR2);
101} 101}
102 102
103static struct irqchip int2_chip = { 103static struct irq_chip int2_chip = {
104 .ack = int2_ack, 104 .ack = int2_ack,
105 .mask = int2_mask, 105 .mask = int2_mask,
106 .unmask = int2_unmask, 106 .unmask = int2_unmask,
@@ -112,12 +112,12 @@ void __init clps711x_init_irq(void)
112 112
113 for (i = 0; i < NR_IRQS; i++) { 113 for (i = 0; i < NR_IRQS; i++) {
114 if (INT1_IRQS & (1 << i)) { 114 if (INT1_IRQS & (1 << i)) {
115 set_irq_handler(i, do_level_IRQ); 115 set_irq_handler(i, handle_level_irq);
116 set_irq_chip(i, &int1_chip); 116 set_irq_chip(i, &int1_chip);
117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 117 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
118 } 118 }
119 if (INT2_IRQS & (1 << i)) { 119 if (INT2_IRQS & (1 << i)) {
120 set_irq_handler(i, do_level_IRQ); 120 set_irq_handler(i, handle_level_irq);
121 set_irq_chip(i, &int2_chip); 121 set_irq_chip(i, &int2_chip);
122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 122 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
123 } 123 }
diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c
index fb10cf25258..231b9000473 100644
--- a/arch/arm/mach-clps7500/core.c
+++ b/arch/arm/mach-clps7500/core.c
@@ -57,7 +57,7 @@ static void cl7500_unmask_irq_a(unsigned int irq)
57 iomd_writeb(val | mask, IOMD_IRQMASKA); 57 iomd_writeb(val | mask, IOMD_IRQMASKA);
58} 58}
59 59
60static struct irqchip clps7500_a_chip = { 60static struct irq_chip clps7500_a_chip = {
61 .ack = cl7500_ack_irq_a, 61 .ack = cl7500_ack_irq_a,
62 .mask = cl7500_mask_irq_a, 62 .mask = cl7500_mask_irq_a,
63 .unmask = cl7500_unmask_irq_a, 63 .unmask = cl7500_unmask_irq_a,
@@ -81,7 +81,7 @@ static void cl7500_unmask_irq_b(unsigned int irq)
81 iomd_writeb(val | mask, IOMD_IRQMASKB); 81 iomd_writeb(val | mask, IOMD_IRQMASKB);
82} 82}
83 83
84static struct irqchip clps7500_b_chip = { 84static struct irq_chip clps7500_b_chip = {
85 .ack = cl7500_mask_irq_b, 85 .ack = cl7500_mask_irq_b,
86 .mask = cl7500_mask_irq_b, 86 .mask = cl7500_mask_irq_b,
87 .unmask = cl7500_unmask_irq_b, 87 .unmask = cl7500_unmask_irq_b,
@@ -105,7 +105,7 @@ static void cl7500_unmask_irq_c(unsigned int irq)
105 iomd_writeb(val | mask, IOMD_IRQMASKC); 105 iomd_writeb(val | mask, IOMD_IRQMASKC);
106} 106}
107 107
108static struct irqchip clps7500_c_chip = { 108static struct irq_chip clps7500_c_chip = {
109 .ack = cl7500_mask_irq_c, 109 .ack = cl7500_mask_irq_c,
110 .mask = cl7500_mask_irq_c, 110 .mask = cl7500_mask_irq_c,
111 .unmask = cl7500_unmask_irq_c, 111 .unmask = cl7500_unmask_irq_c,
@@ -129,7 +129,7 @@ static void cl7500_unmask_irq_d(unsigned int irq)
129 iomd_writeb(val | mask, IOMD_IRQMASKD); 129 iomd_writeb(val | mask, IOMD_IRQMASKD);
130} 130}
131 131
132static struct irqchip clps7500_d_chip = { 132static struct irq_chip clps7500_d_chip = {
133 .ack = cl7500_mask_irq_d, 133 .ack = cl7500_mask_irq_d,
134 .mask = cl7500_mask_irq_d, 134 .mask = cl7500_mask_irq_d,
135 .unmask = cl7500_unmask_irq_d, 135 .unmask = cl7500_unmask_irq_d,
@@ -153,7 +153,7 @@ static void cl7500_unmask_irq_dma(unsigned int irq)
153 iomd_writeb(val | mask, IOMD_DMAMASK); 153 iomd_writeb(val | mask, IOMD_DMAMASK);
154} 154}
155 155
156static struct irqchip clps7500_dma_chip = { 156static struct irq_chip clps7500_dma_chip = {
157 .ack = cl7500_mask_irq_dma, 157 .ack = cl7500_mask_irq_dma,
158 .mask = cl7500_mask_irq_dma, 158 .mask = cl7500_mask_irq_dma,
159 .unmask = cl7500_unmask_irq_dma, 159 .unmask = cl7500_unmask_irq_dma,
@@ -177,7 +177,7 @@ static void cl7500_unmask_irq_fiq(unsigned int irq)
177 iomd_writeb(val | mask, IOMD_FIQMASK); 177 iomd_writeb(val | mask, IOMD_FIQMASK);
178} 178}
179 179
180static struct irqchip clps7500_fiq_chip = { 180static struct irq_chip clps7500_fiq_chip = {
181 .ack = cl7500_mask_irq_fiq, 181 .ack = cl7500_mask_irq_fiq,
182 .mask = cl7500_mask_irq_fiq, 182 .mask = cl7500_mask_irq_fiq,
183 .unmask = cl7500_unmask_irq_fiq, 183 .unmask = cl7500_unmask_irq_fiq,
@@ -187,7 +187,7 @@ static void cl7500_no_action(unsigned int irq)
187{ 187{
188} 188}
189 189
190static struct irqchip clps7500_no_chip = { 190static struct irq_chip clps7500_no_chip = {
191 .ack = cl7500_no_action, 191 .ack = cl7500_no_action,
192 .mask = cl7500_no_action, 192 .mask = cl7500_no_action,
193 .unmask = cl7500_no_action, 193 .unmask = cl7500_no_action,
@@ -214,43 +214,43 @@ static void __init clps7500_init_irq(void)
214 switch (irq) { 214 switch (irq) {
215 case 0 ... 7: 215 case 0 ... 7:
216 set_irq_chip(irq, &clps7500_a_chip); 216 set_irq_chip(irq, &clps7500_a_chip);
217 set_irq_handler(irq, do_level_IRQ); 217 set_irq_handler(irq, handle_level_irq);
218 set_irq_flags(irq, flags); 218 set_irq_flags(irq, flags);
219 break; 219 break;
220 220
221 case 8 ... 15: 221 case 8 ... 15:
222 set_irq_chip(irq, &clps7500_b_chip); 222 set_irq_chip(irq, &clps7500_b_chip);
223 set_irq_handler(irq, do_level_IRQ); 223 set_irq_handler(irq, handle_level_irq);
224 set_irq_flags(irq, flags); 224 set_irq_flags(irq, flags);
225 break; 225 break;
226 226
227 case 16 ... 22: 227 case 16 ... 22:
228 set_irq_chip(irq, &clps7500_dma_chip); 228 set_irq_chip(irq, &clps7500_dma_chip);
229 set_irq_handler(irq, do_level_IRQ); 229 set_irq_handler(irq, handle_level_irq);
230 set_irq_flags(irq, flags); 230 set_irq_flags(irq, flags);
231 break; 231 break;
232 232
233 case 24 ... 31: 233 case 24 ... 31:
234 set_irq_chip(irq, &clps7500_c_chip); 234 set_irq_chip(irq, &clps7500_c_chip);
235 set_irq_handler(irq, do_level_IRQ); 235 set_irq_handler(irq, handle_level_irq);
236 set_irq_flags(irq, flags); 236 set_irq_flags(irq, flags);
237 break; 237 break;
238 238
239 case 40 ... 47: 239 case 40 ... 47:
240 set_irq_chip(irq, &clps7500_d_chip); 240 set_irq_chip(irq, &clps7500_d_chip);
241 set_irq_handler(irq, do_level_IRQ); 241 set_irq_handler(irq, handle_level_irq);
242 set_irq_flags(irq, flags); 242 set_irq_flags(irq, flags);
243 break; 243 break;
244 244
245 case 48 ... 55: 245 case 48 ... 55:
246 set_irq_chip(irq, &clps7500_no_chip); 246 set_irq_chip(irq, &clps7500_no_chip);
247 set_irq_handler(irq, do_level_IRQ); 247 set_irq_handler(irq, handle_level_irq);
248 set_irq_flags(irq, flags); 248 set_irq_flags(irq, flags);
249 break; 249 break;
250 250
251 case 64 ... 72: 251 case 64 ... 72:
252 set_irq_chip(irq, &clps7500_fiq_chip); 252 set_irq_chip(irq, &clps7500_fiq_chip);
253 set_irq_handler(irq, do_level_IRQ); 253 set_irq_handler(irq, handle_level_irq);
254 set_irq_flags(irq, flags); 254 set_irq_flags(irq, flags);
255 break; 255 break;
256 } 256 }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 90103ab373a..8459431cfd7 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -45,7 +45,7 @@ static void ebsa110_unmask_irq(unsigned int irq)
45 __raw_writeb(1 << irq, IRQ_MSET); 45 __raw_writeb(1 << irq, IRQ_MSET);
46} 46}
47 47
48static struct irqchip ebsa110_irq_chip = { 48static struct irq_chip ebsa110_irq_chip = {
49 .ack = ebsa110_mask_irq, 49 .ack = ebsa110_mask_irq,
50 .mask = ebsa110_mask_irq, 50 .mask = ebsa110_mask_irq,
51 .unmask = ebsa110_unmask_irq, 51 .unmask = ebsa110_unmask_irq,
@@ -67,7 +67,7 @@ static void __init ebsa110_init_irq(void)
67 67
68 for (irq = 0; irq < NR_IRQS; irq++) { 68 for (irq = 0; irq < NR_IRQS; irq++) {
69 set_irq_chip(irq, &ebsa110_irq_chip); 69 set_irq_chip(irq, &ebsa110_irq_chip);
70 set_irq_handler(irq, do_level_IRQ); 70 set_irq_handler(irq, handle_level_irq);
71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 71 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
72 } 72 }
73} 73}
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index e3fd1ab6adc..d649b39711d 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -245,7 +245,7 @@ EXPORT_SYMBOL(gpio_line_set);
245 * EP93xx IRQ handling 245 * EP93xx IRQ handling
246 *************************************************************************/ 246 *************************************************************************/
247static void ep93xx_gpio_ab_irq_handler(unsigned int irq, 247static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
248 struct irqdesc *desc) 248 struct irq_desc *desc)
249{ 249{
250 unsigned char status; 250 unsigned char status;
251 int i; 251 int i;
@@ -335,7 +335,7 @@ static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
335 return 0; 335 return 0;
336} 336}
337 337
338static struct irqchip ep93xx_gpio_ab_irq_chip = { 338static struct irq_chip ep93xx_gpio_ab_irq_chip = {
339 .ack = ep93xx_gpio_ab_irq_mask_ack, 339 .ack = ep93xx_gpio_ab_irq_mask_ack,
340 .mask = ep93xx_gpio_ab_irq_mask, 340 .mask = ep93xx_gpio_ab_irq_mask,
341 .unmask = ep93xx_gpio_ab_irq_unmask, 341 .unmask = ep93xx_gpio_ab_irq_unmask,
@@ -352,7 +352,7 @@ void __init ep93xx_init_irq(void)
352 352
353 for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) { 353 for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
354 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip); 354 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
355 set_irq_handler(irq, do_level_IRQ); 355 set_irq_handler(irq, handle_level_irq);
356 set_irq_flags(irq, IRQF_VALID); 356 set_irq_flags(irq, IRQF_VALID);
357 } 357 }
358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); 358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index af900f4755a..ef29fc34ce6 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -78,7 +78,7 @@ static void fb_unmask_irq(unsigned int irq)
78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)]; 78 *CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(irq)];
79} 79}
80 80
81static struct irqchip fb_chip = { 81static struct irq_chip fb_chip = {
82 .ack = fb_mask_irq, 82 .ack = fb_mask_irq,
83 .mask = fb_mask_irq, 83 .mask = fb_mask_irq,
84 .unmask = fb_unmask_irq, 84 .unmask = fb_unmask_irq,
@@ -96,7 +96,7 @@ static void __init __fb_init_irq(void)
96 96
97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { 97 for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
98 set_irq_chip(irq, &fb_chip); 98 set_irq_chip(irq, &fb_chip);
99 set_irq_handler(irq, do_level_IRQ); 99 set_irq_handler(irq, handle_level_irq);
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
101 } 101 }
102} 102}
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 888dedd501b..79443ffc891 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -49,7 +49,7 @@ static void isa_unmask_pic_lo_irq(unsigned int irq)
49 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); 49 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
50} 50}
51 51
52static struct irqchip isa_lo_chip = { 52static struct irq_chip isa_lo_chip = {
53 .ack = isa_ack_pic_lo_irq, 53 .ack = isa_ack_pic_lo_irq,
54 .mask = isa_mask_pic_lo_irq, 54 .mask = isa_mask_pic_lo_irq,
55 .unmask = isa_unmask_pic_lo_irq, 55 .unmask = isa_unmask_pic_lo_irq,
@@ -78,14 +78,14 @@ static void isa_unmask_pic_hi_irq(unsigned int irq)
78 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); 78 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
79} 79}
80 80
81static struct irqchip isa_hi_chip = { 81static struct irq_chip isa_hi_chip = {
82 .ack = isa_ack_pic_hi_irq, 82 .ack = isa_ack_pic_hi_irq,
83 .mask = isa_mask_pic_hi_irq, 83 .mask = isa_mask_pic_hi_irq,
84 .unmask = isa_unmask_pic_hi_irq, 84 .unmask = isa_unmask_pic_hi_irq,
85}; 85};
86 86
87static void 87static void
88isa_irq_handler(unsigned int irq, struct irqdesc *desc) 88isa_irq_handler(unsigned int irq, struct irq_desc *desc)
89{ 89{
90 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE; 90 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
91 91
@@ -150,13 +150,13 @@ void __init isa_init_irq(unsigned int host_irq)
150 if (host_irq != (unsigned int)-1) { 150 if (host_irq != (unsigned int)-1) {
151 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { 151 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
152 set_irq_chip(irq, &isa_lo_chip); 152 set_irq_chip(irq, &isa_lo_chip);
153 set_irq_handler(irq, do_level_IRQ); 153 set_irq_handler(irq, handle_level_irq);
154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 154 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
155 } 155 }
156 156
157 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { 157 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
158 set_irq_chip(irq, &isa_hi_chip); 158 set_irq_chip(irq, &isa_hi_chip);
159 set_irq_handler(irq, do_level_IRQ); 159 set_irq_handler(irq, handle_level_irq);
160 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 160 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
161 } 161 }
162 162
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 4719229a1a7..7f31816896a 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -101,7 +101,7 @@ static void inline unmask_gpio_irq(u32 irq)
101 101
102static void 102static void
103h720x_gpio_handler(unsigned int mask, unsigned int irq, 103h720x_gpio_handler(unsigned int mask, unsigned int irq,
104 struct irqdesc *desc) 104 struct irq_desc *desc)
105{ 105{
106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq); 106 IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
107 desc = irq_desc + irq; 107 desc = irq_desc + irq;
@@ -117,7 +117,7 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
117} 117}
118 118
119static void 119static void
120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 120h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
121{ 121{
122 unsigned int mask, irq; 122 unsigned int mask, irq;
123 123
@@ -128,7 +128,7 @@ h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
128} 128}
129 129
130static void 130static void
131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 131h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
132{ 132{
133 unsigned int mask, irq; 133 unsigned int mask, irq;
134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 134 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
@@ -138,7 +138,7 @@ h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
138} 138}
139 139
140static void 140static void
141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 141h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
142{ 142{
143 unsigned int mask, irq; 143 unsigned int mask, irq;
144 144
@@ -149,7 +149,7 @@ h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
149} 149}
150 150
151static void 151static void
152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 152h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
153{ 153{
154 unsigned int mask, irq; 154 unsigned int mask, irq;
155 155
@@ -161,7 +161,7 @@ h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
161 161
162#ifdef CONFIG_CPU_H7202 162#ifdef CONFIG_CPU_H7202
163static void 163static void
164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 164h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
165{ 165{
166 unsigned int mask, irq; 166 unsigned int mask, irq;
167 167
@@ -172,13 +172,13 @@ h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
172} 172}
173#endif 173#endif
174 174
175static struct irqchip h720x_global_chip = { 175static struct irq_chip h720x_global_chip = {
176 .ack = mask_global_irq, 176 .ack = mask_global_irq,
177 .mask = mask_global_irq, 177 .mask = mask_global_irq,
178 .unmask = unmask_global_irq, 178 .unmask = unmask_global_irq,
179}; 179};
180 180
181static struct irqchip h720x_gpio_chip = { 181static struct irq_chip h720x_gpio_chip = {
182 .ack = ack_gpio_irq, 182 .ack = ack_gpio_irq,
183 .mask = mask_gpio_irq, 183 .mask = mask_gpio_irq,
184 .unmask = unmask_gpio_irq, 184 .unmask = unmask_gpio_irq,
@@ -203,14 +203,14 @@ void __init h720x_init_irq (void)
203 /* Initialize global IRQ's, fast path */ 203 /* Initialize global IRQ's, fast path */
204 for (irq = 0; irq < NR_GLBL_IRQS; irq++) { 204 for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
205 set_irq_chip(irq, &h720x_global_chip); 205 set_irq_chip(irq, &h720x_global_chip);
206 set_irq_handler(irq, do_level_IRQ); 206 set_irq_handler(irq, handle_level_irq);
207 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 207 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
208 } 208 }
209 209
210 /* Initialize multiplexed IRQ's, slow path */ 210 /* Initialize multiplexed IRQ's, slow path */
211 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { 211 for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
212 set_irq_chip(irq, &h720x_gpio_chip); 212 set_irq_chip(irq, &h720x_gpio_chip);
213 set_irq_handler(irq, do_edge_IRQ); 213 set_irq_handler(irq, handle_edge_irq);
214 set_irq_flags(irq, IRQF_VALID ); 214 set_irq_flags(irq, IRQF_VALID );
215 } 215 }
216 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); 216 set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
@@ -221,7 +221,7 @@ void __init h720x_init_irq (void)
221#ifdef CONFIG_CPU_H7202 221#ifdef CONFIG_CPU_H7202
222 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { 222 for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
223 set_irq_chip(irq, &h720x_gpio_chip); 223 set_irq_chip(irq, &h720x_gpio_chip);
224 set_irq_handler(irq, do_edge_IRQ); 224 set_irq_handler(irq, handle_edge_irq);
225 set_irq_flags(irq, IRQF_VALID ); 225 set_irq_flags(irq, IRQF_VALID );
226 } 226 }
227 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); 227 set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index 06fecaefd8d..703870f30ad 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -106,7 +106,7 @@ static struct platform_device *devices[] __initdata = {
106 * we have to handle all timer interrupts in one place. 106 * we have to handle all timer interrupts in one place.
107 */ 107 */
108static void 108static void
109h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 109h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
110{ 110{
111 unsigned int mask, irq; 111 unsigned int mask, irq;
112 112
@@ -162,7 +162,7 @@ static void inline unmask_timerx_irq (u32 irq)
162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; 162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
163} 163}
164 164
165static struct irqchip h7202_timerx_chip = { 165static struct irq_chip h7202_timerx_chip = {
166 .ack = mask_timerx_irq, 166 .ack = mask_timerx_irq,
167 .mask = mask_timerx_irq, 167 .mask = mask_timerx_irq,
168 .unmask = unmask_timerx_irq, 168 .unmask = unmask_timerx_irq,
@@ -202,7 +202,7 @@ void __init h7202_init_irq (void)
202 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { 202 irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
203 mask_timerx_irq(irq); 203 mask_timerx_irq(irq);
204 set_irq_chip(irq, &h7202_timerx_chip); 204 set_irq_chip(irq, &h7202_timerx_chip);
205 set_irq_handler(irq, do_edge_IRQ); 205 set_irq_handler(irq, handle_edge_irq);
206 set_irq_flags(irq, IRQF_VALID ); 206 set_irq_flags(irq, IRQF_VALID );
207 } 207 }
208 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); 208 set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 368b13b058a..0791b56caec 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -146,7 +146,7 @@ imx_gpio_unmask_irq(unsigned int irq)
146 146
147static void 147static void
148imx_gpio_handler(unsigned int mask, unsigned int irq, 148imx_gpio_handler(unsigned int mask, unsigned int irq,
149 struct irqdesc *desc) 149 struct irq_desc *desc)
150{ 150{
151 desc = irq_desc + irq; 151 desc = irq_desc + irq;
152 while (mask) { 152 while (mask) {
@@ -161,7 +161,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq,
161} 161}
162 162
163static void 163static void
164imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 164imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
165{ 165{
166 unsigned int mask, irq; 166 unsigned int mask, irq;
167 167
@@ -171,7 +171,7 @@ imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
171} 171}
172 172
173static void 173static void
174imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 174imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
175{ 175{
176 unsigned int mask, irq; 176 unsigned int mask, irq;
177 177
@@ -181,7 +181,7 @@ imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
181} 181}
182 182
183static void 183static void
184imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 184imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
185{ 185{
186 unsigned int mask, irq; 186 unsigned int mask, irq;
187 187
@@ -191,7 +191,7 @@ imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
191} 191}
192 192
193static void 193static void
194imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 194imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
195{ 195{
196 unsigned int mask, irq; 196 unsigned int mask, irq;
197 197
@@ -230,13 +230,13 @@ imx_init_irq(void)
230 230
231 for (irq = 0; irq < IMX_IRQS; irq++) { 231 for (irq = 0; irq < IMX_IRQS; irq++) {
232 set_irq_chip(irq, &imx_internal_chip); 232 set_irq_chip(irq, &imx_internal_chip);
233 set_irq_handler(irq, do_level_IRQ); 233 set_irq_handler(irq, handle_level_irq);
234 set_irq_flags(irq, IRQF_VALID); 234 set_irq_flags(irq, IRQF_VALID);
235 } 235 }
236 236
237 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { 237 for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
238 set_irq_chip(irq, &imx_gpio_chip); 238 set_irq_chip(irq, &imx_gpio_chip);
239 set_irq_handler(irq, do_edge_IRQ); 239 set_irq_handler(irq, handle_edge_irq);
240 set_irq_flags(irq, IRQF_VALID); 240 set_irq_flags(irq, IRQF_VALID);
241 } 241 }
242 242
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 191c57a3b99..72280754354 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -183,7 +183,7 @@ static void __init ap_init_irq(void)
183 for (i = 0; i < NR_IRQS; i++) { 183 for (i = 0; i < NR_IRQS; i++) {
184 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) { 184 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
185 set_irq_chip(i, &sc_chip); 185 set_irq_chip(i, &sc_chip);
186 set_irq_handler(i, do_level_IRQ); 186 set_irq_handler(i, handle_level_irq);
187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 187 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
188 } 188 }
189 } 189 }
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 771b65bffe6..913f64b2240 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -202,7 +202,7 @@ static struct irq_chip sic_chip = {
202}; 202};
203 203
204static void 204static void
205sic_handle_irq(unsigned int irq, struct irqdesc *desc) 205sic_handle_irq(unsigned int irq, struct irq_desc *desc)
206{ 206{
207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); 207 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
208 208
@@ -238,7 +238,7 @@ static void __init intcp_init_irq(void)
238 if (i == 29) 238 if (i == 29)
239 break; 239 break;
240 set_irq_chip(i, &pic_chip); 240 set_irq_chip(i, &pic_chip);
241 set_irq_handler(i, do_level_IRQ); 241 set_irq_handler(i, handle_level_irq);
242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
243 } 243 }
244 244
@@ -247,7 +247,7 @@ static void __init intcp_init_irq(void)
247 247
248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { 248 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
249 set_irq_chip(i, &cic_chip); 249 set_irq_chip(i, &cic_chip);
250 set_irq_handler(i, do_level_IRQ); 250 set_irq_handler(i, handle_level_irq);
251 set_irq_flags(i, IRQF_VALID); 251 set_irq_flags(i, IRQF_VALID);
252 } 252 }
253 253
@@ -256,7 +256,7 @@ static void __init intcp_init_irq(void)
256 256
257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 257 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
258 set_irq_chip(i, &sic_chip); 258 set_irq_chip(i, &sic_chip);
259 set_irq_handler(i, do_level_IRQ); 259 set_irq_handler(i, handle_level_irq);
260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 260 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
261 } 261 }
262 262
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 69d6302f40c..3ec1cd5c4f9 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -70,7 +70,7 @@ void __init iop32x_init_irq(void)
70 70
71 for (i = 0; i < NR_IRQS; i++) { 71 for (i = 0; i < NR_IRQS; i++) {
72 set_irq_chip(i, &ext_chip); 72 set_irq_chip(i, &ext_chip);
73 set_irq_handler(i, do_level_IRQ); 73 set_irq_handler(i, handle_level_irq);
74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 74 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
75 } 75 }
76} 76}
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 63304b3d0d7..00b37f32d72 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -121,7 +121,7 @@ void __init iop33x_init_irq(void)
121 121
122 for (i = 0; i < NR_IRQS; i++) { 122 for (i = 0; i < NR_IRQS; i++) {
123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); 123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
124 set_irq_handler(i, do_level_IRQ); 124 set_irq_handler(i, handle_level_irq);
125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
126 } 126 }
127} 127}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 22c98e9dad2..27b7480f4af 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -308,7 +308,7 @@ EXPORT_SYMBOL(gpio_line_config);
308/************************************************************************* 308/*************************************************************************
309 * IRQ handling IXP2000 309 * IRQ handling IXP2000
310 *************************************************************************/ 310 *************************************************************************/
311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc) 311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
312{ 312{
313 int i; 313 int i;
314 unsigned long status = *IXP2000_GPIO_INST; 314 unsigned long status = *IXP2000_GPIO_INST;
@@ -373,7 +373,7 @@ static void ixp2000_GPIO_irq_unmask(unsigned int irq)
373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
374} 374}
375 375
376static struct irqchip ixp2000_GPIO_irq_chip = { 376static struct irq_chip ixp2000_GPIO_irq_chip = {
377 .ack = ixp2000_GPIO_irq_mask_ack, 377 .ack = ixp2000_GPIO_irq_mask_ack,
378 .mask = ixp2000_GPIO_irq_mask, 378 .mask = ixp2000_GPIO_irq_mask,
379 .unmask = ixp2000_GPIO_irq_unmask, 379 .unmask = ixp2000_GPIO_irq_unmask,
@@ -401,7 +401,7 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
401/* 401/*
402 * Error interrupts. These are used extensively by the microengine drivers 402 * Error interrupts. These are used extensively by the microengine drivers
403 */ 403 */
404static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc) 404static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
405{ 405{
406 int i; 406 int i;
407 unsigned long status = *IXP2000_IRQ_ERR_STATUS; 407 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
@@ -426,13 +426,13 @@ static void ixp2000_err_irq_unmask(unsigned int irq)
426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); 426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
427} 427}
428 428
429static struct irqchip ixp2000_err_irq_chip = { 429static struct irq_chip ixp2000_err_irq_chip = {
430 .ack = ixp2000_err_irq_mask, 430 .ack = ixp2000_err_irq_mask,
431 .mask = ixp2000_err_irq_mask, 431 .mask = ixp2000_err_irq_mask,
432 .unmask = ixp2000_err_irq_unmask 432 .unmask = ixp2000_err_irq_unmask
433}; 433};
434 434
435static struct irqchip ixp2000_pci_irq_chip = { 435static struct irq_chip ixp2000_pci_irq_chip = {
436 .ack = ixp2000_pci_irq_mask, 436 .ack = ixp2000_pci_irq_mask,
437 .mask = ixp2000_pci_irq_mask, 437 .mask = ixp2000_pci_irq_mask,
438 .unmask = ixp2000_pci_irq_unmask 438 .unmask = ixp2000_pci_irq_unmask
@@ -448,7 +448,7 @@ static void ixp2000_irq_unmask(unsigned int irq)
448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq)); 448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
449} 449}
450 450
451static struct irqchip ixp2000_irq_chip = { 451static struct irq_chip ixp2000_irq_chip = {
452 .ack = ixp2000_irq_mask, 452 .ack = ixp2000_irq_mask,
453 .mask = ixp2000_irq_mask, 453 .mask = ixp2000_irq_mask,
454 .unmask = ixp2000_irq_unmask 454 .unmask = ixp2000_irq_unmask
@@ -484,7 +484,7 @@ void __init ixp2000_init_irq(void)
484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { 484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { 485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
486 set_irq_chip(irq, &ixp2000_irq_chip); 486 set_irq_chip(irq, &ixp2000_irq_chip);
487 set_irq_handler(irq, do_level_IRQ); 487 set_irq_handler(irq, handle_level_irq);
488 set_irq_flags(irq, IRQF_VALID); 488 set_irq_flags(irq, IRQF_VALID);
489 } else set_irq_flags(irq, 0); 489 } else set_irq_flags(irq, 0);
490 } 490 }
@@ -493,7 +493,7 @@ void __init ixp2000_init_irq(void)
493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & 493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
494 IXP2000_VALID_ERR_IRQ_MASK) { 494 IXP2000_VALID_ERR_IRQ_MASK) {
495 set_irq_chip(irq, &ixp2000_err_irq_chip); 495 set_irq_chip(irq, &ixp2000_err_irq_chip);
496 set_irq_handler(irq, do_level_IRQ); 496 set_irq_handler(irq, handle_level_irq);
497 set_irq_flags(irq, IRQF_VALID); 497 set_irq_flags(irq, IRQF_VALID);
498 } 498 }
499 else 499 else
@@ -503,7 +503,7 @@ void __init ixp2000_init_irq(void)
503 503
504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { 504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip); 505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
506 set_irq_handler(irq, do_level_IRQ); 506 set_irq_handler(irq, handle_level_irq);
507 set_irq_flags(irq, IRQF_VALID); 507 set_irq_flags(irq, IRQF_VALID);
508 } 508 }
509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); 509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
@@ -516,7 +516,7 @@ void __init ixp2000_init_irq(void)
516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); 516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { 517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
518 set_irq_chip(irq, &ixp2000_pci_irq_chip); 518 set_irq_chip(irq, &ixp2000_pci_irq_chip);
519 set_irq_handler(irq, do_level_IRQ); 519 set_irq_handler(irq, handle_level_irq);
520 set_irq_flags(irq, IRQF_VALID); 520 set_irq_flags(irq, IRQF_VALID);
521 } 521 }
522} 522}
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index aa2655092d2..52b368b3434 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -106,7 +106,7 @@ static void ixdp2x00_irq_unmask(unsigned int irq)
106 ixp2000_release_slowport(&old_cfg); 106 ixp2000_release_slowport(&old_cfg);
107} 107}
108 108
109static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc) 109static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
110{ 110{
111 volatile u32 ex_interrupt = 0; 111 volatile u32 ex_interrupt = 0;
112 static struct slowport_cfg old_cfg; 112 static struct slowport_cfg old_cfg;
@@ -129,7 +129,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
129 129
130 for(i = 0; i < board_irq_count; i++) { 130 for(i = 0; i < board_irq_count; i++) {
131 if(ex_interrupt & (1 << i)) { 131 if(ex_interrupt & (1 << i)) {
132 struct irqdesc *cpld_desc; 132 struct irq_desc *cpld_desc;
133 int cpld_irq = IXP2000_BOARD_IRQ(0) + i; 133 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
134 cpld_desc = irq_desc + cpld_irq; 134 cpld_desc = irq_desc + cpld_irq;
135 desc_handle_irq(cpld_irq, cpld_desc); 135 desc_handle_irq(cpld_irq, cpld_desc);
@@ -139,7 +139,7 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irqdesc *desc)
139 desc->chip->unmask(irq); 139 desc->chip->unmask(irq);
140} 140}
141 141
142static struct irqchip ixdp2x00_cpld_irq_chip = { 142static struct irq_chip ixdp2x00_cpld_irq_chip = {
143 .ack = ixdp2x00_irq_mask, 143 .ack = ixdp2x00_irq_mask,
144 .mask = ixdp2x00_irq_mask, 144 .mask = ixdp2x00_irq_mask,
145 .unmask = ixdp2x00_irq_unmask 145 .unmask = ixdp2x00_irq_unmask
@@ -162,7 +162,7 @@ void ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long
162 162
163 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { 163 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
164 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); 164 set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
165 set_irq_handler(irq, do_level_IRQ); 165 set_irq_handler(irq, handle_level_irq);
166 set_irq_flags(irq, IRQF_VALID); 166 set_irq_flags(irq, IRQF_VALID);
167 } 167 }
168 168
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 9ccae9e63f7..3084a5fa751 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -63,7 +63,7 @@ static void ixdp2x01_irq_unmask(unsigned int irq)
63 63
64static u32 valid_irq_mask; 64static u32 valid_irq_mask;
65 65
66static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc) 66static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
67{ 67{
68 u32 ex_interrupt; 68 u32 ex_interrupt;
69 int i; 69 int i;
@@ -79,7 +79,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
79 79
80 for (i = 0; i < IXP2000_BOARD_IRQS; i++) { 80 for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
81 if (ex_interrupt & (1 << i)) { 81 if (ex_interrupt & (1 << i)) {
82 struct irqdesc *cpld_desc; 82 struct irq_desc *cpld_desc;
83 int cpld_irq = IXP2000_BOARD_IRQ(0) + i; 83 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
84 cpld_desc = irq_desc + cpld_irq; 84 cpld_desc = irq_desc + cpld_irq;
85 desc_handle_irq(cpld_irq, cpld_desc); 85 desc_handle_irq(cpld_irq, cpld_desc);
@@ -89,7 +89,7 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc)
89 desc->chip->unmask(irq); 89 desc->chip->unmask(irq);
90} 90}
91 91
92static struct irqchip ixdp2x01_irq_chip = { 92static struct irq_chip ixdp2x01_irq_chip = {
93 .mask = ixdp2x01_irq_mask, 93 .mask = ixdp2x01_irq_mask,
94 .ack = ixdp2x01_irq_mask, 94 .ack = ixdp2x01_irq_mask,
95 .unmask = ixdp2x01_irq_unmask 95 .unmask = ixdp2x01_irq_unmask
@@ -119,7 +119,7 @@ void __init ixdp2x01_init_irq(void)
119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { 119 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
120 if (irq & valid_irq_mask) { 120 if (irq & valid_irq_mask) {
121 set_irq_chip(irq, &ixdp2x01_irq_chip); 121 set_irq_chip(irq, &ixdp2x01_irq_chip);
122 set_irq_handler(irq, do_level_IRQ); 122 set_irq_handler(irq, handle_level_irq);
123 set_irq_flags(irq, IRQF_VALID); 123 set_irq_flags(irq, IRQF_VALID);
124 } else { 124 } else {
125 set_irq_flags(irq, 0); 125 set_irq_flags(irq, 0);
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index a704a182004..ce6ad635a00 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -224,14 +224,14 @@ static void ixp23xx_irq_edge_unmask(unsigned int irq)
224 *intr_reg |= (1 << (irq % 32)); 224 *intr_reg |= (1 << (irq % 32));
225} 225}
226 226
227static struct irqchip ixp23xx_irq_level_chip = { 227static struct irq_chip ixp23xx_irq_level_chip = {
228 .ack = ixp23xx_irq_mask, 228 .ack = ixp23xx_irq_mask,
229 .mask = ixp23xx_irq_mask, 229 .mask = ixp23xx_irq_mask,
230 .unmask = ixp23xx_irq_level_unmask, 230 .unmask = ixp23xx_irq_level_unmask,
231 .set_type = ixp23xx_irq_set_type 231 .set_type = ixp23xx_irq_set_type
232}; 232};
233 233
234static struct irqchip ixp23xx_irq_edge_chip = { 234static struct irq_chip ixp23xx_irq_edge_chip = {
235 .ack = ixp23xx_irq_ack, 235 .ack = ixp23xx_irq_ack,
236 .mask = ixp23xx_irq_mask, 236 .mask = ixp23xx_irq_mask,
237 .unmask = ixp23xx_irq_edge_unmask, 237 .unmask = ixp23xx_irq_edge_unmask,
@@ -251,11 +251,11 @@ static void ixp23xx_pci_irq_unmask(unsigned int irq)
251/* 251/*
252 * TODO: Should this just be done at ASM level? 252 * TODO: Should this just be done at ASM level?
253 */ 253 */
254static void pci_handler(unsigned int irq, struct irqdesc *desc) 254static void pci_handler(unsigned int irq, struct irq_desc *desc)
255{ 255{
256 u32 pci_interrupt; 256 u32 pci_interrupt;
257 unsigned int irqno; 257 unsigned int irqno;
258 struct irqdesc *int_desc; 258 struct irq_desc *int_desc;
259 259
260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS; 260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
261 261
@@ -276,7 +276,7 @@ static void pci_handler(unsigned int irq, struct irqdesc *desc)
276 desc->chip->unmask(irq); 276 desc->chip->unmask(irq);
277} 277}
278 278
279static struct irqchip ixp23xx_pci_irq_chip = { 279static struct irq_chip ixp23xx_pci_irq_chip = {
280 .ack = ixp23xx_pci_irq_mask, 280 .ack = ixp23xx_pci_irq_mask,
281 .mask = ixp23xx_pci_irq_mask, 281 .mask = ixp23xx_pci_irq_mask,
282 .unmask = ixp23xx_pci_irq_unmask 282 .unmask = ixp23xx_pci_irq_unmask
@@ -287,11 +287,11 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
287 switch (type) { 287 switch (type) {
288 case IXP23XX_IRQ_LEVEL: 288 case IXP23XX_IRQ_LEVEL:
289 set_irq_chip(irq, &ixp23xx_irq_level_chip); 289 set_irq_chip(irq, &ixp23xx_irq_level_chip);
290 set_irq_handler(irq, do_level_IRQ); 290 set_irq_handler(irq, handle_level_irq);
291 break; 291 break;
292 case IXP23XX_IRQ_EDGE: 292 case IXP23XX_IRQ_EDGE:
293 set_irq_chip(irq, &ixp23xx_irq_edge_chip); 293 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
294 set_irq_handler(irq, do_edge_IRQ); 294 set_irq_handler(irq, handle_edge_irq);
295 break; 295 break;
296 } 296 }
297 set_irq_flags(irq, IRQF_VALID); 297 set_irq_flags(irq, IRQF_VALID);
@@ -322,7 +322,7 @@ void __init ixp23xx_init_irq(void)
322 322
323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { 323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
324 set_irq_chip(irq, &ixp23xx_pci_irq_chip); 324 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
325 set_irq_handler(irq, do_level_IRQ); 325 set_irq_handler(irq, handle_level_irq);
326 set_irq_flags(irq, IRQF_VALID); 326 set_irq_flags(irq, IRQF_VALID);
327 } 327 }
328 328
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index b6ab0e8bb5e..7a86a2516ea 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -60,7 +60,7 @@ static void ixdp2351_inta_unmask(unsigned int irq)
60 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq); 60 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
61} 61}
62 62
63static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc) 63static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
64{ 64{
65 u16 ex_interrupt = 65 u16 ex_interrupt =
66 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID; 66 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
@@ -70,7 +70,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
70 70
71 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) { 71 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
72 if (ex_interrupt & (1 << i)) { 72 if (ex_interrupt & (1 << i)) {
73 struct irqdesc *cpld_desc; 73 struct irq_desc *cpld_desc;
74 int cpld_irq = 74 int cpld_irq =
75 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i); 75 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
76 cpld_desc = irq_desc + cpld_irq; 76 cpld_desc = irq_desc + cpld_irq;
@@ -81,7 +81,7 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc)
81 desc->chip->unmask(irq); 81 desc->chip->unmask(irq);
82} 82}
83 83
84static struct irqchip ixdp2351_inta_chip = { 84static struct irq_chip ixdp2351_inta_chip = {
85 .ack = ixdp2351_inta_mask, 85 .ack = ixdp2351_inta_mask,
86 .mask = ixdp2351_inta_mask, 86 .mask = ixdp2351_inta_mask,
87 .unmask = ixdp2351_inta_unmask 87 .unmask = ixdp2351_inta_unmask
@@ -97,7 +97,7 @@ static void ixdp2351_intb_unmask(unsigned int irq)
97 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq); 97 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
98} 98}
99 99
100static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc) 100static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
101{ 101{
102 u16 ex_interrupt = 102 u16 ex_interrupt =
103 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID; 103 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
@@ -107,7 +107,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
107 107
108 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) { 108 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
109 if (ex_interrupt & (1 << i)) { 109 if (ex_interrupt & (1 << i)) {
110 struct irqdesc *cpld_desc; 110 struct irq_desc *cpld_desc;
111 int cpld_irq = 111 int cpld_irq =
112 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i); 112 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
113 cpld_desc = irq_desc + cpld_irq; 113 cpld_desc = irq_desc + cpld_irq;
@@ -118,7 +118,7 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc)
118 desc->chip->unmask(irq); 118 desc->chip->unmask(irq);
119} 119}
120 120
121static struct irqchip ixdp2351_intb_chip = { 121static struct irq_chip ixdp2351_intb_chip = {
122 .ack = ixdp2351_intb_mask, 122 .ack = ixdp2351_intb_mask,
123 .mask = ixdp2351_intb_mask, 123 .mask = ixdp2351_intb_mask,
124 .unmask = ixdp2351_intb_unmask 124 .unmask = ixdp2351_intb_unmask
@@ -142,7 +142,7 @@ void ixdp2351_init_irq(void)
142 irq++) { 142 irq++) {
143 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { 143 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
144 set_irq_flags(irq, IRQF_VALID); 144 set_irq_flags(irq, IRQF_VALID);
145 set_irq_handler(irq, do_level_IRQ); 145 set_irq_handler(irq, handle_level_irq);
146 set_irq_chip(irq, &ixdp2351_inta_chip); 146 set_irq_chip(irq, &ixdp2351_inta_chip);
147 } 147 }
148 } 148 }
@@ -153,7 +153,7 @@ void ixdp2351_init_irq(void)
153 irq++) { 153 irq++) {
154 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { 154 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
155 set_irq_flags(irq, IRQF_VALID); 155 set_irq_flags(irq, IRQF_VALID);
156 set_irq_handler(irq, do_level_IRQ); 156 set_irq_handler(irq, handle_level_irq);
157 set_irq_chip(irq, &ixdp2351_intb_chip); 157 set_irq_chip(irq, &ixdp2351_intb_chip);
158 } 158 }
159 } 159 }
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index fbe288a8da6..074c9652024 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -195,7 +195,7 @@ static void ixp4xx_irq_unmask(unsigned int irq)
195 *IXP4XX_ICMR |= (1 << irq); 195 *IXP4XX_ICMR |= (1 << irq);
196} 196}
197 197
198static struct irqchip ixp4xx_irq_chip = { 198static struct irq_chip ixp4xx_irq_chip = {
199 .name = "IXP4xx", 199 .name = "IXP4xx",
200 .ack = ixp4xx_irq_ack, 200 .ack = ixp4xx_irq_ack,
201 .mask = ixp4xx_irq_mask, 201 .mask = ixp4xx_irq_mask,
@@ -224,7 +224,7 @@ void __init ixp4xx_init_irq(void)
224 /* Default to all level triggered */ 224 /* Default to all level triggered */
225 for(i = 0; i < NR_IRQS; i++) { 225 for(i = 0; i < NR_IRQS; i++) {
226 set_irq_chip(i, &ixp4xx_irq_chip); 226 set_irq_chip(i, &ixp4xx_irq_chip);
227 set_irq_handler(i, do_level_IRQ); 227 set_irq_handler(i, handle_level_irq);
228 set_irq_flags(i, IRQF_VALID); 228 set_irq_flags(i, IRQF_VALID);
229 } 229 }
230} 230}
diff --git a/arch/arm/mach-l7200/core.c b/arch/arm/mach-l7200/core.c
index b7af5640ea7..561a0fe7095 100644
--- a/arch/arm/mach-l7200/core.c
+++ b/arch/arm/mach-l7200/core.c
@@ -55,7 +55,7 @@ static void l7200_unmask_irq(unsigned int irq)
55 IRQ_ENABLE = 1 << irq; 55 IRQ_ENABLE = 1 << irq;
56} 56}
57 57
58static struct irqchip l7200_irq_chip = { 58static struct irq_chip l7200_irq_chip = {
59 .ack = l7200_mask_irq, 59 .ack = l7200_mask_irq,
60 .mask = l7200_mask_irq, 60 .mask = l7200_mask_irq,
61 .unmask = l7200_unmask_irq 61 .unmask = l7200_unmask_irq
@@ -71,7 +71,7 @@ static void __init l7200_init_irq(void)
71 for (irq = 0; irq < NR_IRQS; irq++) { 71 for (irq = 0; irq < NR_IRQS; irq++) {
72 set_irq_chip(irq, &l7200_irq_chip); 72 set_irq_chip(irq, &l7200_irq_chip);
73 set_irq_flags(irq, IRQF_VALID); 73 set_irq_flags(irq, IRQF_VALID);
74 set_irq_handler(irq, do_level_IRQ); 74 set_irq_handler(irq, handle_level_irq);
75 } 75 }
76 76
77 init_FIQ(); 77 init_FIQ();
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 15fbcc911fe..6d26661d99f 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -71,7 +71,7 @@ static struct irq_chip kev7a400_cpld_chip = {
71}; 71};
72 72
73 73
74static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc) 74static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
75{ 75{
76 u32 mask = CPLD_LATCHED_INTS; 76 u32 mask = CPLD_LATCHED_INTS;
77 irq = IRQ_KEV7A400_CPLD; 77 irq = IRQ_KEV7A400_CPLD;
@@ -88,7 +88,7 @@ void __init lh7a40x_init_board_irq (void)
88 for (irq = IRQ_KEV7A400_CPLD; 88 for (irq = IRQ_KEV7A400_CPLD;
89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) { 89 irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) {
90 set_irq_chip (irq, &kev7a400_cpld_chip); 90 set_irq_chip (irq, &kev7a400_cpld_chip);
91 set_irq_handler (irq, do_edge_IRQ); 91 set_irq_handler (irq, handle_edge_irq);
92 set_irq_flags (irq, IRQF_VALID); 92 set_irq_flags (irq, IRQF_VALID);
93 } 93 }
94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); 94 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index 8441e0a156c..fe64946f9e1 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -207,7 +207,7 @@ static struct irq_chip lpd7a40x_cpld_chip = {
207 .unmask = lh7a40x_unmask_cpld_irq, 207 .unmask = lh7a40x_unmask_cpld_irq,
208}; 208};
209 209
210static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc) 210static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
211{ 211{
212 unsigned int mask = CPLD_INTERRUPTS; 212 unsigned int mask = CPLD_INTERRUPTS;
213 213
@@ -279,7 +279,7 @@ void __init lh7a40x_init_board_irq (void)
279 for (irq = IRQ_BOARD_START; 279 for (irq = IRQ_BOARD_START;
280 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 280 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
281 set_irq_chip (irq, &lpd7a40x_cpld_chip); 281 set_irq_chip (irq, &lpd7a40x_cpld_chip);
282 set_irq_handler (irq, do_level_IRQ); 282 set_irq_handler (irq, handle_level_irq);
283 set_irq_flags (irq, IRQF_VALID); 283 set_irq_flags (irq, IRQF_VALID);
284 } 284 }
285 285
diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c
index 646071334b8..c7433b3c581 100644
--- a/arch/arm/mach-lh7a40x/irq-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c
@@ -51,7 +51,7 @@ irq_chip lh7a400_cpld_chip = {
51}; 51};
52 52
53static void 53static void
54lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc) 54lh7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
55{ 55{
56 u32 mask = CPLD_LATCHED_INTS; 56 u32 mask = CPLD_LATCHED_INTS;
57 irq = IRQ_KEV_7A400_CPLD; 57 irq = IRQ_KEV_7A400_CPLD;
@@ -71,7 +71,7 @@ lh7a400_init_board_irq (void)
71 for (irq = IRQ_KEV7A400_CPLD; 71 for (irq = IRQ_KEV7A400_CPLD;
72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) { 72 irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) {
73 set_irq_chip (irq, &lh7a400_cpld_chip); 73 set_irq_chip (irq, &lh7a400_cpld_chip);
74 set_irq_handler (irq, do_edge_IRQ); 74 set_irq_handler (irq, handle_edge_irq);
75 set_irq_flags (irq, IRQF_VALID); 75 set_irq_flags (irq, IRQF_VALID);
76 } 76 }
77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); 77 set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler);
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 091b2dc58d2..0b938e8b4d9 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -74,11 +74,11 @@ void __init lh7a400_init_irq (void)
74 case IRQ_GPIO6INTR: 74 case IRQ_GPIO6INTR:
75 case IRQ_GPIO7INTR: 75 case IRQ_GPIO7INTR:
76 set_irq_chip (irq, &lh7a400_gpio_chip); 76 set_irq_chip (irq, &lh7a400_gpio_chip);
77 set_irq_handler (irq, do_level_IRQ); /* OK default */ 77 set_irq_handler (irq, handle_level_irq); /* OK default */
78 break; 78 break;
79 default: 79 default:
80 set_irq_chip (irq, &lh7a400_internal_chip); 80 set_irq_chip (irq, &lh7a400_internal_chip);
81 set_irq_handler (irq, do_level_IRQ); 81 set_irq_handler (irq, handle_level_irq);
82 } 82 }
83 set_irq_flags (irq, IRQF_VALID); 83 set_irq_flags (irq, IRQF_VALID);
84 } 84 }
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index 7059b983724..5760f8c53e8 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -161,13 +161,13 @@ void __init lh7a404_init_irq (void)
161 set_irq_chip (irq, irq < 32 161 set_irq_chip (irq, irq < 32
162 ? &lh7a404_gpio_vic1_chip 162 ? &lh7a404_gpio_vic1_chip
163 : &lh7a404_gpio_vic2_chip); 163 : &lh7a404_gpio_vic2_chip);
164 set_irq_handler (irq, do_level_IRQ); /* OK default */ 164 set_irq_handler (irq, handle_level_irq); /* OK default */
165 break; 165 break;
166 default: 166 default:
167 set_irq_chip (irq, irq < 32 167 set_irq_chip (irq, irq < 32
168 ? &lh7a404_vic1_chip 168 ? &lh7a404_vic1_chip
169 : &lh7a404_vic2_chip); 169 : &lh7a404_vic2_chip);
170 set_irq_handler (irq, do_level_IRQ); 170 set_irq_handler (irq, handle_level_irq);
171 } 171 }
172 set_irq_flags (irq, IRQF_VALID); 172 set_irq_flags (irq, IRQF_VALID);
173 } 173 }
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index b20376804bb..15b9577023c 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -57,7 +57,7 @@ static struct irq_chip lh7a40x_cpld_chip = {
57 .unmask = lh7a40x_unmask_cpld_irq, 57 .unmask = lh7a40x_unmask_cpld_irq,
58}; 58};
59 59
60static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc) 60static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
61{ 61{
62 unsigned int mask = CPLD_INTERRUPTS; 62 unsigned int mask = CPLD_INTERRUPTS;
63 63
@@ -118,7 +118,7 @@ void __init lh7a40x_init_board_irq (void)
118 for (irq = IRQ_BOARD_START; 118 for (irq = IRQ_BOARD_START;
119 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 119 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
120 set_irq_chip (irq, &lh7a40x_cpld_chip); 120 set_irq_chip (irq, &lh7a40x_cpld_chip);
121 set_irq_handler (irq, do_edge_IRQ); 121 set_irq_handler (irq, handle_edge_irq);
122 set_irq_flags (irq, IRQF_VALID); 122 set_irq_flags (irq, IRQF_VALID);
123 } 123 }
124 124
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index edbbbdc3b06..b9ca8f98265 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -69,7 +69,7 @@ static struct platform_device *devices[] __initdata = {
69#endif 69#endif
70 70
71static void 71static void
72netx_hif_demux_handler(unsigned int irq_unused, struct irqdesc *desc) 72netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
73{ 73{
74 unsigned int irq = NETX_IRQ_HIF_CHAINED(0); 74 unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
75 unsigned int stat; 75 unsigned int stat;
@@ -160,7 +160,7 @@ netx_hif_unmask_irq(unsigned int _irq)
160 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq); 160 DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, _irq);
161} 161}
162 162
163static struct irqchip netx_hif_chip = { 163static struct irq_chip netx_hif_chip = {
164 .ack = netx_hif_ack_irq, 164 .ack = netx_hif_ack_irq,
165 .mask = netx_hif_mask_irq, 165 .mask = netx_hif_mask_irq,
166 .unmask = netx_hif_unmask_irq, 166 .unmask = netx_hif_unmask_irq,
@@ -175,7 +175,7 @@ void __init netx_init_irq(void)
175 175
176 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 176 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
177 set_irq_chip(irq, &netx_hif_chip); 177 set_irq_chip(irq, &netx_hif_chip);
178 set_irq_handler(irq, do_level_IRQ); 178 set_irq_handler(irq, handle_level_irq);
179 set_irq_flags(irq, IRQF_VALID); 179 set_irq_flags(irq, IRQF_VALID);
180 } 180 }
181 181
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 8e40208b10b..30e18810904 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -84,9 +84,9 @@ static void fpga_mask_ack_irq(unsigned int irq)
84 fpga_ack_irq(irq); 84 fpga_ack_irq(irq);
85} 85}
86 86
87void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc) 87void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
88{ 88{
89 struct irqdesc *d; 89 struct irq_desc *d;
90 u32 stat; 90 u32 stat;
91 int fpga_irq; 91 int fpga_irq;
92 92
@@ -168,7 +168,7 @@ void omap1510_fpga_init_irq(void)
168 set_irq_chip(i, &omap_fpga_irq); 168 set_irq_chip(i, &omap_fpga_irq);
169 } 169 }
170 170
171 set_irq_handler(i, do_edge_IRQ); 171 set_irq_handler(i, handle_edge_irq);
172 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
173 } 173 }
174 174
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 3ea140bb9eb..6383a12ad97 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -229,7 +229,7 @@ void __init omap_init_irq(void)
229 omap_irq_set_cfg(j, 0, 0, irq_trigger); 229 omap_irq_set_cfg(j, 0, 0, irq_trigger);
230 230
231 set_irq_chip(j, &omap_irq_chip); 231 set_irq_chip(j, &omap_irq_chip);
232 set_irq_handler(j, do_level_IRQ); 232 set_irq_handler(j, handle_level_irq);
233 set_irq_flags(j, IRQF_VALID); 233 set_irq_flags(j, IRQF_VALID);
234 } 234 }
235 } 235 }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 11870093d7a..a39d3068030 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -130,7 +130,7 @@ void __init omap_init_irq(void)
130 130
131 for (i = 0; i < nr_irqs; i++) { 131 for (i = 0; i < nr_irqs; i++) {
132 set_irq_chip(i, &omap_irq_chip); 132 set_irq_chip(i, &omap_irq_chip);
133 set_irq_handler(i, do_level_IRQ); 133 set_irq_handler(i, handle_level_irq);
134 set_irq_flags(i, IRQF_VALID); 134 set_irq_flags(i, IRQF_VALID);
135 } 135 }
136} 136}
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 3a4bcf3d91f..968d0b02759 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
59 case IRQT_RISING: 59 case IRQT_RISING:
60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ 61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
62 set_irq_handler(irq, do_edge_IRQ); 62 set_irq_handler(irq, handle_edge_irq);
63 break; 63 break;
64 case IRQT_FALLING: 64 case IRQT_FALLING:
65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ 66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
67 set_irq_handler(irq, do_edge_IRQ); 67 set_irq_handler(irq, handle_edge_irq);
68 break; 68 break;
69 case IRQT_LOW: 69 case IRQT_LOW:
70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ 71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
72 set_irq_handler(irq, do_level_IRQ); 72 set_irq_handler(irq, handle_level_irq);
73 break; 73 break;
74 case IRQT_HIGH: 74 case IRQT_HIGH:
75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ 76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
77 set_irq_handler(irq, do_level_IRQ); 77 set_irq_handler(irq, handle_level_irq);
78 break; 78 break;
79 79
80 /* IRQT_BOTHEDGE is not supported */ 80 /* IRQT_BOTHEDGE is not supported */
@@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
85 return 0; 85 return 0;
86} 86}
87 87
88static struct irqchip pnx4008_irq_chip = { 88static struct irq_chip pnx4008_irq_chip = {
89 .ack = pnx4008_mask_ack_irq, 89 .ack = pnx4008_mask_ack_irq,
90 .mask = pnx4008_mask_irq, 90 .mask = pnx4008_mask_irq,
91 .unmask = pnx4008_unmask_irq, 91 .unmask = pnx4008_unmask_irq,
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index ab1a16025d5..f815678a9d6 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -143,7 +143,7 @@ static struct irq_chip pxa_low_gpio_chip = {
143 * Demux handler for GPIO>=2 edge detect interrupts 143 * Demux handler for GPIO>=2 edge detect interrupts
144 */ 144 */
145 145
146static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc) 146static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
147{ 147{
148 unsigned int mask; 148 unsigned int mask;
149 int loop; 149 int loop;
@@ -286,27 +286,27 @@ void __init pxa_init_irq(void)
286 286
287 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) { 287 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
288 set_irq_chip(irq, &pxa_internal_chip_low); 288 set_irq_chip(irq, &pxa_internal_chip_low);
289 set_irq_handler(irq, do_level_IRQ); 289 set_irq_handler(irq, handle_level_irq);
290 set_irq_flags(irq, IRQF_VALID); 290 set_irq_flags(irq, IRQF_VALID);
291 } 291 }
292 292
293#if PXA_INTERNAL_IRQS > 32 293#if PXA_INTERNAL_IRQS > 32
294 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) { 294 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
295 set_irq_chip(irq, &pxa_internal_chip_high); 295 set_irq_chip(irq, &pxa_internal_chip_high);
296 set_irq_handler(irq, do_level_IRQ); 296 set_irq_handler(irq, handle_level_irq);
297 set_irq_flags(irq, IRQF_VALID); 297 set_irq_flags(irq, IRQF_VALID);
298 } 298 }
299#endif 299#endif
300 300
301 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { 301 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
302 set_irq_chip(irq, &pxa_low_gpio_chip); 302 set_irq_chip(irq, &pxa_low_gpio_chip);
303 set_irq_handler(irq, do_edge_IRQ); 303 set_irq_handler(irq, handle_edge_irq);
304 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 304 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
305 } 305 }
306 306
307 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { 307 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
308 set_irq_chip(irq, &pxa_muxed_gpio_chip); 308 set_irq_chip(irq, &pxa_muxed_gpio_chip);
309 set_irq_handler(irq, do_edge_IRQ); 309 set_irq_handler(irq, handle_edge_irq);
310 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 310 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
311 } 311 }
312 312
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 5749f6b72e1..8e27a64fa9f 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -75,7 +75,7 @@ static struct irq_chip lpd270_irq_chip = {
75 .unmask = lpd270_unmask_irq, 75 .unmask = lpd270_unmask_irq,
76}; 76};
77 77
78static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc) 78static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
79{ 79{
80 unsigned long pending; 80 unsigned long pending;
81 81
@@ -105,7 +105,7 @@ static void __init lpd270_init_irq(void)
105 /* setup extra LogicPD PXA270 irqs */ 105 /* setup extra LogicPD PXA270 irqs */
106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { 106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
107 set_irq_chip(irq, &lpd270_irq_chip); 107 set_irq_chip(irq, &lpd270_irq_chip);
108 set_irq_handler(irq, do_level_IRQ); 108 set_irq_handler(irq, handle_level_irq);
109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
110 } 110 }
111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); 111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 142c33c3dff..055de7f4f00 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -85,7 +85,7 @@ static struct irq_chip lubbock_irq_chip = {
85 .unmask = lubbock_unmask_irq, 85 .unmask = lubbock_unmask_irq,
86}; 86};
87 87
88static void lubbock_irq_handler(unsigned int irq, struct irqdesc *desc) 88static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
89{ 89{
90 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; 90 unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
91 do { 91 do {
@@ -108,7 +108,7 @@ static void __init lubbock_init_irq(void)
108 /* setup extra lubbock irqs */ 108 /* setup extra lubbock irqs */
109 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { 109 for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
110 set_irq_chip(irq, &lubbock_irq_chip); 110 set_irq_chip(irq, &lubbock_irq_chip);
111 set_irq_handler(irq, do_level_IRQ); 111 set_irq_handler(irq, handle_level_irq);
112 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 112 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
113 } 113 }
114 114
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 49c34d94a9f..56d94d88d5c 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -71,7 +71,7 @@ static struct irq_chip mainstone_irq_chip = {
71 .unmask = mainstone_unmask_irq, 71 .unmask = mainstone_unmask_irq,
72}; 72};
73 73
74static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc) 74static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
75{ 75{
76 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; 76 unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
77 do { 77 do {
@@ -94,7 +94,7 @@ static void __init mainstone_init_irq(void)
94 /* setup extra Mainstone irqs */ 94 /* setup extra Mainstone irqs */
95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
96 set_irq_chip(irq, &mainstone_irq_chip); 96 set_irq_chip(irq, &mainstone_irq_chip);
97 set_irq_handler(irq, do_level_IRQ); 97 set_irq_handler(irq, handle_level_irq);
98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) 98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); 99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
100 else 100 else
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 56b2716f8cf..7a029621db4 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -34,7 +34,7 @@ static void iomd_unmask_irq_a(unsigned int irq)
34 iomd_writeb(val | mask, IOMD_IRQMASKA); 34 iomd_writeb(val | mask, IOMD_IRQMASKA);
35} 35}
36 36
37static struct irqchip iomd_a_chip = { 37static struct irq_chip iomd_a_chip = {
38 .ack = iomd_ack_irq_a, 38 .ack = iomd_ack_irq_a,
39 .mask = iomd_mask_irq_a, 39 .mask = iomd_mask_irq_a,
40 .unmask = iomd_unmask_irq_a, 40 .unmask = iomd_unmask_irq_a,
@@ -58,7 +58,7 @@ static void iomd_unmask_irq_b(unsigned int irq)
58 iomd_writeb(val | mask, IOMD_IRQMASKB); 58 iomd_writeb(val | mask, IOMD_IRQMASKB);
59} 59}
60 60
61static struct irqchip iomd_b_chip = { 61static struct irq_chip iomd_b_chip = {
62 .ack = iomd_mask_irq_b, 62 .ack = iomd_mask_irq_b,
63 .mask = iomd_mask_irq_b, 63 .mask = iomd_mask_irq_b,
64 .unmask = iomd_unmask_irq_b, 64 .unmask = iomd_unmask_irq_b,
@@ -82,7 +82,7 @@ static void iomd_unmask_irq_dma(unsigned int irq)
82 iomd_writeb(val | mask, IOMD_DMAMASK); 82 iomd_writeb(val | mask, IOMD_DMAMASK);
83} 83}
84 84
85static struct irqchip iomd_dma_chip = { 85static struct irq_chip iomd_dma_chip = {
86 .ack = iomd_mask_irq_dma, 86 .ack = iomd_mask_irq_dma,
87 .mask = iomd_mask_irq_dma, 87 .mask = iomd_mask_irq_dma,
88 .unmask = iomd_unmask_irq_dma, 88 .unmask = iomd_unmask_irq_dma,
@@ -106,7 +106,7 @@ static void iomd_unmask_irq_fiq(unsigned int irq)
106 iomd_writeb(val | mask, IOMD_FIQMASK); 106 iomd_writeb(val | mask, IOMD_FIQMASK);
107} 107}
108 108
109static struct irqchip iomd_fiq_chip = { 109static struct irq_chip iomd_fiq_chip = {
110 .ack = iomd_mask_irq_fiq, 110 .ack = iomd_mask_irq_fiq,
111 .mask = iomd_mask_irq_fiq, 111 .mask = iomd_mask_irq_fiq,
112 .unmask = iomd_unmask_irq_fiq, 112 .unmask = iomd_unmask_irq_fiq,
@@ -134,19 +134,19 @@ void __init rpc_init_irq(void)
134 switch (irq) { 134 switch (irq) {
135 case 0 ... 7: 135 case 0 ... 7:
136 set_irq_chip(irq, &iomd_a_chip); 136 set_irq_chip(irq, &iomd_a_chip);
137 set_irq_handler(irq, do_level_IRQ); 137 set_irq_handler(irq, handle_level_irq);
138 set_irq_flags(irq, flags); 138 set_irq_flags(irq, flags);
139 break; 139 break;
140 140
141 case 8 ... 15: 141 case 8 ... 15:
142 set_irq_chip(irq, &iomd_b_chip); 142 set_irq_chip(irq, &iomd_b_chip);
143 set_irq_handler(irq, do_level_IRQ); 143 set_irq_handler(irq, handle_level_irq);
144 set_irq_flags(irq, flags); 144 set_irq_flags(irq, flags);
145 break; 145 break;
146 146
147 case 16 ... 21: 147 case 16 ... 21:
148 set_irq_chip(irq, &iomd_dma_chip); 148 set_irq_chip(irq, &iomd_dma_chip);
149 set_irq_handler(irq, do_level_IRQ); 149 set_irq_handler(irq, handle_level_irq);
150 set_irq_flags(irq, flags); 150 set_irq_flags(irq, flags);
151 break; 151 break;
152 152
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 23d5beea556..379efe70778 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -88,7 +88,7 @@ bast_pc104_mask(unsigned int irqno)
88static void 88static void
89bast_pc104_maskack(unsigned int irqno) 89bast_pc104_maskack(unsigned int irqno)
90{ 90{
91 struct irqdesc *desc = irq_desc + IRQ_ISA; 91 struct irq_desc *desc = irq_desc + IRQ_ISA;
92 92
93 bast_pc104_mask(irqno); 93 bast_pc104_mask(irqno);
94 desc->chip->ack(IRQ_ISA); 94 desc->chip->ack(IRQ_ISA);
@@ -104,7 +104,7 @@ bast_pc104_unmask(unsigned int irqno)
104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK); 104 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
105} 105}
106 106
107static struct irqchip bast_pc104_chip = { 107static struct irq_chip bast_pc104_chip = {
108 .mask = bast_pc104_mask, 108 .mask = bast_pc104_mask,
109 .unmask = bast_pc104_unmask, 109 .unmask = bast_pc104_unmask,
110 .ack = bast_pc104_maskack 110 .ack = bast_pc104_maskack
@@ -112,7 +112,7 @@ static struct irqchip bast_pc104_chip = {
112 112
113static void 113static void
114bast_irq_pc104_demux(unsigned int irq, 114bast_irq_pc104_demux(unsigned int irq,
115 struct irqdesc *desc) 115 struct irq_desc *desc)
116{ 116{
117 unsigned int stat; 117 unsigned int stat;
118 unsigned int irqno; 118 unsigned int irqno;
@@ -157,7 +157,7 @@ static __init int bast_irq_init(void)
157 unsigned int irqno = bast_pc104_irqs[i]; 157 unsigned int irqno = bast_pc104_irqs[i];
158 158
159 set_irq_chip(irqno, &bast_pc104_chip); 159 set_irq_chip(irqno, &bast_pc104_chip);
160 set_irq_handler(irqno, do_level_IRQ); 160 set_irq_handler(irqno, handle_level_irq);
161 set_irq_flags(irqno, IRQF_VALID); 161 set_irq_flags(irqno, IRQF_VALID);
162 } 162 }
163 } 163 }
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b3491ba3..e7d2ad96ae6 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@ s3c_irq_unmask(unsigned int irqno)
180 __raw_writel(mask, S3C2410_INTMSK); 180 __raw_writel(mask, S3C2410_INTMSK);
181} 181}
182 182
183struct irqchip s3c_irq_level_chip = { 183struct irq_chip s3c_irq_level_chip = {
184 .name = "s3c-level", 184 .name = "s3c-level",
185 .ack = s3c_irq_maskack, 185 .ack = s3c_irq_maskack,
186 .mask = s3c_irq_mask, 186 .mask = s3c_irq_mask,
@@ -188,7 +188,7 @@ struct irqchip s3c_irq_level_chip = {
188 .set_wake = s3c_irq_wake 188 .set_wake = s3c_irq_wake
189}; 189};
190 190
191static struct irqchip s3c_irq_chip = { 191static struct irq_chip s3c_irq_chip = {
192 .name = "s3c", 192 .name = "s3c",
193 .ack = s3c_irq_ack, 193 .ack = s3c_irq_ack,
194 .mask = s3c_irq_mask, 194 .mask = s3c_irq_mask,
@@ -344,7 +344,7 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
344 return 0; 344 return 0;
345} 345}
346 346
347static struct irqchip s3c_irqext_chip = { 347static struct irq_chip s3c_irqext_chip = {
348 .name = "s3c-ext", 348 .name = "s3c-ext",
349 .mask = s3c_irqext_mask, 349 .mask = s3c_irqext_mask,
350 .unmask = s3c_irqext_unmask, 350 .unmask = s3c_irqext_unmask,
@@ -353,7 +353,7 @@ static struct irqchip s3c_irqext_chip = {
353 .set_wake = s3c_irqext_wake 353 .set_wake = s3c_irqext_wake
354}; 354};
355 355
356static struct irqchip s3c_irq_eint0t4 = { 356static struct irq_chip s3c_irq_eint0t4 = {
357 .name = "s3c-ext0", 357 .name = "s3c-ext0",
358 .ack = s3c_irq_ack, 358 .ack = s3c_irq_ack,
359 .mask = s3c_irq_mask, 359 .mask = s3c_irq_mask,
@@ -390,7 +390,7 @@ s3c_irq_uart0_ack(unsigned int irqno)
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); 390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
391} 391}
392 392
393static struct irqchip s3c_irq_uart0 = { 393static struct irq_chip s3c_irq_uart0 = {
394 .name = "s3c-uart0", 394 .name = "s3c-uart0",
395 .mask = s3c_irq_uart0_mask, 395 .mask = s3c_irq_uart0_mask,
396 .unmask = s3c_irq_uart0_unmask, 396 .unmask = s3c_irq_uart0_unmask,
@@ -417,7 +417,7 @@ s3c_irq_uart1_ack(unsigned int irqno)
417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); 417 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
418} 418}
419 419
420static struct irqchip s3c_irq_uart1 = { 420static struct irq_chip s3c_irq_uart1 = {
421 .name = "s3c-uart1", 421 .name = "s3c-uart1",
422 .mask = s3c_irq_uart1_mask, 422 .mask = s3c_irq_uart1_mask,
423 .unmask = s3c_irq_uart1_unmask, 423 .unmask = s3c_irq_uart1_unmask,
@@ -444,7 +444,7 @@ s3c_irq_uart2_ack(unsigned int irqno)
444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); 444 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
445} 445}
446 446
447static struct irqchip s3c_irq_uart2 = { 447static struct irq_chip s3c_irq_uart2 = {
448 .name = "s3c-uart2", 448 .name = "s3c-uart2",
449 .mask = s3c_irq_uart2_mask, 449 .mask = s3c_irq_uart2_mask,
450 .unmask = s3c_irq_uart2_unmask, 450 .unmask = s3c_irq_uart2_unmask,
@@ -471,7 +471,7 @@ s3c_irq_adc_ack(unsigned int irqno)
471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); 471 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
472} 472}
473 473
474static struct irqchip s3c_irq_adc = { 474static struct irq_chip s3c_irq_adc = {
475 .name = "s3c-adc", 475 .name = "s3c-adc",
476 .mask = s3c_irq_adc_mask, 476 .mask = s3c_irq_adc_mask,
477 .unmask = s3c_irq_adc_unmask, 477 .unmask = s3c_irq_adc_unmask,
@@ -480,11 +480,11 @@ static struct irqchip s3c_irq_adc = {
480 480
481/* irq demux for adc */ 481/* irq demux for adc */
482static void s3c_irq_demux_adc(unsigned int irq, 482static void s3c_irq_demux_adc(unsigned int irq,
483 struct irqdesc *desc) 483 struct irq_desc *desc)
484{ 484{
485 unsigned int subsrc, submsk; 485 unsigned int subsrc, submsk;
486 unsigned int offset = 9; 486 unsigned int offset = 9;
487 struct irqdesc *mydesc; 487 struct irq_desc *mydesc;
488 488
489 /* read the current pending interrupts, and the mask 489 /* read the current pending interrupts, and the mask
490 * for what it is available */ 490 * for what it is available */
@@ -512,7 +512,7 @@ static void s3c_irq_demux_uart(unsigned int start)
512{ 512{
513 unsigned int subsrc, submsk; 513 unsigned int subsrc, submsk;
514 unsigned int offset = start - IRQ_S3CUART_RX0; 514 unsigned int offset = start - IRQ_S3CUART_RX0;
515 struct irqdesc *desc; 515 struct irq_desc *desc;
516 516
517 /* read the current pending interrupts, and the mask 517 /* read the current pending interrupts, and the mask
518 * for what it is available */ 518 * for what it is available */
@@ -549,7 +549,7 @@ static void s3c_irq_demux_uart(unsigned int start)
549 549
550static void 550static void
551s3c_irq_demux_uart0(unsigned int irq, 551s3c_irq_demux_uart0(unsigned int irq,
552 struct irqdesc *desc) 552 struct irq_desc *desc)
553{ 553{
554 irq = irq; 554 irq = irq;
555 s3c_irq_demux_uart(IRQ_S3CUART_RX0); 555 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +557,7 @@ s3c_irq_demux_uart0(unsigned int irq,
557 557
558static void 558static void
559s3c_irq_demux_uart1(unsigned int irq, 559s3c_irq_demux_uart1(unsigned int irq,
560 struct irqdesc *desc) 560 struct irq_desc *desc)
561{ 561{
562 irq = irq; 562 irq = irq;
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1); 563 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +565,7 @@ s3c_irq_demux_uart1(unsigned int irq,
565 565
566static void 566static void
567s3c_irq_demux_uart2(unsigned int irq, 567s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc) 568 struct irq_desc *desc)
569{ 569{
570 irq = irq; 570 irq = irq;
571 s3c_irq_demux_uart(IRQ_S3CUART_RX2); 571 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +573,7 @@ s3c_irq_demux_uart2(unsigned int irq,
573 573
574static void 574static void
575s3c_irq_demux_extint8(unsigned int irq, 575s3c_irq_demux_extint8(unsigned int irq,
576 struct irqdesc *desc) 576 struct irq_desc *desc)
577{ 577{
578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 578 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 579 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +595,7 @@ s3c_irq_demux_extint8(unsigned int irq,
595 595
596static void 596static void
597s3c_irq_demux_extint4t7(unsigned int irq, 597s3c_irq_demux_extint4t7(unsigned int irq,
598 struct irqdesc *desc) 598 struct irq_desc *desc)
599{ 599{
600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); 600 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); 601 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +738,7 @@ void __init s3c24xx_init_irq(void)
738 case IRQ_UART2: 738 case IRQ_UART2:
739 case IRQ_ADCPARENT: 739 case IRQ_ADCPARENT:
740 set_irq_chip(irqno, &s3c_irq_level_chip); 740 set_irq_chip(irqno, &s3c_irq_level_chip);
741 set_irq_handler(irqno, do_level_IRQ); 741 set_irq_handler(irqno, handle_level_irq);
742 break; 742 break;
743 743
744 case IRQ_RESERVED6: 744 case IRQ_RESERVED6:
@@ -749,7 +749,7 @@ void __init s3c24xx_init_irq(void)
749 default: 749 default:
750 //irqdbf("registering irq %d (s3c irq)\n", irqno); 750 //irqdbf("registering irq %d (s3c irq)\n", irqno);
751 set_irq_chip(irqno, &s3c_irq_chip); 751 set_irq_chip(irqno, &s3c_irq_chip);
752 set_irq_handler(irqno, do_edge_IRQ); 752 set_irq_handler(irqno, handle_edge_irq);
753 set_irq_flags(irqno, IRQF_VALID); 753 set_irq_flags(irqno, IRQF_VALID);
754 } 754 }
755 } 755 }
@@ -769,14 +769,14 @@ void __init s3c24xx_init_irq(void)
769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 769 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
770 irqdbf("registering irq %d (ext int)\n", irqno); 770 irqdbf("registering irq %d (ext int)\n", irqno);
771 set_irq_chip(irqno, &s3c_irq_eint0t4); 771 set_irq_chip(irqno, &s3c_irq_eint0t4);
772 set_irq_handler(irqno, do_edge_IRQ); 772 set_irq_handler(irqno, handle_edge_irq);
773 set_irq_flags(irqno, IRQF_VALID); 773 set_irq_flags(irqno, IRQF_VALID);
774 } 774 }
775 775
776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { 776 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
777 irqdbf("registering irq %d (extended s3c irq)\n", irqno); 777 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
778 set_irq_chip(irqno, &s3c_irqext_chip); 778 set_irq_chip(irqno, &s3c_irqext_chip);
779 set_irq_handler(irqno, do_edge_IRQ); 779 set_irq_handler(irqno, handle_edge_irq);
780 set_irq_flags(irqno, IRQF_VALID); 780 set_irq_flags(irqno, IRQF_VALID);
781 } 781 }
782 782
@@ -787,28 +787,28 @@ void __init s3c24xx_init_irq(void)
787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { 787 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); 788 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
789 set_irq_chip(irqno, &s3c_irq_uart0); 789 set_irq_chip(irqno, &s3c_irq_uart0);
790 set_irq_handler(irqno, do_level_IRQ); 790 set_irq_handler(irqno, handle_level_irq);
791 set_irq_flags(irqno, IRQF_VALID); 791 set_irq_flags(irqno, IRQF_VALID);
792 } 792 }
793 793
794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { 794 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); 795 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
796 set_irq_chip(irqno, &s3c_irq_uart1); 796 set_irq_chip(irqno, &s3c_irq_uart1);
797 set_irq_handler(irqno, do_level_IRQ); 797 set_irq_handler(irqno, handle_level_irq);
798 set_irq_flags(irqno, IRQF_VALID); 798 set_irq_flags(irqno, IRQF_VALID);
799 } 799 }
800 800
801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { 801 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); 802 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
803 set_irq_chip(irqno, &s3c_irq_uart2); 803 set_irq_chip(irqno, &s3c_irq_uart2);
804 set_irq_handler(irqno, do_level_IRQ); 804 set_irq_handler(irqno, handle_level_irq);
805 set_irq_flags(irqno, IRQF_VALID); 805 set_irq_flags(irqno, IRQF_VALID);
806 } 806 }
807 807
808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { 808 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
809 irqdbf("registering irq %d (s3c adc irq)\n", irqno); 809 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
810 set_irq_chip(irqno, &s3c_irq_adc); 810 set_irq_chip(irqno, &s3c_irq_adc);
811 set_irq_handler(irqno, do_edge_IRQ); 811 set_irq_handler(irqno, handle_edge_irq);
812 set_irq_flags(irqno, IRQF_VALID); 812 set_irq_flags(irqno, IRQF_VALID);
813 } 813 }
814 814
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
index 842a9f42c97..3686a008224 100644
--- a/arch/arm/mach-s3c2410/irq.h
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -17,7 +17,7 @@
17 17
18#define EXTINT_OFF (IRQ_EINT4 - 4) 18#define EXTINT_OFF (IRQ_EINT4 - 4)
19 19
20extern struct irqchip s3c_irq_level_chip; 20extern struct irq_chip s3c_irq_level_chip;
21 21
22static inline void 22static inline void
23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, 23s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index 7f741547658..ffcc30b23a8 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -98,7 +98,7 @@ s3c2412_irq_unmask(unsigned int irqno)
98 __raw_writel(mask & ~bitval, S3C2410_INTMSK); 98 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
99} 99}
100 100
101static struct irqchip s3c2412_irq_eint0t4 = { 101static struct irq_chip s3c2412_irq_eint0t4 = {
102 .ack = s3c2412_irq_ack, 102 .ack = s3c2412_irq_ack,
103 .mask = s3c2412_irq_mask, 103 .mask = s3c2412_irq_mask,
104 .unmask = s3c2412_irq_unmask, 104 .unmask = s3c2412_irq_unmask,
@@ -112,7 +112,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
112 112
113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { 113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
114 set_irq_chip(irqno, &s3c2412_irq_eint0t4); 114 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
115 set_irq_handler(irqno, do_edge_IRQ); 115 set_irq_handler(irqno, handle_edge_irq);
116 set_irq_flags(irqno, IRQF_VALID); 116 set_irq_flags(irqno, IRQF_VALID);
117 } 117 }
118 118
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 39db0752d53..1ba19b27ab0 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -42,10 +42,10 @@
42/* WDT/AC97 */ 42/* WDT/AC97 */
43 43
44static void s3c_irq_demux_wdtac97(unsigned int irq, 44static void s3c_irq_demux_wdtac97(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -90,7 +90,7 @@ s3c_irq_wdtac97_ack(unsigned int irqno)
90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); 90 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
91} 91}
92 92
93static struct irqchip s3c_irq_wdtac97 = { 93static struct irq_chip s3c_irq_wdtac97 = {
94 .mask = s3c_irq_wdtac97_mask, 94 .mask = s3c_irq_wdtac97_mask,
95 .unmask = s3c_irq_wdtac97_unmask, 95 .unmask = s3c_irq_wdtac97_unmask,
96 .ack = s3c_irq_wdtac97_ack, 96 .ack = s3c_irq_wdtac97_ack,
@@ -105,12 +105,12 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
105 /* add new chained handler for wdt, ac7 */ 105 /* add new chained handler for wdt, ac7 */
106 106
107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); 107 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
108 set_irq_handler(IRQ_WDT, do_level_IRQ); 108 set_irq_handler(IRQ_WDT, handle_level_irq);
109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); 109 set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
110 110
111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { 111 for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
112 set_irq_chip(irqno, &s3c_irq_wdtac97); 112 set_irq_chip(irqno, &s3c_irq_wdtac97);
113 set_irq_handler(irqno, do_level_IRQ); 113 set_irq_handler(irqno, handle_level_irq);
114 set_irq_flags(irqno, IRQF_VALID); 114 set_irq_flags(irqno, IRQF_VALID);
115 } 115 }
116 116
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 146f2109dd9..ede94636a72 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -42,10 +42,10 @@
42/* camera irq */ 42/* camera irq */
43 43
44static void s3c_irq_demux_cam(unsigned int irq, 44static void s3c_irq_demux_cam(unsigned int irq,
45 struct irqdesc *desc) 45 struct irq_desc *desc)
46{ 46{
47 unsigned int subsrc, submsk; 47 unsigned int subsrc, submsk;
48 struct irqdesc *mydesc; 48 struct irq_desc *mydesc;
49 49
50 /* read the current pending interrupts, and the mask 50 /* read the current pending interrupts, and the mask
51 * for what it is available */ 51 * for what it is available */
@@ -89,7 +89,7 @@ s3c_irq_cam_ack(unsigned int irqno)
89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); 89 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
90} 90}
91 91
92static struct irqchip s3c_irq_cam = { 92static struct irq_chip s3c_irq_cam = {
93 .mask = s3c_irq_cam_mask, 93 .mask = s3c_irq_cam_mask,
94 .unmask = s3c_irq_cam_unmask, 94 .unmask = s3c_irq_cam_unmask,
95 .ack = s3c_irq_cam_ack, 95 .ack = s3c_irq_cam_ack,
@@ -100,18 +100,18 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
100 unsigned int irqno; 100 unsigned int irqno;
101 101
102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); 102 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
103 set_irq_handler(IRQ_NFCON, do_level_IRQ); 103 set_irq_handler(IRQ_NFCON, handle_level_irq);
104 set_irq_flags(IRQ_NFCON, IRQF_VALID); 104 set_irq_flags(IRQ_NFCON, IRQF_VALID);
105 105
106 /* add chained handler for camera */ 106 /* add chained handler for camera */
107 107
108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); 108 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
109 set_irq_handler(IRQ_CAM, do_level_IRQ); 109 set_irq_handler(IRQ_CAM, handle_level_irq);
110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); 110 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
111 111
112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { 112 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
113 set_irq_chip(irqno, &s3c_irq_cam); 113 set_irq_chip(irqno, &s3c_irq_cam);
114 set_irq_handler(irqno, do_level_IRQ); 114 set_irq_handler(irqno, handle_level_irq);
115 set_irq_flags(irqno, IRQF_VALID); 115 set_irq_flags(irqno, IRQF_VALID);
116 } 116 }
117 117
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index fa6dc71bd6a..b034ad69a32 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -702,7 +702,7 @@ static u32 gpio_irq_mask[] = {
702 GPIO2_SD_CON_SLT, 702 GPIO2_SD_CON_SLT,
703}; 703};
704 704
705static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc) 705static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc)
706{ 706{
707 int i; 707 int i;
708 708
@@ -719,14 +719,14 @@ static void h3800_IRQ_demux(unsigned int irq, struct irqdesc *desc)
719 if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq); 719 if (0) printk("%s KPIO 0x%08X\n", __FUNCTION__, irq);
720 for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) 720 for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++)
721 if (irq & kpio_irq_mask[j]) 721 if (irq & kpio_irq_mask[j])
722 do_edge_IRQ(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); 722 handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j);
723 723
724 /* GPIO2 */ 724 /* GPIO2 */
725 irq = H3800_ASIC2_GPIINTFLAG; 725 irq = H3800_ASIC2_GPIINTFLAG;
726 if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq); 726 if (0) printk("%s GPIO 0x%08X\n", __FUNCTION__, irq);
727 for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) 727 for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++)
728 if (irq & gpio_irq_mask[j]) 728 if (irq & gpio_irq_mask[j])
729 do_edge_IRQ(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); 729 handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j);
730 } 730 }
731 731
732 if (i >= MAX_ASIC_ISR_LOOPS) 732 if (i >= MAX_ASIC_ISR_LOOPS)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index f4c6322ca33..5642aeca079 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -110,7 +110,7 @@ static struct irq_chip sa1100_low_gpio_chip = {
110 * and call the handler. 110 * and call the handler.
111 */ 111 */
112static void 112static void
113sa1100_high_gpio_handler(unsigned int irq, struct irqdesc *desc) 113sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
114{ 114{
115 unsigned int mask; 115 unsigned int mask;
116 116
@@ -327,19 +327,19 @@ void __init sa1100_init_irq(void)
327 327
328 for (irq = 0; irq <= 10; irq++) { 328 for (irq = 0; irq <= 10; irq++) {
329 set_irq_chip(irq, &sa1100_low_gpio_chip); 329 set_irq_chip(irq, &sa1100_low_gpio_chip);
330 set_irq_handler(irq, do_edge_IRQ); 330 set_irq_handler(irq, handle_edge_irq);
331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
332 } 332 }
333 333
334 for (irq = 12; irq <= 31; irq++) { 334 for (irq = 12; irq <= 31; irq++) {
335 set_irq_chip(irq, &sa1100_normal_chip); 335 set_irq_chip(irq, &sa1100_normal_chip);
336 set_irq_handler(irq, do_level_IRQ); 336 set_irq_handler(irq, handle_level_irq);
337 set_irq_flags(irq, IRQF_VALID); 337 set_irq_flags(irq, IRQF_VALID);
338 } 338 }
339 339
340 for (irq = 32; irq <= 48; irq++) { 340 for (irq = 32; irq <= 48; irq++) {
341 set_irq_chip(irq, &sa1100_high_gpio_chip); 341 set_irq_chip(irq, &sa1100_high_gpio_chip);
342 set_irq_handler(irq, do_edge_IRQ); 342 set_irq_handler(irq, handle_edge_irq);
343 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 343 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
344 } 344 }
345 345
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 354d5e91da5..075d4d1d63b 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -29,12 +29,12 @@
29 * is rather unfortunate. 29 * is rather unfortunate.
30 */ 30 */
31static void 31static void
32neponset_irq_handler(unsigned int irq, struct irqdesc *desc) 32neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
33{ 33{
34 unsigned int irr; 34 unsigned int irr;
35 35
36 while (1) { 36 while (1) {
37 struct irqdesc *d; 37 struct irq_desc *d;
38 38
39 /* 39 /*
40 * Acknowledge the parent IRQ. 40 * Acknowledge the parent IRQ.
@@ -168,9 +168,9 @@ static int neponset_probe(struct platform_device *dev)
168 * Setup other Neponset IRQs. SA1111 will be done by the 168 * Setup other Neponset IRQs. SA1111 will be done by the
169 * generic SA1111 code. 169 * generic SA1111 code.
170 */ 170 */
171 set_irq_handler(IRQ_NEPONSET_SMC9196, do_simple_IRQ); 171 set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
172 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); 172 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
173 set_irq_handler(IRQ_NEPONSET_USAR, do_simple_IRQ); 173 set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
174 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); 174 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
175 175
176 /* 176 /*
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 297ecf13065..00a6c146686 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -82,7 +82,7 @@ void __init shark_init_irq(void)
82 82
83 for (irq = 0; irq < NR_IRQS; irq++) { 83 for (irq = 0; irq < NR_IRQS; irq++) {
84 set_irq_chip(irq, &fb_chip); 84 set_irq_chip(irq, &fb_chip);
85 set_irq_handler(irq, do_edge_IRQ); 85 set_irq_handler(irq, handle_edge_irq);
86 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 86 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
87 } 87 }
88 88
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3b8576111c1..dcc2ca3dcde 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -77,7 +77,7 @@ static struct irq_chip sic_chip = {
77}; 77};
78 78
79static void 79static void
80sic_handle_irq(unsigned int irq, struct irqdesc *desc) 80sic_handle_irq(unsigned int irq, struct irq_desc *desc)
81{ 81{
82 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS); 82 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
83 83
@@ -123,7 +123,7 @@ void __init versatile_init_irq(void)
123 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 123 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
124 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) { 124 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
125 set_irq_chip(i, &sic_chip); 125 set_irq_chip(i, &sic_chip);
126 set_irq_handler(i, do_level_IRQ); 126 set_irq_handler(i, handle_level_irq);
127 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 127 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
128 } 128 }
129 } 129 }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8162eed8b50..4f2fd559133 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -410,7 +410,7 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
410 trigger & __IRQT_RISEDGE); 410 trigger & __IRQT_RISEDGE);
411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
412 trigger & __IRQT_FALEDGE); 412 trigger & __IRQT_FALEDGE);
413 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level 413 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
414 * triggering requested. */ 414 * triggering requested. */
415} 415}
416 416
@@ -783,7 +783,7 @@ void omap_free_gpio(int gpio)
783 * line's interrupt handler has been run, we may miss some nested 783 * line's interrupt handler has been run, we may miss some nested
784 * interrupts. 784 * interrupts.
785 */ 785 */
786static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc) 786static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
787{ 787{
788 void __iomem *isr_reg = NULL; 788 void __iomem *isr_reg = NULL;
789 u32 isr; 789 u32 isr;
@@ -853,7 +853,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
853 853
854 gpio_irq = bank->virtual_irq_start; 854 gpio_irq = bank->virtual_irq_start;
855 for (; isr != 0; isr >>= 1, gpio_irq++) { 855 for (; isr != 0; isr >>= 1, gpio_irq++) {
856 struct irqdesc *d; 856 struct irq_desc *d;
857 int irq_mask; 857 int irq_mask;
858 if (!(isr & 1)) 858 if (!(isr & 1))
859 continue; 859 continue;
@@ -1092,7 +1092,7 @@ static int __init _omap_gpio_init(void)
1092 set_irq_chip(j, &mpuio_irq_chip); 1092 set_irq_chip(j, &mpuio_irq_chip);
1093 else 1093 else
1094 set_irq_chip(j, &gpio_irq_chip); 1094 set_irq_chip(j, &gpio_irq_chip);
1095 set_irq_handler(j, do_simple_IRQ); 1095 set_irq_handler(j, handle_simple_irq);
1096 set_irq_flags(j, IRQF_VALID); 1096 set_irq_flags(j, IRQF_VALID);
1097 } 1097 }
1098 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1098 set_irq_chained_handler(bank->irq, gpio_irq_handler);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 14:23:04 -0500