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-rw-r--r--arch/arm/plat-samsung/include/plat/adc-core.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/audio-simtec.h37
-rw-r--r--arch/arm/plat-samsung/include/plat/camport.h28
-rw-r--r--arch/arm/plat-samsung/include/plat/common-smdk.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h288
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h151
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-ops.h63
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h (renamed from arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h)24
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-s3c24xx.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/ehci.h21
-rw-r--r--arch/arm/plat-samsung/include/plat/exynos4.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-s3c2410.h72
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/fiq.h13
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h172
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h34
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h97
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-fns.h98
-rw-r--r--arch/arm/plat-samsung/include/plat/iic.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/irq.h116
-rw-r--r--arch/arm/plat-samsung/include/plat/irqs.h80
-rw-r--r--arch/arm/plat-samsung/include/plat/mci.h52
-rw-r--r--arch/arm/plat-samsung/include/plat/mfc.h27
-rw-r--r--arch/arm/plat-samsung/include/plat/mipi_csis.h43
-rw-r--r--arch/arm/plat-samsung/include/plat/pll.h323
-rw-r--r--arch/arm/plat-samsung/include/plat/pll6553x.h51
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/pwm-clock.h81
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-adc.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-dma.h151
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-iis.h70
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-spi.h48
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-srom.h54
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-udc.h151
-rw-r--r--arch/arm/plat-samsung/include/plat/reset.h16
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h32
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2410.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2412.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2416.h31
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c2443.h52
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c244x.h42
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c6400.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c6410.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h55
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-time.h40
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p6440.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p6450.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/s5pc100.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/s5pv210.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h57
-rw-r--r--arch/arm/plat-samsung/include/plat/sysmmu.h95
-rw-r--r--arch/arm/plat-samsung/include/plat/system-reset.h31
-rw-r--r--arch/arm/plat-samsung/include/plat/tv-core.h44
-rw-r--r--arch/arm/plat-samsung/include/plat/udc.h57
-rw-r--r--arch/arm/plat-samsung/include/plat/usb-phy.h22
57 files changed, 2811 insertions, 464 deletions
diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/plat-samsung/include/plat/adc-core.h
index a281568d585..a927bee5535 100644
--- a/arch/arm/plat-samsung/include/plat/adc-core.h
+++ b/arch/arm/plat-samsung/include/plat/adc-core.h
@@ -20,7 +20,7 @@
20/* re-define device name depending on support. */ 20/* re-define device name depending on support. */
21static inline void s3c_adc_setname(char *name) 21static inline void s3c_adc_setname(char *name)
22{ 22{
23#ifdef CONFIG_SAMSUNG_DEV_ADC 23#if defined(CONFIG_SAMSUNG_DEV_ADC) || defined(CONFIG_PLAT_S3C24XX)
24 s3c_device_adc.name = name; 24 s3c_device_adc.name = name;
25#endif 25#endif
26} 26}
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
new file mode 100644
index 00000000000..5345364e742
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -0,0 +1,37 @@
1/* arch/arm/plat-samsung/include/plat/audio-simtec.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Simtec Audio support.
12*/
13
14/**
15 * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
16 * @use_mpllin: Select codec clock from MPLLin
17 * @output_cdclk: Need to output CDCLK to the codec
18 * @have_mic: Set if we have a MIC socket
19 * @have_lout: Set if we have a LineOut socket
20 * @amp_gpio: GPIO pin to enable the AMP
21 * @amp_gain: Option GPIO to control AMP gain
22 */
23struct s3c24xx_audio_simtec_pdata {
24 unsigned int use_mpllin:1;
25 unsigned int output_cdclk:1;
26
27 unsigned int have_mic:1;
28 unsigned int have_lout:1;
29
30 int amp_gpio;
31 int amp_gain[2];
32
33 void (*startup)(void);
34};
35
36extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
37 struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-samsung/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h
new file mode 100644
index 00000000000..a5708bf84b3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/camport.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series camera interface helper functions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __PLAT_SAMSUNG_CAMPORT_H_
12#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
13
14enum s5p_camport_id {
15 S5P_CAMPORT_A,
16 S5P_CAMPORT_B,
17};
18
19/*
20 * The helper functions to configure GPIO for the camera parallel bus.
21 * The camera port can be multiplexed with any FIMC entity, even multiple
22 * FIMC entities are allowed to be attached to a single port simultaneously.
23 * These functions are to be used in the board setup code.
24 */
25int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
26int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
27
28#endif /* __PLAT_SAMSUNG_CAMPORT_H */
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/plat-samsung/include/plat/common-smdk.h
new file mode 100644
index 00000000000..ba028f1ed30
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/common-smdk.h
@@ -0,0 +1,15 @@
1/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Common code for SMDK2410 and SMDK2440 boards
7 *
8 * http://www.fluff.org/ben/smdk2440/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern void smdk_machine_init(void);
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
new file mode 100644
index 00000000000..dac4760c0f0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -0,0 +1,288 @@
1/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
2 *
3 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - core support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <plat/cpu-freq.h>
15
16struct seq_file;
17
18#define MAX_BANKS (8)
19#define S3C2412_MAX_IO (8)
20
21/**
22 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
23 * @bankcon: The cached version of settings in this structure.
24 * @tacp:
25 * @tacs: Time from address valid to nCS asserted.
26 * @tcos: Time from nCS asserted to nOE or nWE asserted.
27 * @tacc: Time that nOE or nWE is asserted.
28 * @tcoh: Time nCS is held after nOE or nWE are released.
29 * @tcah: Time address is held for after
30 * @nwait_en: Whether nWAIT is enabled for this bank.
31 *
32 * This structure represents the IO timings for a S3C2410 style IO bank
33 * used by the CPU frequency support if it needs to change the settings
34 * of the IO.
35 */
36struct s3c2410_iobank_timing {
37 unsigned long bankcon;
38 unsigned int tacp;
39 unsigned int tacs;
40 unsigned int tcos;
41 unsigned int tacc;
42 unsigned int tcoh; /* nCS hold afrer nOE/nWE */
43 unsigned int tcah; /* Address hold after nCS */
44 unsigned char nwait_en; /* nWait enabled for bank. */
45};
46
47/**
48 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
49 * @idcy: The idle cycle time between transactions.
50 * @wstrd: nCS release to end of read cycle.
51 * @wstwr: nCS release to end of write cycle.
52 * @wstoen: nCS assertion to nOE assertion time.
53 * @wstwen: nCS assertion to nWE assertion time.
54 * @wstbrd: Burst ready delay.
55 * @smbidcyr: Register cache for smbidcyr value.
56 * @smbwstrd: Register cache for smbwstrd value.
57 * @smbwstwr: Register cache for smbwstwr value.
58 * @smbwstoen: Register cache for smbwstoen value.
59 * @smbwstwen: Register cache for smbwstwen value.
60 * @smbwstbrd: Register cache for smbwstbrd value.
61 *
62 * Timing information for a IO bank on an S3C2412 or similar system which
63 * uses a PL093 block.
64 */
65struct s3c2412_iobank_timing {
66 unsigned int idcy;
67 unsigned int wstrd;
68 unsigned int wstwr;
69 unsigned int wstoen;
70 unsigned int wstwen;
71 unsigned int wstbrd;
72
73 /* register cache */
74 unsigned char smbidcyr;
75 unsigned char smbwstrd;
76 unsigned char smbwstwr;
77 unsigned char smbwstoen;
78 unsigned char smbwstwen;
79 unsigned char smbwstbrd;
80};
81
82union s3c_iobank {
83 struct s3c2410_iobank_timing *io_2410;
84 struct s3c2412_iobank_timing *io_2412;
85};
86
87/**
88 * struct s3c_iotimings - Chip IO timings holder
89 * @bank: The timings for each IO bank.
90 */
91struct s3c_iotimings {
92 union s3c_iobank bank[MAX_BANKS];
93};
94
95/**
96 * struct s3c_plltab - PLL table information.
97 * @vals: List of PLL values.
98 * @size: Size of the PLL table @vals.
99 */
100struct s3c_plltab {
101 struct s3c_pllval *vals;
102 int size;
103};
104
105/**
106 * struct s3c_cpufreq_config - current cpu frequency configuration
107 * @freq: The current settings for the core clocks.
108 * @max: Maxium settings, derived from core, board and user settings.
109 * @pll: The PLL table entry for the current PLL settings.
110 * @divs: The divisor settings for the core clocks.
111 * @info: The current core driver information.
112 * @board: The information for the board we are running on.
113 * @lock_pll: Set if the PLL settings cannot be changed.
114 *
115 * This is for the core drivers that need to know information about
116 * the current settings and values. It should not be needed by any
117 * device drivers.
118*/
119struct s3c_cpufreq_config {
120 struct s3c_freq freq;
121 struct s3c_freq max;
122 struct cpufreq_frequency_table pll;
123 struct s3c_clkdivs divs;
124 struct s3c_cpufreq_info *info; /* for core, not drivers */
125 struct s3c_cpufreq_board *board;
126
127 unsigned int lock_pll:1;
128};
129
130/**
131 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
132 * @name: The name of this implementation.
133 * @max: The maximum frequencies for the system.
134 * @latency: Transition latency to give to cpufreq.
135 * @locktime_m: The lock-time in uS for the MPLL.
136 * @locktime_u: The lock-time in uS for the UPLL.
137 * @locttime_bits: The number of bits each LOCKTIME field.
138 * @need_pll: Set if this driver needs to change the PLL values to achieve
139 * any frequency changes. This is really only need by devices like the
140 * S3C2410 where there is no or limited divider between the PLL and the
141 * ARMCLK.
142 * @resume_clocks: Update the clocks on resume.
143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
144 * @set_iotiming: Update the IO timings from the cached copies calculated
145 * from the @calc_iotiming entry when changing the frequency.
146 * @calc_iotiming: Calculate and update the cached copies of the IO timings
147 * from the newly calculated frequencies.
148 * @calc_freqtable: Calculate (fill in) the given frequency table from the
149 * current frequency configuration. If the table passed in is NULL,
150 * then the return is the number of elements to be filled for allocation
151 * of the table.
152 * @set_refresh: Set the memory refresh configuration.
153 * @set_fvco: Set the PLL frequencies.
154 * @set_divs: Update the clock divisors.
155 * @calc_divs: Calculate the clock divisors.
156 */
157struct s3c_cpufreq_info {
158 const char *name;
159 struct s3c_freq max;
160
161 unsigned int latency;
162
163 unsigned int locktime_m;
164 unsigned int locktime_u;
165 unsigned char locktime_bits;
166
167 unsigned int need_pll:1;
168
169 /* driver routines */
170
171 void (*resume_clocks)(void);
172
173 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
174 struct s3c_iotimings *timings);
175
176 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
177 struct s3c_iotimings *timings);
178
179 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
180 struct s3c_iotimings *timings);
181
182 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
183 struct cpufreq_frequency_table *t,
184 size_t table_size);
185
186 void (*debug_io_show)(struct seq_file *seq,
187 struct s3c_cpufreq_config *cfg,
188 union s3c_iobank *iob);
189
190 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
191 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
192 void (*set_divs)(struct s3c_cpufreq_config *cfg);
193 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
194};
195
196extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
197
198extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
199 unsigned int plls_no);
200
201/* exports and utilities for debugfs */
202extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
203extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
204
205extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
206 struct s3c_cpufreq_config *cfg,
207 union s3c_iobank *iob);
208
209extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
210 struct s3c_cpufreq_config *cfg,
211 union s3c_iobank *iob);
212
213#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
214#define s3c_cpufreq_debugfs_call(x) x
215#else
216#define s3c_cpufreq_debugfs_call(x) NULL
217#endif
218
219/* Useful utility functions. */
220
221extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
222
223/* S3C2410 and compatible exported functions */
224
225extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
226extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
227
228#ifdef CONFIG_S3C2410_IOTIMING
229extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
230 struct s3c_iotimings *iot);
231
232extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
233 struct s3c_iotimings *timings);
234
235extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
236 struct s3c_iotimings *iot);
237#else
238#define s3c2410_iotiming_calc NULL
239#define s3c2410_iotiming_get NULL
240#define s3c2410_iotiming_set NULL
241#endif /* CONFIG_S3C2410_IOTIMING */
242
243/* S3C2412 compatible routines */
244
245extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
246 struct s3c_iotimings *timings);
247
248extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
249 struct s3c_iotimings *timings);
250
251extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
252 struct s3c_iotimings *iot);
253
254extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
255 struct s3c_iotimings *iot);
256
257#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
258#define s3c_freq_dbg(x...) printk(KERN_INFO x)
259#else
260#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
261#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
262
263#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
264#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
265#else
266#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
267#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
268
269static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
270 int index, size_t table_size,
271 unsigned int freq)
272{
273 if (index < 0)
274 return index;
275
276 if (table) {
277 if (index >= table_size)
278 return -ENOMEM;
279
280 s3c_freq_dbg("%s: { %d = %u kHz }\n",
281 __func__, index, freq);
282
283 table[index].index = index;
284 table[index].frequency = freq;
285 }
286
287 return index + 1;
288}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 54f370f0fc0..40fd7b6b5e6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -25,7 +25,6 @@ extern unsigned long samsung_cpu_id;
25 25
26#define S3C6400_CPU_ID 0x36400000 26#define S3C6400_CPU_ID 0x36400000
27#define S3C6410_CPU_ID 0x36410000 27#define S3C6410_CPU_ID 0x36410000
28#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID)
29#define S3C64XX_CPU_MASK 0xFFFFF000 28#define S3C64XX_CPU_MASK 0xFFFFF000
30 29
31#define S5P6440_CPU_ID 0x56440000 30#define S5P6440_CPU_ID 0x56440000
@@ -50,7 +49,8 @@ static inline int is_samsung_##name(void) \
50} 49}
51 50
52IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) 51IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
53IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK) 52IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
53IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
54IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) 54IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
55IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) 55IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
56IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) 56IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
@@ -69,7 +69,7 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
69#endif 69#endif
70 70
71#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) 71#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
72# define soc_is_s3c64xx() is_samsung_s3c64xx() 72# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410())
73#else 73#else
74# define soc_is_s3c64xx() 0 74# define soc_is_s3c64xx() 0
75#endif 75#endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 24ebb1e1de4..ab633c9c2ae 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -30,30 +30,24 @@ extern struct s3c24xx_uart_resources s5p_uart_resources[];
30extern struct platform_device *s3c24xx_uart_devs[]; 30extern struct platform_device *s3c24xx_uart_devs[];
31extern struct platform_device *s3c24xx_uart_src[]; 31extern struct platform_device *s3c24xx_uart_src[];
32 32
33extern struct platform_device s3c_device_timer[]; 33extern struct platform_device s3c64xx_device_ac97;
34
35extern struct platform_device s3c64xx_device_iis0; 34extern struct platform_device s3c64xx_device_iis0;
36extern struct platform_device s3c64xx_device_iis1; 35extern struct platform_device s3c64xx_device_iis1;
37extern struct platform_device s3c64xx_device_iisv4; 36extern struct platform_device s3c64xx_device_iisv4;
38 37extern struct platform_device s3c64xx_device_onenand1;
39extern struct platform_device s3c64xx_device_spi0;
40extern struct platform_device s3c64xx_device_spi1;
41
42extern struct platform_device samsung_asoc_dma;
43extern struct platform_device samsung_asoc_idma;
44
45extern struct platform_device s3c64xx_device_pcm0; 38extern struct platform_device s3c64xx_device_pcm0;
46extern struct platform_device s3c64xx_device_pcm1; 39extern struct platform_device s3c64xx_device_pcm1;
40extern struct platform_device s3c64xx_device_spi0;
41extern struct platform_device s3c64xx_device_spi1;
47 42
48extern struct platform_device s3c64xx_device_ac97; 43extern struct platform_device s3c_device_adc;
49 44extern struct platform_device s3c_device_cfcon;
50extern struct platform_device s3c_device_ts;
51
52extern struct platform_device s3c_device_fb; 45extern struct platform_device s3c_device_fb;
53extern struct platform_device s5p_device_fimd0; 46extern struct platform_device s3c_device_hwmon;
54extern struct platform_device s3c_device_ohci; 47extern struct platform_device s3c_device_hsmmc0;
55extern struct platform_device s3c_device_lcd; 48extern struct platform_device s3c_device_hsmmc1;
56extern struct platform_device s3c_device_wdt; 49extern struct platform_device s3c_device_hsmmc2;
50extern struct platform_device s3c_device_hsmmc3;
57extern struct platform_device s3c_device_i2c0; 51extern struct platform_device s3c_device_i2c0;
58extern struct platform_device s3c_device_i2c1; 52extern struct platform_device s3c_device_i2c1;
59extern struct platform_device s3c_device_i2c2; 53extern struct platform_device s3c_device_i2c2;
@@ -62,93 +56,90 @@ extern struct platform_device s3c_device_i2c4;
62extern struct platform_device s3c_device_i2c5; 56extern struct platform_device s3c_device_i2c5;
63extern struct platform_device s3c_device_i2c6; 57extern struct platform_device s3c_device_i2c6;
64extern struct platform_device s3c_device_i2c7; 58extern struct platform_device s3c_device_i2c7;
59extern struct platform_device s3c_device_iis;
60extern struct platform_device s3c_device_lcd;
61extern struct platform_device s3c_device_nand;
62extern struct platform_device s3c_device_ohci;
63extern struct platform_device s3c_device_onenand;
65extern struct platform_device s3c_device_rtc; 64extern struct platform_device s3c_device_rtc;
66extern struct platform_device s3c_device_adc;
67extern struct platform_device s3c_device_sdi; 65extern struct platform_device s3c_device_sdi;
68extern struct platform_device s3c_device_iis;
69extern struct platform_device s3c_device_hwmon;
70extern struct platform_device s3c_device_hsmmc0;
71extern struct platform_device s3c_device_hsmmc1;
72extern struct platform_device s3c_device_hsmmc2;
73extern struct platform_device s3c_device_hsmmc3;
74extern struct platform_device s3c_device_cfcon;
75
76extern struct platform_device s3c_device_spi0; 66extern struct platform_device s3c_device_spi0;
77extern struct platform_device s3c_device_spi1; 67extern struct platform_device s3c_device_spi1;
78 68extern struct platform_device s3c_device_ts;
79extern struct platform_device s5pc100_device_spi0; 69extern struct platform_device s3c_device_timer[];
80extern struct platform_device s5pc100_device_spi1;
81extern struct platform_device s5pc100_device_spi2;
82extern struct platform_device s5pv210_device_spi0;
83extern struct platform_device s5pv210_device_spi1;
84extern struct platform_device s5p64x0_device_spi0;
85extern struct platform_device s5p64x0_device_spi1;
86
87extern struct platform_device s3c_device_hwmon;
88
89extern struct platform_device s3c_device_nand;
90extern struct platform_device s3c_device_onenand;
91extern struct platform_device s3c64xx_device_onenand1;
92extern struct platform_device s5p_device_onenand;
93
94extern struct platform_device s3c_device_usbgadget; 70extern struct platform_device s3c_device_usbgadget;
95extern struct platform_device s3c_device_usb_hsudc;
96extern struct platform_device s3c_device_usb_hsotg; 71extern struct platform_device s3c_device_usb_hsotg;
72extern struct platform_device s3c_device_usb_hsudc;
73extern struct platform_device s3c_device_wdt;
97 74
98extern struct platform_device s5pv210_device_ac97; 75extern struct platform_device s5p_device_ehci;
99extern struct platform_device s5pv210_device_pcm0; 76extern struct platform_device s5p_device_fimc0;
100extern struct platform_device s5pv210_device_pcm1; 77extern struct platform_device s5p_device_fimc1;
101extern struct platform_device s5pv210_device_pcm2; 78extern struct platform_device s5p_device_fimc2;
102extern struct platform_device s5pv210_device_iis0; 79extern struct platform_device s5p_device_fimc3;
103extern struct platform_device s5pv210_device_iis1; 80extern struct platform_device s5p_device_fimc_md;
104extern struct platform_device s5pv210_device_iis2; 81extern struct platform_device s5p_device_fimd0;
105extern struct platform_device s5pv210_device_spdif; 82extern struct platform_device s5p_device_hdmi;
106 83extern struct platform_device s5p_device_i2c_hdmiphy;
107extern struct platform_device exynos4_device_ac97; 84extern struct platform_device s5p_device_mfc;
108extern struct platform_device exynos4_device_pcm0; 85extern struct platform_device s5p_device_mfc_l;
109extern struct platform_device exynos4_device_pcm1; 86extern struct platform_device s5p_device_mfc_r;
110extern struct platform_device exynos4_device_pcm2; 87extern struct platform_device s5p_device_mipi_csis0;
111extern struct platform_device exynos4_device_i2s0; 88extern struct platform_device s5p_device_mipi_csis1;
112extern struct platform_device exynos4_device_i2s1; 89extern struct platform_device s5p_device_mixer;
113extern struct platform_device exynos4_device_i2s2; 90extern struct platform_device s5p_device_onenand;
114extern struct platform_device exynos4_device_spdif; 91extern struct platform_device s5p_device_sdo;
115extern struct platform_device exynos4_device_pd[];
116extern struct platform_device exynos4_device_ahci;
117extern struct platform_device exynos4_device_dwmci;
118 92
119extern struct platform_device s5p6440_device_pcm;
120extern struct platform_device s5p6440_device_iis; 93extern struct platform_device s5p6440_device_iis;
94extern struct platform_device s5p6440_device_pcm;
121 95
122extern struct platform_device s5p6450_device_iis0; 96extern struct platform_device s5p6450_device_iis0;
123extern struct platform_device s5p6450_device_iis1; 97extern struct platform_device s5p6450_device_iis1;
124extern struct platform_device s5p6450_device_iis2; 98extern struct platform_device s5p6450_device_iis2;
125extern struct platform_device s5p6450_device_pcm0; 99extern struct platform_device s5p6450_device_pcm0;
126 100
101extern struct platform_device s5p64x0_device_spi0;
102extern struct platform_device s5p64x0_device_spi1;
103
127extern struct platform_device s5pc100_device_ac97; 104extern struct platform_device s5pc100_device_ac97;
128extern struct platform_device s5pc100_device_pcm0;
129extern struct platform_device s5pc100_device_pcm1;
130extern struct platform_device s5pc100_device_iis0; 105extern struct platform_device s5pc100_device_iis0;
131extern struct platform_device s5pc100_device_iis1; 106extern struct platform_device s5pc100_device_iis1;
132extern struct platform_device s5pc100_device_iis2; 107extern struct platform_device s5pc100_device_iis2;
108extern struct platform_device s5pc100_device_pcm0;
109extern struct platform_device s5pc100_device_pcm1;
133extern struct platform_device s5pc100_device_spdif; 110extern struct platform_device s5pc100_device_spdif;
111extern struct platform_device s5pc100_device_spi0;
112extern struct platform_device s5pc100_device_spi1;
113extern struct platform_device s5pc100_device_spi2;
134 114
135extern struct platform_device samsung_device_keypad; 115extern struct platform_device s5pv210_device_ac97;
136 116extern struct platform_device s5pv210_device_iis0;
137extern struct platform_device s5p_device_fimc0; 117extern struct platform_device s5pv210_device_iis1;
138extern struct platform_device s5p_device_fimc1; 118extern struct platform_device s5pv210_device_iis2;
139extern struct platform_device s5p_device_fimc2; 119extern struct platform_device s5pv210_device_pcm0;
140extern struct platform_device s5p_device_fimc3; 120extern struct platform_device s5pv210_device_pcm1;
141 121extern struct platform_device s5pv210_device_pcm2;
142extern struct platform_device s5p_device_mfc; 122extern struct platform_device s5pv210_device_spdif;
143extern struct platform_device s5p_device_mfc_l; 123extern struct platform_device s5pv210_device_spi0;
144extern struct platform_device s5p_device_mfc_r; 124extern struct platform_device s5pv210_device_spi1;
145extern struct platform_device s5p_device_mipi_csis0;
146extern struct platform_device s5p_device_mipi_csis1;
147
148extern struct platform_device s5p_device_ehci;
149 125
126extern struct platform_device exynos4_device_ac97;
127extern struct platform_device exynos4_device_ahci;
128extern struct platform_device exynos4_device_dwmci;
129extern struct platform_device exynos4_device_i2s0;
130extern struct platform_device exynos4_device_i2s1;
131extern struct platform_device exynos4_device_i2s2;
132extern struct platform_device exynos4_device_pcm0;
133extern struct platform_device exynos4_device_pcm1;
134extern struct platform_device exynos4_device_pcm2;
135extern struct platform_device exynos4_device_pd[];
136extern struct platform_device exynos4_device_spdif;
150extern struct platform_device exynos4_device_sysmmu; 137extern struct platform_device exynos4_device_sysmmu;
151 138
139extern struct platform_device samsung_asoc_dma;
140extern struct platform_device samsung_asoc_idma;
141extern struct platform_device samsung_device_keypad;
142
152/* s3c2440 specific devices */ 143/* s3c2440 specific devices */
153 144
154#ifdef CONFIG_CPU_S3C2440 145#ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
new file mode 100644
index 00000000000..4c1a363526c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -0,0 +1,63 @@
1/* arch/arm/plat-samsung/include/plat/dma-ops.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __SAMSUNG_DMA_OPS_H_
14#define __SAMSUNG_DMA_OPS_H_ __FILE__
15
16#include <linux/dmaengine.h>
17
18struct samsung_dma_prep_info {
19 enum dma_transaction_type cap;
20 enum dma_data_direction direction;
21 dma_addr_t buf;
22 unsigned long period;
23 unsigned long len;
24 void (*fp)(void *data);
25 void *fp_param;
26};
27
28struct samsung_dma_info {
29 enum dma_transaction_type cap;
30 enum dma_data_direction direction;
31 enum dma_slave_buswidth width;
32 dma_addr_t fifo;
33 struct s3c2410_dma_client *client;
34};
35
36struct samsung_dma_ops {
37 unsigned (*request)(enum dma_ch ch, struct samsung_dma_info *info);
38 int (*release)(unsigned ch, struct s3c2410_dma_client *client);
39 int (*prepare)(unsigned ch, struct samsung_dma_prep_info *info);
40 int (*trigger)(unsigned ch);
41 int (*started)(unsigned ch);
42 int (*flush)(unsigned ch);
43 int (*stop)(unsigned ch);
44};
45
46extern void *samsung_dmadev_get_ops(void);
47extern void *s3c_dma_get_ops(void);
48
49static inline void *__samsung_dma_get_ops(void)
50{
51 if (samsung_dma_is_dmadev())
52 return samsung_dmadev_get_ops();
53 else
54 return s3c_dma_get_ops();
55}
56
57/*
58 * samsung_dma_get_ops
59 * get the set of samsung dma operations
60 */
61#define samsung_dma_get_ops() __samsung_dma_get_ops()
62
63#endif /* __SAMSUNG_DMA_OPS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 81074421312..2e55e595867 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -8,11 +8,8 @@
8 * (at your option) any later version. 8 * (at your option) any later version.
9 */ 9 */
10 10
11#ifndef __S3C_DMA_PL330_H_ 11#ifndef __DMA_PL330_H_
12#define __S3C_DMA_PL330_H_ 12#define __DMA_PL330_H_ __FILE__
13
14#define S3C2410_DMAF_AUTOSTART (1 << 0)
15#define S3C2410_DMAF_CIRCULAR (1 << 1)
16 13
17/* 14/*
18 * PL330 can assign any channel to communicate with 15 * PL330 can assign any channel to communicate with
@@ -20,7 +17,7 @@
20 * For the sake of consistency across client drivers, 17 * For the sake of consistency across client drivers,
21 * We keep the channel names unchanged and only add 18 * We keep the channel names unchanged and only add
22 * missing peripherals are added. 19 * missing peripherals are added.
23 * Order is not important since S3C PL330 API driver 20 * Order is not important since DMA PL330 API driver
24 * use these just as IDs. 21 * use these just as IDs.
25 */ 22 */
26enum dma_ch { 23enum dma_ch {
@@ -88,11 +85,20 @@ enum dma_ch {
88 DMACH_MAX, 85 DMACH_MAX,
89}; 86};
90 87
91static inline bool s3c_dma_has_circular(void) 88struct s3c2410_dma_client {
89 char *name;
90};
91
92static inline bool samsung_dma_has_circular(void)
93{
94 return true;
95}
96
97static inline bool samsung_dma_is_dmadev(void)
92{ 98{
93 return true; 99 return true;
94} 100}
95 101
96#include <plat/dma.h> 102#include <plat/dma-ops.h>
97 103
98#endif /* __S3C_DMA_PL330_H_ */ 104#endif /* __DMA_PL330_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index ab9bce637cb..1c1ed548125 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -41,7 +41,7 @@ struct s3c24xx_dma_selection {
41 41
42 void (*direction)(struct s3c2410_dma_chan *chan, 42 void (*direction)(struct s3c2410_dma_chan *chan,
43 struct s3c24xx_dma_map *map, 43 struct s3c24xx_dma_map *map,
44 enum s3c2410_dmasrc dir); 44 enum dma_data_direction dir);
45}; 45};
46 46
47extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel); 47extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
index 8c273b7a6f5..b9061128abd 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -10,17 +10,14 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <linux/dma-mapping.h>
14
13enum s3c2410_dma_buffresult { 15enum s3c2410_dma_buffresult {
14 S3C2410_RES_OK, 16 S3C2410_RES_OK,
15 S3C2410_RES_ERR, 17 S3C2410_RES_ERR,
16 S3C2410_RES_ABORT 18 S3C2410_RES_ABORT
17}; 19};
18 20
19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */
22};
23
24/* enum s3c2410_chan_op 21/* enum s3c2410_chan_op
25 * 22 *
26 * operation codes passed to the DMA code by the user, and also used 23 * operation codes passed to the DMA code by the user, and also used
@@ -112,7 +109,7 @@ extern int s3c2410_dma_config(enum dma_ch channel, int xferunit);
112*/ 109*/
113 110
114extern int s3c2410_dma_devconfig(enum dma_ch channel, 111extern int s3c2410_dma_devconfig(enum dma_ch channel,
115 enum s3c2410_dmasrc source, unsigned long devaddr); 112 enum dma_data_direction source, unsigned long devaddr);
116 113
117/* s3c2410_dma_getposition 114/* s3c2410_dma_getposition
118 * 115 *
@@ -126,3 +123,4 @@ extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
126extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn); 123extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
127 124
128 125
126#include <plat/dma-ops.h>
diff --git a/arch/arm/plat-samsung/include/plat/ehci.h b/arch/arm/plat-samsung/include/plat/ehci.h
new file mode 100644
index 00000000000..5f28cae1858
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/ehci.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_SAMSUNG_EHCI_H
12#define __PLAT_SAMSUNG_EHCI_H __FILE__
13
14struct s5p_ehci_platdata {
15 int (*phy_init)(struct platform_device *pdev, int type);
16 int (*phy_exit)(struct platform_device *pdev, int type);
17};
18
19extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
20
21#endif /* __PLAT_SAMSUNG_EHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h
new file mode 100644
index 00000000000..f546e88ebc9
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/exynos4.h
@@ -0,0 +1,35 @@
1/* linux/arch/arm/plat-samsung/include/plat/exynos4.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for exynos4 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for EXYNOS4 related SoCs */
14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void);
17extern void exynos4210_register_clocks(void);
18extern void exynos4212_register_clocks(void);
19extern void exynos4_setup_clocks(void);
20
21#ifdef CONFIG_ARCH_EXYNOS
22extern int exynos_init(void);
23extern void exynos4_init_irq(void);
24extern void exynos4_map_io(void);
25extern void exynos4_init_clocks(int xtal);
26extern struct sys_timer exynos4_timer;
27
28#define exynos4_init_uarts exynos4_common_init_uarts
29
30#else
31#define exynos4_init_clocks NULL
32#define exynos4_init_uarts NULL
33#define exynos4_map_io NULL
34#define exynos_init NULL
35#endif
diff --git a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h
new file mode 100644
index 00000000000..4e5d9588b5b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h
@@ -0,0 +1,72 @@
1/* arch/arm/plat-samsung/include/plat/fb-s3c2410.h
2 *
3 * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 * Inspired by pxafb.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_PLAT_FB_S3C2410_H
13#define __ASM_PLAT_FB_S3C2410_H __FILE__
14
15struct s3c2410fb_hw {
16 unsigned long lcdcon1;
17 unsigned long lcdcon2;
18 unsigned long lcdcon3;
19 unsigned long lcdcon4;
20 unsigned long lcdcon5;
21};
22
23/* LCD description */
24struct s3c2410fb_display {
25 /* LCD type */
26 unsigned type;
27
28 /* Screen size */
29 unsigned short width;
30 unsigned short height;
31
32 /* Screen info */
33 unsigned short xres;
34 unsigned short yres;
35 unsigned short bpp;
36
37 unsigned pixclock; /* pixclock in picoseconds */
38 unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
39 unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
40 unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
41 unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
42 unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
43 unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
44
45 /* lcd configuration registers */
46 unsigned long lcdcon5;
47};
48
49struct s3c2410fb_mach_info {
50
51 struct s3c2410fb_display *displays; /* attached diplays info */
52 unsigned num_displays; /* number of defined displays */
53 unsigned default_display;
54
55 /* GPIOs */
56
57 unsigned long gpcup;
58 unsigned long gpcup_mask;
59 unsigned long gpccon;
60 unsigned long gpccon_mask;
61 unsigned long gpdup;
62 unsigned long gpdup_mask;
63 unsigned long gpdcon;
64 unsigned long gpdcon_mask;
65
66 /* lpc3600 control register */
67 unsigned long lpcsel;
68};
69
70extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
71
72#endif /* __ASM_PLAT_FB_S3C2410_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 01f10e4d00c..0fedf47fa50 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -109,4 +109,11 @@ extern void s5pv210_fb_gpio_setup_24bpp(void);
109 */ 109 */
110extern void exynos4_fimd0_gpio_setup_24bpp(void); 110extern void exynos4_fimd0_gpio_setup_24bpp(void);
111 111
112/**
113 * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD
114 *
115 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
116 */
117extern void s5p64x0_fb_gpio_setup_24bpp(void);
118
112#endif /* __PLAT_S3C_FB_H */ 119#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h
new file mode 100644
index 00000000000..535d06a3562
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fiq.h
@@ -0,0 +1,13 @@
1/* linux/arch/arm/plat-samsung/include/plat/fiq.h
2 *
3 * Copyright (c) 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU FIQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 9a4e53d5296..a181d7ce81c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -1,11 +1,11 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h 1/* linux/arch/arm/plat-samsung/include/plat/gpio-cfg-helper.h
2 * 2 *
3 * Copyright 2008 Openmoko, Inc. 3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/ 5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk> 6 * Ben Dooks <ben@simtec.co.uk>
7 * 7 *
8 * S3C Platform - GPIO pin configuration helper definitions 8 * Samsung Platform - GPIO pin configuration helper definitions
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
@@ -24,120 +24,30 @@
24 * by disabling interrupts. 24 * by disabling interrupts.
25*/ 25*/
26 26
27static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, 27static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip,
28 unsigned int off, unsigned int config) 28 unsigned int off, unsigned int config)
29{ 29{
30 return (chip->config->set_config)(chip, off, config); 30 return (chip->config->set_config)(chip, off, config);
31} 31}
32 32
33static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip, 33static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip,
34 unsigned int off) 34 unsigned int off)
35{ 35{
36 return (chip->config->get_config)(chip, off); 36 return (chip->config->get_config)(chip, off);
37} 37}
38 38
39static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, 39static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip,
40 unsigned int off, s3c_gpio_pull_t pull) 40 unsigned int off, samsung_gpio_pull_t pull)
41{ 41{
42 return (chip->config->set_pull)(chip, off, pull); 42 return (chip->config->set_pull)(chip, off, pull);
43} 43}
44 44
45static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip, 45static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip,
46 unsigned int off) 46 unsigned int off)
47{ 47{
48 return chip->config->get_pull(chip, off); 48 return chip->config->get_pull(chip, off);
49} 49}
50 50
51/**
52 * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
53 * @chip: The gpio chip that is being configured.
54 * @off: The offset for the GPIO being configured.
55 * @cfg: The configuration value to set.
56 *
57 * This helper deal with the GPIO cases where the control register
58 * has two bits of configuration per gpio, which have the following
59 * functions:
60 * 00 = input
61 * 01 = output
62 * 1x = special function
63*/
64extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
65 unsigned int off, unsigned int cfg);
66
67/**
68 * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read.
69 * @chip: The gpio chip that is being configured.
70 * @off: The offset for the GPIO being configured.
71 *
72 * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg
73 * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the
74 * S3C_GPIO_SPECIAL() macro.
75 */
76unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
77 unsigned int off);
78
79/**
80 * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
81 * @chip: The gpio chip that is being configured.
82 * @off: The offset for the GPIO being configured.
83 * @cfg: The configuration value to set.
84 *
85 * This helper deal with the GPIO cases where the control register
86 * has one bit of configuration for the gpio, where setting the bit
87 * means the pin is in special function mode and unset means output.
88*/
89extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
90 unsigned int off, unsigned int cfg);
91
92
93/**
94 * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A)
95 * @chip: The gpio chip that is being configured.
96 * @off: The offset for the GPIO being configured.
97 *
98 * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable
99 * GPIO configuration value.
100 *
101 * @sa s3c_gpio_getcfg_s3c24xx
102 * @sa s3c_gpio_getcfg_s3c64xx_4bit
103 */
104extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
105 unsigned int off);
106
107/**
108 * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
109 * @chip: The gpio chip that is being configured.
110 * @off: The offset for the GPIO being configured.
111 * @cfg: The configuration value to set.
112 *
113 * This helper deal with the GPIO cases where the control register has 4 bits
114 * of control per GPIO, generally in the form of:
115 * 0000 = Input
116 * 0001 = Output
117 * others = Special functions (dependent on bank)
118 *
119 * Note, since the code to deal with the case where there are two control
120 * registers instead of one, we do not have a separate set of functions for
121 * each case.
122*/
123extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
124 unsigned int off, unsigned int cfg);
125
126
127/**
128 * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read.
129 * @chip: The gpio chip that is being configured.
130 * @off: The offset for the GPIO being configured.
131 *
132 * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration
133 * register setting into a value the software can use, such as could be passed
134 * to s3c_gpio_setcfg_s3c64xx_4bit().
135 *
136 * @sa s3c_gpio_getcfg_s3c24xx
137 */
138extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
139 unsigned int off);
140
141/* Pull-{up,down} resistor controls. 51/* Pull-{up,down} resistor controls.
142 * 52 *
143 * S3C2410,S3C2440 = Pull-UP, 53 * S3C2410,S3C2440 = Pull-UP,
@@ -147,7 +57,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
147 */ 57 */
148 58
149/** 59/**
150 * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. 60 * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none.
151 * @chip: The gpio chip that is being configured. 61 * @chip: The gpio chip that is being configured.
152 * @off: The offset for the GPIO being configured. 62 * @off: The offset for the GPIO being configured.
153 * @param: pull: The pull mode being requested. 63 * @param: pull: The pull mode being requested.
@@ -155,11 +65,11 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
155 * This is a helper function for the case where we have GPIOs with one 65 * This is a helper function for the case where we have GPIOs with one
156 * bit configuring the presence of a pull-up resistor. 66 * bit configuring the presence of a pull-up resistor.
157 */ 67 */
158extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, 68extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
159 unsigned int off, s3c_gpio_pull_t pull); 69 unsigned int off, samsung_gpio_pull_t pull);
160 70
161/** 71/**
162 * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none 72 * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none
163 * @chip: The gpio chip that is being configured 73 * @chip: The gpio chip that is being configured
164 * @off: The offset for the GPIO being configured 74 * @off: The offset for the GPIO being configured
165 * @param: pull: The pull mode being requested 75 * @param: pull: The pull mode being requested
@@ -167,11 +77,13 @@ extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
167 * This is a helper function for the case where we have GPIOs with one 77 * This is a helper function for the case where we have GPIOs with one
168 * bit configuring the presence of a pull-down resistor. 78 * bit configuring the presence of a pull-down resistor.
169 */ 79 */
170extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, 80extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
171 unsigned int off, s3c_gpio_pull_t pull); 81 unsigned int off, samsung_gpio_pull_t pull);
172 82
173/** 83/**
174 * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none 84 * samsung_gpio_setpull_upown() - Pull configuration for choice of up,
85 * down or none
86 *
175 * @chip: The gpio chip that is being configured. 87 * @chip: The gpio chip that is being configured.
176 * @off: The offset for the GPIO being configured. 88 * @off: The offset for the GPIO being configured.
177 * @param: pull: The pull mode being requested. 89 * @param: pull: The pull mode being requested.
@@ -183,45 +95,46 @@ extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
183 * 01 = Pull-up resistor connected 95 * 01 = Pull-up resistor connected
184 * 10 = Pull-down resistor connected 96 * 10 = Pull-down resistor connected
185 */ 97 */
186extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, 98extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
187 unsigned int off, s3c_gpio_pull_t pull); 99 unsigned int off, samsung_gpio_pull_t pull);
188
189 100
190/** 101/**
191 * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none 102 * samsung_gpio_getpull_updown() - Get configuration for choice of up,
103 * down or none
104 *
192 * @chip: The gpio chip that the GPIO pin belongs to 105 * @chip: The gpio chip that the GPIO pin belongs to
193 * @off: The offset to the pin to get the configuration of. 106 * @off: The offset to the pin to get the configuration of.
194 * 107 *
195 * This helper function reads the state of the pull-{up,down} resistor for the 108 * This helper function reads the state of the pull-{up,down} resistor
196 * given GPIO in the same case as s3c_gpio_setpull_upown. 109 * for the given GPIO in the same case as samsung_gpio_setpull_upown.
197*/ 110*/
198extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, 111extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
199 unsigned int off); 112 unsigned int off);
200 113
201/** 114/**
202 * s3c_gpio_getpull_1up() - Get configuration for choice of up or none 115 * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none
203 * @chip: The gpio chip that the GPIO pin belongs to 116 * @chip: The gpio chip that the GPIO pin belongs to
204 * @off: The offset to the pin to get the configuration of. 117 * @off: The offset to the pin to get the configuration of.
205 * 118 *
206 * This helper function reads the state of the pull-up resistor for the 119 * This helper function reads the state of the pull-up resistor for the
207 * given GPIO in the same case as s3c_gpio_setpull_1up. 120 * given GPIO in the same case as s3c24xx_gpio_setpull_1up.
208*/ 121*/
209extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, 122extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
210 unsigned int off); 123 unsigned int off);
211 124
212/** 125/**
213 * s3c_gpio_getpull_1down() - Get configuration for choice of down or none 126 * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none
214 * @chip: The gpio chip that the GPIO pin belongs to 127 * @chip: The gpio chip that the GPIO pin belongs to
215 * @off: The offset to the pin to get the configuration of. 128 * @off: The offset to the pin to get the configuration of.
216 * 129 *
217 * This helper function reads the state of the pull-down resistor for the 130 * This helper function reads the state of the pull-down resistor for the
218 * given GPIO in the same case as s3c_gpio_setpull_1down. 131 * given GPIO in the same case as s3c24xx_gpio_setpull_1down.
219*/ 132*/
220extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, 133extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
221 unsigned int off); 134 unsigned int off);
222 135
223/** 136/**
224 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. 137 * s3c2443_gpio_setpull() - Pull configuration for s3c2443.
225 * @chip: The gpio chip that is being configured. 138 * @chip: The gpio chip that is being configured.
226 * @off: The offset for the GPIO being configured. 139 * @off: The offset for the GPIO being configured.
227 * @param: pull: The pull mode being requested. 140 * @param: pull: The pull mode being requested.
@@ -233,19 +146,18 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
233 * 10 = Pull-down resistor connected 146 * 10 = Pull-down resistor connected
234 * x1 = No pull up resistor 147 * x1 = No pull up resistor
235 */ 148 */
236extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, 149extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
237 unsigned int off, s3c_gpio_pull_t pull); 150 unsigned int off, samsung_gpio_pull_t pull);
238 151
239/** 152/**
240 * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors 153 * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors
241 * @chip: The gpio chip that the GPIO pin belongs to. 154 * @chip: The gpio chip that the GPIO pin belongs to.
242 * @off: The offset to the pin to get the configuration of. 155 * @off: The offset to the pin to get the configuration of.
243 * 156 *
244 * This helper function reads the state of the pull-{up,down} resistor for the 157 * This helper function reads the state of the pull-{up,down} resistor for the
245 * given GPIO in the same case as s3c_gpio_setpull_upown. 158 * given GPIO in the same case as samsung_gpio_setpull_upown.
246*/ 159*/
247extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, 160extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
248 unsigned int off); 161 unsigned int off);
249 162
250#endif /* __PLAT_GPIO_CFG_HELPERS_H */ 163#endif /* __PLAT_GPIO_CFG_HELPERS_H */
251
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 1762dcb4cb9..d48245bb02b 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -24,14 +24,14 @@
24#ifndef __PLAT_GPIO_CFG_H 24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__ 25#define __PLAT_GPIO_CFG_H __FILE__
26 26
27typedef unsigned int __bitwise__ s3c_gpio_pull_t; 27typedef unsigned int __bitwise__ samsung_gpio_pull_t;
28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; 28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
29 29
30/* forward declaration if gpio-core.h hasn't been included */ 30/* forward declaration if gpio-core.h hasn't been included */
31struct s3c_gpio_chip; 31struct samsung_gpio_chip;
32 32
33/** 33/**
34 * struct s3c_gpio_cfg GPIO configuration 34 * struct samsung_gpio_cfg GPIO configuration
35 * @cfg_eint: Configuration setting when used for external interrupt source 35 * @cfg_eint: Configuration setting when used for external interrupt source
36 * @get_pull: Read the current pull configuration for the GPIO 36 * @get_pull: Read the current pull configuration for the GPIO
37 * @set_pull: Set the current pull configuraiton for the GPIO 37 * @set_pull: Set the current pull configuraiton for the GPIO
@@ -44,20 +44,20 @@ struct s3c_gpio_chip;
44 * per-bank configuration information that other systems such as the 44 * per-bank configuration information that other systems such as the
45 * external interrupt code will need. 45 * external interrupt code will need.
46 * 46 *
47 * @sa s3c_gpio_cfgpin 47 * @sa samsung_gpio_cfgpin
48 * @sa s3c_gpio_getcfg 48 * @sa s3c_gpio_getcfg
49 * @sa s3c_gpio_setpull 49 * @sa s3c_gpio_setpull
50 * @sa s3c_gpio_getpull 50 * @sa s3c_gpio_getpull
51 */ 51 */
52struct s3c_gpio_cfg { 52struct samsung_gpio_cfg {
53 unsigned int cfg_eint; 53 unsigned int cfg_eint;
54 54
55 s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); 55 samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs);
56 int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, 56 int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs,
57 s3c_gpio_pull_t pull); 57 samsung_gpio_pull_t pull);
58 58
59 unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); 59 unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs);
60 int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, 60 int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs,
61 unsigned config); 61 unsigned config);
62}; 62};
63 63
@@ -69,7 +69,7 @@ struct s3c_gpio_cfg {
69#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) 69#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
70#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) 70#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
71 71
72#define s3c_gpio_is_cfg_special(_cfg) \ 72#define samsung_gpio_is_cfg_special(_cfg) \
73 (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) 73 (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
74 74
75/** 75/**
@@ -128,9 +128,9 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
128 * up or down settings, and it may be dependent on the chip that is being 128 * up or down settings, and it may be dependent on the chip that is being
129 * used to whether the particular mode is available. 129 * used to whether the particular mode is available.
130 */ 130 */
131#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) 131#define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00)
132#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) 132#define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01)
133#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) 133#define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02)
134 134
135/** 135/**
136 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor 136 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
@@ -143,7 +143,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
143 * 143 *
144 * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. 144 * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP.
145*/ 145*/
146extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); 146extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull);
147 147
148/** 148/**
149 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin 149 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
@@ -151,7 +151,7 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
151 * 151 *
152 * Read the pull resistor value for the specified pin. 152 * Read the pull resistor value for the specified pin.
153*/ 153*/
154extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); 154extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
155 155
156/* configure `all` aspects of an gpio */ 156/* configure `all` aspects of an gpio */
157 157
@@ -170,7 +170,7 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
170 * @sa s3c_gpio_cfgpin_range 170 * @sa s3c_gpio_cfgpin_range
171 */ 171 */
172extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, 172extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
173 unsigned int cfg, s3c_gpio_pull_t pull); 173 unsigned int cfg, samsung_gpio_pull_t pull);
174 174
175static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, 175static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
176 unsigned int cfg) 176 unsigned int cfg)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 8cad4cf19c3..1fe6917f6a2 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -25,22 +25,22 @@
25 * specific code. 25 * specific code.
26*/ 26*/
27 27
28struct s3c_gpio_chip; 28struct samsung_gpio_chip;
29 29
30/** 30/**
31 * struct s3c_gpio_pm - power management (suspend/resume) information 31 * struct samsung_gpio_pm - power management (suspend/resume) information
32 * @save: Routine to save the state of the GPIO block 32 * @save: Routine to save the state of the GPIO block
33 * @resume: Routine to resume the GPIO block. 33 * @resume: Routine to resume the GPIO block.
34 */ 34 */
35struct s3c_gpio_pm { 35struct samsung_gpio_pm {
36 void (*save)(struct s3c_gpio_chip *chip); 36 void (*save)(struct samsung_gpio_chip *chip);
37 void (*resume)(struct s3c_gpio_chip *chip); 37 void (*resume)(struct samsung_gpio_chip *chip);
38}; 38};
39 39
40struct s3c_gpio_cfg; 40struct samsung_gpio_cfg;
41 41
42/** 42/**
43 * struct s3c_gpio_chip - wrapper for specific implementation of gpio 43 * struct samsung_gpio_chip - wrapper for specific implementation of gpio
44 * @chip: The chip structure to be exported via gpiolib. 44 * @chip: The chip structure to be exported via gpiolib.
45 * @base: The base pointer to the gpio configuration registers. 45 * @base: The base pointer to the gpio configuration registers.
46 * @group: The group register number for gpio interrupt support. 46 * @group: The group register number for gpio interrupt support.
@@ -60,10 +60,10 @@ struct s3c_gpio_cfg;
60 * CPU cores trying to get one lock for different GPIO banks, where each 60 * CPU cores trying to get one lock for different GPIO banks, where each
61 * bank of GPIO has its own register space and configuration registers. 61 * bank of GPIO has its own register space and configuration registers.
62 */ 62 */
63struct s3c_gpio_chip { 63struct samsung_gpio_chip {
64 struct gpio_chip chip; 64 struct gpio_chip chip;
65 struct s3c_gpio_cfg *config; 65 struct samsung_gpio_cfg *config;
66 struct s3c_gpio_pm *pm; 66 struct samsung_gpio_pm *pm;
67 void __iomem *base; 67 void __iomem *base;
68 int irq_base; 68 int irq_base;
69 int group; 69 int group;
@@ -73,58 +73,11 @@ struct s3c_gpio_chip {
73#endif 73#endif
74}; 74};
75 75
76static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) 76static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc)
77{ 77{
78 return container_of(gpc, struct s3c_gpio_chip, chip); 78 return container_of(gpc, struct samsung_gpio_chip, chip);
79} 79}
80 80
81/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
82 * @chip: The chip to register
83 *
84 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
85 * information and makes the necessary alterations for the platform and
86 * notes the information for use with the configuration systems and any
87 * other parts of the system.
88 */
89extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
90
91/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
92 * for use with the configuration calls, and other parts of the s3c gpiolib
93 * support code.
94 *
95 * Not all s3c support code will need this, as some configurations of cpu
96 * may only support one or two different configuration options and have an
97 * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
98 * the machine support file should provide its own s3c_gpiolib_getchip()
99 * and any other necessary functions.
100 */
101
102/**
103 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
104 * @chip: The gpio chip that is being configured.
105 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
106 *
107 * This helper deal with the GPIO cases where the control register has 4 bits
108 * of control per GPIO, generally in the form of:
109 * 0000 = Input
110 * 0001 = Output
111 * others = Special functions (dependent on bank)
112 *
113 * Note, since the code to deal with the case where there are two control
114 * registers instead of one, we do not have a separate set of function
115 * (samsung_gpiolib_add_4bit2_chips)for each case.
116 */
117extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
118 int nr_chips);
119extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
120 int nr_chips);
121extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
122 int nr_chips);
123
124extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
125extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
126
127
128/** 81/**
129 * samsung_gpiolib_to_irq - convert gpio pin to irq number 82 * samsung_gpiolib_to_irq - convert gpio pin to irq number
130 * @chip: The gpio chip that the pin belongs to. 83 * @chip: The gpio chip that the pin belongs to.
@@ -136,36 +89,36 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
136extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); 89extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
137 90
138/* exported for core SoC support to change */ 91/* exported for core SoC support to change */
139extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; 92extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default;
140 93
141#ifdef CONFIG_S3C_GPIO_TRACK 94#ifdef CONFIG_S3C_GPIO_TRACK
142extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; 95extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
143 96
144static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) 97static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip)
145{ 98{
146 return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; 99 return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
147} 100}
148#else 101#else
149/* machine specific code should provide s3c_gpiolib_getchip */ 102/* machine specific code should provide samsung_gpiolib_getchip */
150 103
151#include <mach/gpio-track.h> 104#include <mach/gpio-track.h>
152 105
153static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } 106static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { }
154#endif 107#endif
155 108
156#ifdef CONFIG_PM 109#ifdef CONFIG_PM
157extern struct s3c_gpio_pm s3c_gpio_pm_1bit; 110extern struct samsung_gpio_pm samsung_gpio_pm_1bit;
158extern struct s3c_gpio_pm s3c_gpio_pm_2bit; 111extern struct samsung_gpio_pm samsung_gpio_pm_2bit;
159extern struct s3c_gpio_pm s3c_gpio_pm_4bit; 112extern struct samsung_gpio_pm samsung_gpio_pm_4bit;
160#define __gpio_pm(x) x 113#define __gpio_pm(x) x
161#else 114#else
162#define s3c_gpio_pm_1bit NULL 115#define samsung_gpio_pm_1bit NULL
163#define s3c_gpio_pm_2bit NULL 116#define samsung_gpio_pm_2bit NULL
164#define s3c_gpio_pm_4bit NULL 117#define samsung_gpio_pm_4bit NULL
165#define __gpio_pm(x) NULL 118#define __gpio_pm(x) NULL
166 119
167#endif /* CONFIG_PM */ 120#endif /* CONFIG_PM */
168 121
169/* locking wrappers to deal with multiple access to the same gpio bank */ 122/* locking wrappers to deal with multiple access to the same gpio bank */
170#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) 123#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
171#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) 124#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
new file mode 100644
index 00000000000..bab13920176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -0,0 +1,98 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
2 *
3 * Copyright (c) 2003-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __MACH_GPIO_FNS_H
14#define __MACH_GPIO_FNS_H __FILE__
15
16/* These functions are in the to-be-removed category and it is strongly
17 * encouraged not to use these in new code. They will be marked deprecated
18 * very soon.
19 *
20 * Most of the functionality can be either replaced by the gpiocfg calls
21 * for the s3c platform or by the generic GPIOlib API.
22 *
23 * As of 2.6.35-rc, these will be removed, with the few drivers using them
24 * either replaced or given a wrapper until the calls can be removed.
25*/
26
27#include <plat/gpio-cfg.h>
28
29static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
30{
31 /* 1:1 mapping between cfgpin and setcfg calls at the moment */
32 s3c_gpio_cfgpin(pin, cfg);
33}
34
35/* external functions for GPIO support
36 *
37 * These allow various different clients to access the same GPIO
38 * registers without conflicting. If your driver only owns the entire
39 * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
40*/
41
42extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
43
44/* s3c2410_gpio_getirq
45 *
46 * turn the given pin number into the corresponding IRQ number
47 *
48 * returns:
49 * < 0 = no interrupt for this pin
50 * >=0 = interrupt number for the pin
51*/
52
53extern int s3c2410_gpio_getirq(unsigned int pin);
54
55/* s3c2410_gpio_irqfilter
56 *
57 * set the irq filtering on the given pin
58 *
59 * on = 0 => disable filtering
60 * 1 => enable filtering
61 *
62 * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
63 * width of filter (0 through 63)
64 *
65 *
66*/
67
68extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
69 unsigned int config);
70
71/* s3c2410_gpio_pullup
72 *
73 * This call should be replaced with s3c_gpio_setpull().
74 *
75 * As a note, there is currently no distinction between pull-up and pull-down
76 * in the s3c24xx series devices with only an on/off configuration.
77 */
78
79/* s3c2410_gpio_pullup
80 *
81 * configure the pull-up control on the given pin
82 *
83 * to = 1 => disable the pull-up
84 * 0 => enable the pull-up
85 *
86 * eg;
87 *
88 * s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
89 * s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
90*/
91
92extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
93
94extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
95
96extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
97
98#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 56b0059439e..51d52e767a1 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -60,6 +60,7 @@ extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
60extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c); 60extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
61extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c); 61extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
62extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c); 62extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
63extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
63 64
64/* defined by architecture to configure gpio */ 65/* defined by architecture to configure gpio */
65extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); 66extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
new file mode 100644
index 00000000000..e21a89bc26c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq.h
@@ -0,0 +1,116 @@
1/* linux/arch/arm/plat-samsung/include/plat/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14
15#include <mach/hardware.h>
16#include <mach/regs-irq.h>
17#include <mach/regs-gpio.h>
18
19#define irqdbf(x...)
20#define irqdbf2(x...)
21
22#define EXTINT_OFF (IRQ_EINT4 - 4)
23
24/* these are exported for arch/arm/mach-* usage */
25extern struct irq_chip s3c_irq_level_chip;
26extern struct irq_chip s3c_irq_chip;
27
28static inline void s3c_irqsub_mask(unsigned int irqno,
29 unsigned int parentbit,
30 int subcheck)
31{
32 unsigned long mask;
33 unsigned long submask;
34
35 submask = __raw_readl(S3C2410_INTSUBMSK);
36 mask = __raw_readl(S3C2410_INTMSK);
37
38 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
39
40 /* check to see if we need to mask the parent IRQ */
41
42 if ((submask & subcheck) == subcheck)
43 __raw_writel(mask | parentbit, S3C2410_INTMSK);
44
45 /* write back masks */
46 __raw_writel(submask, S3C2410_INTSUBMSK);
47
48}
49
50static inline void s3c_irqsub_unmask(unsigned int irqno,
51 unsigned int parentbit)
52{
53 unsigned long mask;
54 unsigned long submask;
55
56 submask = __raw_readl(S3C2410_INTSUBMSK);
57 mask = __raw_readl(S3C2410_INTMSK);
58
59 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
60 mask &= ~parentbit;
61
62 /* write back masks */
63 __raw_writel(submask, S3C2410_INTSUBMSK);
64 __raw_writel(mask, S3C2410_INTMSK);
65}
66
67
68static inline void s3c_irqsub_maskack(unsigned int irqno,
69 unsigned int parentmask,
70 unsigned int group)
71{
72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
73
74 s3c_irqsub_mask(irqno, parentmask, group);
75
76 __raw_writel(bit, S3C2410_SUBSRCPND);
77
78 /* only ack parent if we've got all the irqs (seems we must
79 * ack, all and hope that the irq system retriggers ok when
80 * the interrupt goes off again)
81 */
82
83 if (1) {
84 __raw_writel(parentmask, S3C2410_SRCPND);
85 __raw_writel(parentmask, S3C2410_INTPND);
86 }
87}
88
89static inline void s3c_irqsub_ack(unsigned int irqno,
90 unsigned int parentmask,
91 unsigned int group)
92{
93 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
94
95 __raw_writel(bit, S3C2410_SUBSRCPND);
96
97 /* only ack parent if we've got all the irqs (seems we must
98 * ack, all and hope that the irq system retriggers ok when
99 * the interrupt goes off again)
100 */
101
102 if (1) {
103 __raw_writel(parentmask, S3C2410_SRCPND);
104 __raw_writel(parentmask, S3C2410_INTPND);
105 }
106}
107
108/* exported for use in arch/arm/mach-s3c2410 */
109
110#ifdef CONFIG_PM
111extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
112#else
113#define s3c_irq_wake NULL
114#endif
115
116extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
new file mode 100644
index 00000000000..08d1a7ef97b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -0,0 +1,80 @@
1/* linux/arch/arm/plat-samsung/include/plat/irqs.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P Common IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_IRQS_H
14#define __PLAT_SAMSUNG_IRQS_H __FILE__
15
16/* we keep the first set of CPU IRQs out of the range of
17 * the ISA space, so that the PC104 has them to itself
18 * and we don't end up having to do horrible things to the
19 * standard ISA drivers....
20 *
21 * note, since we're using the VICs, our start must be a
22 * mulitple of 32 to allow the common code to work
23 */
24
25#define S5P_IRQ_OFFSET (32)
26
27#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
28
29#define S5P_VIC0_BASE S5P_IRQ(0)
30#define S5P_VIC1_BASE S5P_IRQ(32)
31#define S5P_VIC2_BASE S5P_IRQ(64)
32#define S5P_VIC3_BASE S5P_IRQ(96)
33
34#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
35
36#define IRQ_VIC0_BASE S5P_VIC0_BASE
37#define IRQ_VIC1_BASE S5P_VIC1_BASE
38#define IRQ_VIC2_BASE S5P_VIC2_BASE
39
40/* VIC based IRQs */
41
42#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
43#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
46
47#define S5P_TIMER_IRQ(x) (11 + (x))
48
49#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
50#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
51#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
52#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
53#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
54
55#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
56 : ((x) - 16 + S5P_EINT_BASE2))
57
58#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
59 ((irq) - S5P_EINT_BASE1) : \
60 ((irq) + 16 - S5P_EINT_BASE2))
61
62#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
63
64/* Typically only a few gpio chips require gpio interrupt support.
65 To avoid memory waste irq descriptors are allocated only for
66 S5P_GPIOINT_GROUP_COUNT chips, each with total number of
67 S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
68 to any gpio chip with the s5p_register_gpio_interrupt() function */
69#define S5P_GPIOINT_GROUP_COUNT 4
70#define S5P_GPIOINT_GROUP_SIZE 8
71#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
72
73/* IRQ types common for all s5p platforms */
74#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
75#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
76#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
77#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
78#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
79
80#endif /* __PLAT_SAMSUNG_IRQS_H */
diff --git a/arch/arm/plat-samsung/include/plat/mci.h b/arch/arm/plat-samsung/include/plat/mci.h
new file mode 100644
index 00000000000..c42d3171194
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mci.h
@@ -0,0 +1,52 @@
1#ifndef _ARCH_MCI_H
2#define _ARCH_MCI_H
3
4/**
5 * struct s3c24xx_mci_pdata - sd/mmc controller platform data
6 * @no_wprotect: Set this to indicate there is no write-protect switch.
7 * @no_detect: Set this if there is no detect switch.
8 * @wprotect_invert: Invert the default sense of the write protect switch.
9 * @detect_invert: Invert the default sense of the write protect switch.
10 * @use_dma: Set to allow the use of DMA.
11 * @gpio_detect: GPIO number for the card detect line.
12 * @gpio_wprotect: GPIO number for the write protect line.
13 * @ocr_avail: The mask of the available power states, non-zero to use.
14 * @set_power: Callback to control the power mode.
15 *
16 * The @gpio_detect is used for card detection when @no_wprotect is unset,
17 * and the default sense is that 0 returned from gpio_get_value() means
18 * that a card is inserted. If @detect_invert is set, then the value from
19 * gpio_get_value() is inverted, which makes 1 mean card inserted.
20 *
21 * The driver will use @gpio_wprotect to signal whether the card is write
22 * protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
23 * means the card is read/write, and 1 means read-only. The @wprotect_invert
24 * will invert the value returned from gpio_get_value().
25 *
26 * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
27 * to a non-zero value, otherwise the default of 3.2-3.4V is used.
28 */
29struct s3c24xx_mci_pdata {
30 unsigned int no_wprotect:1;
31 unsigned int no_detect:1;
32 unsigned int wprotect_invert:1;
33 unsigned int detect_invert:1; /* set => detect active high */
34 unsigned int use_dma:1;
35
36 unsigned int gpio_detect;
37 unsigned int gpio_wprotect;
38 unsigned long ocr_avail;
39 void (*set_power)(unsigned char power_mode,
40 unsigned short vdd);
41};
42
43/**
44 * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device
45 * @pdata: The platform data
46 *
47 * Copy the platform data supplied by @pdata so that this can be marked
48 * __initdata.
49 */
50extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata);
51
52#endif /* _ARCH_NCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
new file mode 100644
index 00000000000..ac13227272f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __PLAT_SAMSUNG_MFC_H
11#define __PLAT_SAMSUNG_MFC_H __FILE__
12
13/**
14 * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
15 * @rbase: base address for MFC 'right' memory interface
16 * @rsize: size of the memory reserved for MFC 'right' interface
17 * @lbase: base address for MFC 'left' memory interface
18 * @lsize: size of the memory reserved for MFC 'left' interface
19 *
20 * This function reserves system memory for both MFC device memory
21 * interfaces and registers it to respective struct device entries as
22 * coherent memory.
23 */
24void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
25 phys_addr_t lbase, unsigned int lsize);
26
27#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-samsung/include/plat/mipi_csis.h b/arch/arm/plat-samsung/include/plat/mipi_csis.h
new file mode 100644
index 00000000000..c45b1e8d4c2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mipi_csis.h
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
3 *
4 * S5P series MIPI CSI slave device support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_
12#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__
13
14struct platform_device;
15
16/**
17 * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
18 * @clk_rate: bus clock frequency
19 * @lanes: number of data lanes used
20 * @alignment: data alignment in bits
21 * @hs_settle: HS-RX settle time
22 * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
23 * driver or true in case this regulator has no enable function
24 * @phy_enable: pointer to a callback controlling D-PHY enable/reset
25 */
26struct s5p_platform_mipi_csis {
27 unsigned long clk_rate;
28 u8 lanes;
29 u8 alignment;
30 u8 hs_settle;
31 bool fixed_phy_vdd;
32 int (*phy_enable)(struct platform_device *pdev, bool on);
33};
34
35/**
36 * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
37 * @pdev: MIPI-CSIS platform device
38 * @on: true to enable D-PHY and deassert its reset
39 * false to disable D-PHY
40 */
41int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
42
43#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
new file mode 100644
index 00000000000..357af7c1c66
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll.h
@@ -0,0 +1,323 @@
1/* linux/arch/arm/plat-samsung/include/plat/pll.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Samsung PLL codes
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#include <asm/div64.h>
19
20#define S3C24XX_PLL_MDIV_MASK (0xFF)
21#define S3C24XX_PLL_PDIV_MASK (0x1F)
22#define S3C24XX_PLL_SDIV_MASK (0x3)
23#define S3C24XX_PLL_MDIV_SHIFT (12)
24#define S3C24XX_PLL_PDIV_SHIFT (4)
25#define S3C24XX_PLL_SDIV_SHIFT (0)
26
27static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
28 unsigned int baseclk)
29{
30 unsigned int mdiv, pdiv, sdiv;
31 uint64_t fvco;
32
33 mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
34 pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
35 sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
36
37 fvco = (uint64_t)baseclk * (mdiv + 8);
38 do_div(fvco, (pdiv + 2) << sdiv);
39
40 return (unsigned int)fvco;
41}
42
43#define S3C2416_PLL_MDIV_MASK (0x3FF)
44#define S3C2416_PLL_PDIV_MASK (0x3F)
45#define S3C2416_PLL_SDIV_MASK (0x7)
46#define S3C2416_PLL_MDIV_SHIFT (14)
47#define S3C2416_PLL_PDIV_SHIFT (5)
48#define S3C2416_PLL_SDIV_SHIFT (0)
49
50static inline unsigned int s3c2416_get_pll(unsigned int pllval,
51 unsigned int baseclk)
52{
53 unsigned int mdiv, pdiv, sdiv;
54 uint64_t fvco;
55
56 mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
57 pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
58 sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
59
60 fvco = (uint64_t)baseclk * mdiv;
61 do_div(fvco, (pdiv << sdiv));
62
63 return (unsigned int)fvco;
64}
65
66#define S3C6400_PLL_MDIV_MASK (0x3FF)
67#define S3C6400_PLL_PDIV_MASK (0x3F)
68#define S3C6400_PLL_SDIV_MASK (0x7)
69#define S3C6400_PLL_MDIV_SHIFT (16)
70#define S3C6400_PLL_PDIV_SHIFT (8)
71#define S3C6400_PLL_SDIV_SHIFT (0)
72
73static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
74 u32 pllcon)
75{
76 u32 mdiv, pdiv, sdiv;
77 u64 fvco = baseclk;
78
79 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
80 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
81 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
82
83 fvco *= mdiv;
84 do_div(fvco, (pdiv << sdiv));
85
86 return (unsigned long)fvco;
87}
88
89#define PLL6553X_MDIV_MASK (0x7F)
90#define PLL6553X_PDIV_MASK (0x1F)
91#define PLL6553X_SDIV_MASK (0x3)
92#define PLL6553X_KDIV_MASK (0xFFFF)
93#define PLL6553X_MDIV_SHIFT (16)
94#define PLL6553X_PDIV_SHIFT (8)
95#define PLL6553X_SDIV_SHIFT (0)
96
97static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
98 u32 pll_con0, u32 pll_con1)
99{
100 unsigned long result;
101 u32 mdiv, pdiv, sdiv, kdiv;
102 u64 tmp;
103
104 mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
105 pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
106 sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
107 kdiv = pll_con1 & PLL6553X_KDIV_MASK;
108
109 /*
110 * We need to multiple baseclk by mdiv (the integer part) and kdiv
111 * which is in 2^16ths, so shift mdiv up (does not overflow) and
112 * add kdiv before multiplying. The use of tmp is to avoid any
113 * overflows before shifting bac down into result when multipling
114 * by the mdiv and kdiv pair.
115 */
116
117 tmp = baseclk;
118 tmp *= (mdiv << 16) + kdiv;
119 do_div(tmp, (pdiv << sdiv));
120 result = tmp >> 16;
121
122 return result;
123}
124
125#define PLL35XX_MDIV_MASK (0x3FF)
126#define PLL35XX_PDIV_MASK (0x3F)
127#define PLL35XX_SDIV_MASK (0x7)
128#define PLL35XX_MDIV_SHIFT (16)
129#define PLL35XX_PDIV_SHIFT (8)
130#define PLL35XX_SDIV_SHIFT (0)
131
132static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
133{
134 u32 mdiv, pdiv, sdiv;
135 u64 fvco = baseclk;
136
137 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
138 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
139 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
140
141 fvco *= mdiv;
142 do_div(fvco, (pdiv << sdiv));
143
144 return (unsigned long)fvco;
145}
146
147#define PLL36XX_KDIV_MASK (0xFFFF)
148#define PLL36XX_MDIV_MASK (0x1FF)
149#define PLL36XX_PDIV_MASK (0x3F)
150#define PLL36XX_SDIV_MASK (0x7)
151#define PLL36XX_MDIV_SHIFT (16)
152#define PLL36XX_PDIV_SHIFT (8)
153#define PLL36XX_SDIV_SHIFT (0)
154
155static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
156 u32 pll_con0, u32 pll_con1)
157{
158 unsigned long result;
159 u32 mdiv, pdiv, sdiv, kdiv;
160 u64 tmp;
161
162 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
163 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
164 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
165 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
166
167 tmp = baseclk;
168
169 tmp *= (mdiv << 16) + kdiv;
170 do_div(tmp, (pdiv << sdiv));
171 result = tmp >> 16;
172
173 return result;
174}
175
176#define PLL45XX_MDIV_MASK (0x3FF)
177#define PLL45XX_PDIV_MASK (0x3F)
178#define PLL45XX_SDIV_MASK (0x7)
179#define PLL45XX_MDIV_SHIFT (16)
180#define PLL45XX_PDIV_SHIFT (8)
181#define PLL45XX_SDIV_SHIFT (0)
182
183enum pll45xx_type_t {
184 pll_4500,
185 pll_4502,
186 pll_4508
187};
188
189static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
190 enum pll45xx_type_t pll_type)
191{
192 u32 mdiv, pdiv, sdiv;
193 u64 fvco = baseclk;
194
195 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
196 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
197 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
198
199 if (pll_type == pll_4508)
200 sdiv = sdiv - 1;
201
202 fvco *= mdiv;
203 do_div(fvco, (pdiv << sdiv));
204
205 return (unsigned long)fvco;
206}
207
208/* CON0 bit-fields */
209#define PLL46XX_MDIV_MASK (0x1FF)
210#define PLL46XX_PDIV_MASK (0x3F)
211#define PLL46XX_SDIV_MASK (0x7)
212#define PLL46XX_LOCKED_SHIFT (29)
213#define PLL46XX_MDIV_SHIFT (16)
214#define PLL46XX_PDIV_SHIFT (8)
215#define PLL46XX_SDIV_SHIFT (0)
216
217/* CON1 bit-fields */
218#define PLL46XX_MRR_MASK (0x1F)
219#define PLL46XX_MFR_MASK (0x3F)
220#define PLL46XX_KDIV_MASK (0xFFFF)
221#define PLL4650C_KDIV_MASK (0xFFF)
222#define PLL46XX_MRR_SHIFT (24)
223#define PLL46XX_MFR_SHIFT (16)
224#define PLL46XX_KDIV_SHIFT (0)
225
226enum pll46xx_type_t {
227 pll_4600,
228 pll_4650,
229 pll_4650c,
230};
231
232static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
233 u32 pll_con0, u32 pll_con1,
234 enum pll46xx_type_t pll_type)
235{
236 unsigned long result;
237 u32 mdiv, pdiv, sdiv, kdiv;
238 u64 tmp;
239
240 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
241 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
242 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
243 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
244
245 if (pll_type == pll_4650c)
246 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
247 else
248 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
249
250 tmp = baseclk;
251
252 if (pll_type == pll_4600) {
253 tmp *= (mdiv << 16) + kdiv;
254 do_div(tmp, (pdiv << sdiv));
255 result = tmp >> 16;
256 } else {
257 tmp *= (mdiv << 10) + kdiv;
258 do_div(tmp, (pdiv << sdiv));
259 result = tmp >> 10;
260 }
261
262 return result;
263}
264
265#define PLL90XX_MDIV_MASK (0xFF)
266#define PLL90XX_PDIV_MASK (0x3F)
267#define PLL90XX_SDIV_MASK (0x7)
268#define PLL90XX_KDIV_MASK (0xffff)
269#define PLL90XX_LOCKED_SHIFT (29)
270#define PLL90XX_MDIV_SHIFT (16)
271#define PLL90XX_PDIV_SHIFT (8)
272#define PLL90XX_SDIV_SHIFT (0)
273#define PLL90XX_KDIV_SHIFT (0)
274
275static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
276 u32 pll_con, u32 pll_conk)
277{
278 unsigned long result;
279 u32 mdiv, pdiv, sdiv, kdiv;
280 u64 tmp;
281
282 mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
283 pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
284 sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
285 kdiv = pll_conk & PLL90XX_KDIV_MASK;
286
287 /*
288 * We need to multiple baseclk by mdiv (the integer part) and kdiv
289 * which is in 2^16ths, so shift mdiv up (does not overflow) and
290 * add kdiv before multiplying. The use of tmp is to avoid any
291 * overflows before shifting bac down into result when multipling
292 * by the mdiv and kdiv pair.
293 */
294
295 tmp = baseclk;
296 tmp *= (mdiv << 16) + kdiv;
297 do_div(tmp, (pdiv << sdiv));
298 result = tmp >> 16;
299
300 return result;
301}
302
303#define PLL65XX_MDIV_MASK (0x3FF)
304#define PLL65XX_PDIV_MASK (0x3F)
305#define PLL65XX_SDIV_MASK (0x7)
306#define PLL65XX_MDIV_SHIFT (16)
307#define PLL65XX_PDIV_SHIFT (8)
308#define PLL65XX_SDIV_SHIFT (0)
309
310static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
311{
312 u32 mdiv, pdiv, sdiv;
313 u64 fvco = baseclk;
314
315 mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
316 pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
317 sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
318
319 fvco *= mdiv;
320 do_div(fvco, (pdiv << sdiv));
321
322 return (unsigned long)fvco;
323}
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h
deleted file mode 100644
index b8b7e1d884f..00000000000
--- a/arch/arm/plat-samsung/include/plat/pll6553x.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/pll6553x.h
2 * partially from arch/arm/mach-s3c64xx/include/mach/pll.h
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Samsung PLL6553x PLL code
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
17
18#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1)
19#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1)
20#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1)
21#define PLL6553X_MDIV_SHIFT (16)
22#define PLL6553X_PDIV_SHIFT (8)
23#define PLL6553X_SDIV_SHIFT (0)
24#define PLL6553X_KDIV_MASK (0xffff)
25
26static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
27 u32 pll0, u32 pll1)
28{
29 unsigned long result;
30 u32 mdiv, pdiv, sdiv, kdiv;
31 u64 tmp;
32
33 mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
34 pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
35 sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
36 kdiv = pll1 & PLL6553X_KDIV_MASK;
37
38 /* We need to multiple baseclk by mdiv (the integer part) and kdiv
39 * which is in 2^16ths, so shift mdiv up (does not overflow) and
40 * add kdiv before multiplying. The use of tmp is to avoid any
41 * overflows before shifting bac down into result when multipling
42 * by the mdiv and kdiv pair.
43 */
44
45 tmp = baseclk;
46 tmp *= (mdiv << 16) + kdiv;
47 do_div(tmp, (pdiv << sdiv));
48 result = tmp >> 16;
49
50 return result;
51}
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6749916d19..dcf68709f9c 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -165,20 +165,20 @@ extern void s3c_pm_check_store(void);
165extern void s3c_pm_configure_extint(void); 165extern void s3c_pm_configure_extint(void);
166 166
167/** 167/**
168 * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. 168 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
169 * 169 *
170 * Restore the state of the GPIO pins after sleep, which may involve ensuring 170 * Restore the state of the GPIO pins after sleep, which may involve ensuring
171 * that we do not glitch the state of the pins from that the bootloader's 171 * that we do not glitch the state of the pins from that the bootloader's
172 * resume code has done. 172 * resume code has done.
173*/ 173*/
174extern void s3c_pm_restore_gpios(void); 174extern void samsung_pm_restore_gpios(void);
175 175
176/** 176/**
177 * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. 177 * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
178 * 178 *
179 * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). 179 * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
180 */ 180 */
181extern void s3c_pm_save_gpios(void); 181extern void samsung_pm_save_gpios(void);
182 182
183extern void s3c_pm_save_core(void); 183extern void s3c_pm_save_core(void);
184extern void s3c_pm_restore_core(void); 184extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h
new file mode 100644
index 00000000000..bf6a60eb623
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pwm-clock.h
@@ -0,0 +1,81 @@
1/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * SAMSUNG - pwm clock and timer support
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_PLAT_PWM_CLOCK_H
19#define __ASM_PLAT_PWM_CLOCK_H __FILE__
20
21/**
22 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
23 * @tcfg: The timer TCFG1 register bits shifted down to 0.
24 *
25 * Return true if the given configuration from TCFG1 is a TCLK instead
26 * any of the TDIV clocks.
27 */
28static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
29{
30 if (soc_is_s3c24xx())
31 return tcfg == S3C2410_TCFG1_MUX_TCLK;
32 else if (soc_is_s3c64xx() || soc_is_s5pc100())
33 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
34 else if (soc_is_s5p6440() || soc_is_s5p6450())
35 return 0;
36 else
37 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
38}
39
40/**
41 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
42 * @tcfg1: The tcfg1 setting, shifted down.
43 *
44 * Get the divisor value for the given tcfg1 setting. We assume the
45 * caller has already checked to see if this is not a TCLK source.
46 */
47static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
48{
49 if (soc_is_s3c24xx())
50 return 1 << (tcfg1 + 1);
51 else
52 return 1 << tcfg1;
53}
54
55/**
56 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
57 *
58 * Return true if we have a /1 in the tdiv setting.
59 */
60static inline unsigned int pwm_tdiv_has_div1(void)
61{
62 if (soc_is_s3c24xx())
63 return 0;
64 else
65 return 1;
66}
67
68/**
69 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
70 * @div: The divisor to calculate the bit information for.
71 *
72 * Turn a divisor into the necessary bit field for TCFG1.
73 */
74static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
75{
76 if (soc_is_s3c24xx())
77 return ilog2(div) - 1;
78 else
79 return ilog2(div);
80}
81#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 035e8c38d69..70612100120 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -20,6 +20,7 @@
20#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) 20#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) 21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) 22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
23#define S3C2443_ADCMUX S3C2410_ADCREG(0x18)
23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) 24#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
24#define S5P_ADCMUX S3C2410_ADCREG(0x1C) 25#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
25#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) 26#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
@@ -33,6 +34,7 @@
33#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) 34#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
34#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) 35#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
35#define S3C2410_ADCCON_MUXMASK (0x7<<3) 36#define S3C2410_ADCCON_MUXMASK (0x7<<3)
37#define S3C2416_ADCCON_RESSEL (1 << 3)
36#define S3C2410_ADCCON_STDBM (1<<2) 38#define S3C2410_ADCCON_STDBM (1<<2)
37#define S3C2410_ADCCON_READ_START (1<<1) 39#define S3C2410_ADCCON_READ_START (1<<1)
38#define S3C2410_ADCCON_ENABLE_START (1<<0) 40#define S3C2410_ADCCON_ENABLE_START (1<<0)
@@ -40,6 +42,7 @@
40 42
41 43
42/* ADCTSC Register Bits */ 44/* ADCTSC Register Bits */
45#define S3C2443_ADCTSC_UD_SEN (1 << 8)
43#define S3C2410_ADCTSC_YM_SEN (1<<7) 46#define S3C2410_ADCTSC_YM_SEN (1<<7)
44#define S3C2410_ADCTSC_YP_SEN (1<<6) 47#define S3C2410_ADCTSC_YP_SEN (1<<6)
45#define S3C2410_ADCTSC_XM_SEN (1<<5) 48#define S3C2410_ADCTSC_XM_SEN (1<<5)
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
new file mode 100644
index 00000000000..178bccbe480
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -0,0 +1,151 @@
1/* arch/arm/plat-samsung/include/plat/regs-dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_REGS_DMA_H
14#define __ASM_PLAT_REGS_DMA_H __FILE__
15
16#define S3C2410_DMA_DISRC (0x00)
17#define S3C2410_DMA_DISRCC (0x04)
18#define S3C2410_DMA_DIDST (0x08)
19#define S3C2410_DMA_DIDSTC (0x0C)
20#define S3C2410_DMA_DCON (0x10)
21#define S3C2410_DMA_DSTAT (0x14)
22#define S3C2410_DMA_DCSRC (0x18)
23#define S3C2410_DMA_DCDST (0x1C)
24#define S3C2410_DMA_DMASKTRIG (0x20)
25#define S3C2412_DMA_DMAREQSEL (0x24)
26#define S3C2443_DMA_DMAREQSEL (0x24)
27
28#define S3C2410_DISRCC_INC (1 << 0)
29#define S3C2410_DISRCC_APB (1 << 1)
30
31#define S3C2410_DMASKTRIG_STOP (1 << 2)
32#define S3C2410_DMASKTRIG_ON (1 << 1)
33#define S3C2410_DMASKTRIG_SWTRIG (1 << 0)
34
35#define S3C2410_DCON_DEMAND (0 << 31)
36#define S3C2410_DCON_HANDSHAKE (1 << 31)
37#define S3C2410_DCON_SYNC_PCLK (0 << 30)
38#define S3C2410_DCON_SYNC_HCLK (1 << 30)
39
40#define S3C2410_DCON_INTREQ (1 << 29)
41
42#define S3C2410_DCON_CH0_XDREQ0 (0 << 24)
43#define S3C2410_DCON_CH0_UART0 (1 << 24)
44#define S3C2410_DCON_CH0_SDI (2 << 24)
45#define S3C2410_DCON_CH0_TIMER (3 << 24)
46#define S3C2410_DCON_CH0_USBEP1 (4 << 24)
47
48#define S3C2410_DCON_CH1_XDREQ1 (0 << 24)
49#define S3C2410_DCON_CH1_UART1 (1 << 24)
50#define S3C2410_DCON_CH1_I2SSDI (2 << 24)
51#define S3C2410_DCON_CH1_SPI (3 << 24)
52#define S3C2410_DCON_CH1_USBEP2 (4 << 24)
53
54#define S3C2410_DCON_CH2_I2SSDO (0 << 24)
55#define S3C2410_DCON_CH2_I2SSDI (1 << 24)
56#define S3C2410_DCON_CH2_SDI (2 << 24)
57#define S3C2410_DCON_CH2_TIMER (3 << 24)
58#define S3C2410_DCON_CH2_USBEP3 (4 << 24)
59
60#define S3C2410_DCON_CH3_UART2 (0 << 24)
61#define S3C2410_DCON_CH3_SDI (1 << 24)
62#define S3C2410_DCON_CH3_SPI (2 << 24)
63#define S3C2410_DCON_CH3_TIMER (3 << 24)
64#define S3C2410_DCON_CH3_USBEP4 (4 << 24)
65
66#define S3C2410_DCON_SRCSHIFT (24)
67#define S3C2410_DCON_SRCMASK (7 << 24)
68
69#define S3C2410_DCON_BYTE (0 << 20)
70#define S3C2410_DCON_HALFWORD (1 << 20)
71#define S3C2410_DCON_WORD (2 << 20)
72
73#define S3C2410_DCON_AUTORELOAD (0 << 22)
74#define S3C2410_DCON_NORELOAD (1 << 22)
75#define S3C2410_DCON_HWTRIG (1 << 23)
76
77#ifdef CONFIG_CPU_S3C2440
78
79#define S3C2440_DIDSTC_CHKINT (1 << 2)
80
81#define S3C2440_DCON_CH0_I2SSDO (5 << 24)
82#define S3C2440_DCON_CH0_PCMIN (6 << 24)
83
84#define S3C2440_DCON_CH1_PCMOUT (5 << 24)
85#define S3C2440_DCON_CH1_SDI (6 << 24)
86
87#define S3C2440_DCON_CH2_PCMIN (5 << 24)
88#define S3C2440_DCON_CH2_MICIN (6 << 24)
89
90#define S3C2440_DCON_CH3_MICIN (5 << 24)
91#define S3C2440_DCON_CH3_PCMOUT (6 << 24)
92#endif /* CONFIG_CPU_S3C2440 */
93
94#ifdef CONFIG_CPU_S3C2412
95
96#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1)
97
98#define S3C2412_DMAREQSEL_HW (1)
99
100#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
101#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
102#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
103#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
104#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
105#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
106#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
107#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
108#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
109#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
110#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
111#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
112#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
113#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
114#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
115#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
116#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
117#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
118#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
119#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
120#endif /* CONFIG_CPU_S3C2412 */
121
122#ifdef CONFIG_CPU_S3C2443
123
124#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1)
125
126#define S3C2443_DMAREQSEL_HW (1)
127
128#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
129#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
130#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
131#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
132#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
133#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
134#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
135#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
136#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
137#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
138#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
139#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
140#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
141#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
142#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
143#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
144#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
145#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
146#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
147#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
148#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
149#endif /* CONFIG_CPU_S3C2443 */
150
151#endif /* __ASM_PLAT_REGS_DMA_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h
new file mode 100644
index 00000000000..a18d35e7a73
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iis.h
@@ -0,0 +1,70 @@
1/* arch/arm/plat-samsung/include/plat/regs-iis.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_IIS_H
14#define __ASM_ARCH_REGS_IIS_H
15
16#define S3C2410_IISCON (0x00)
17
18#define S3C2410_IISCON_LRINDEX (1 << 8)
19#define S3C2410_IISCON_TXFIFORDY (1 << 7)
20#define S3C2410_IISCON_RXFIFORDY (1 << 6)
21#define S3C2410_IISCON_TXDMAEN (1 << 5)
22#define S3C2410_IISCON_RXDMAEN (1 << 4)
23#define S3C2410_IISCON_TXIDLE (1 << 3)
24#define S3C2410_IISCON_RXIDLE (1 << 2)
25#define S3C2410_IISCON_PSCEN (1 << 1)
26#define S3C2410_IISCON_IISEN (1 << 0)
27
28#define S3C2410_IISMOD (0x04)
29
30#define S3C2440_IISMOD_MPLL (1 << 9)
31#define S3C2410_IISMOD_SLAVE (1 << 8)
32#define S3C2410_IISMOD_NOXFER (0 << 6)
33#define S3C2410_IISMOD_RXMODE (1 << 6)
34#define S3C2410_IISMOD_TXMODE (2 << 6)
35#define S3C2410_IISMOD_TXRXMODE (3 << 6)
36#define S3C2410_IISMOD_LR_LLOW (0 << 5)
37#define S3C2410_IISMOD_LR_RLOW (1 << 5)
38#define S3C2410_IISMOD_IIS (0 << 4)
39#define S3C2410_IISMOD_MSB (1 << 4)
40#define S3C2410_IISMOD_8BIT (0 << 3)
41#define S3C2410_IISMOD_16BIT (1 << 3)
42#define S3C2410_IISMOD_BITMASK (1 << 3)
43#define S3C2410_IISMOD_256FS (0 << 2)
44#define S3C2410_IISMOD_384FS (1 << 2)
45#define S3C2410_IISMOD_16FS (0 << 0)
46#define S3C2410_IISMOD_32FS (1 << 0)
47#define S3C2410_IISMOD_48FS (2 << 0)
48#define S3C2410_IISMOD_FS_MASK (3 << 0)
49
50#define S3C2410_IISPSR (0x08)
51
52#define S3C2410_IISPSR_INTMASK (31 << 5)
53#define S3C2410_IISPSR_INTSHIFT (5)
54#define S3C2410_IISPSR_EXTMASK (31 << 0)
55#define S3C2410_IISPSR_EXTSHFIT (0)
56
57#define S3C2410_IISFCON (0x0c)
58
59#define S3C2410_IISFCON_TXDMA (1 << 15)
60#define S3C2410_IISFCON_RXDMA (1 << 14)
61#define S3C2410_IISFCON_TXENABLE (1 << 13)
62#define S3C2410_IISFCON_RXENABLE (1 << 12)
63#define S3C2410_IISFCON_TXMASK (0x3f << 6)
64#define S3C2410_IISFCON_TXSHIFT (6)
65#define S3C2410_IISFCON_RXMASK (0x3f)
66#define S3C2410_IISFCON_RXSHIFT (0)
67
68#define S3C2410_IISFIFO (0x10)
69
70#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h
new file mode 100644
index 00000000000..552fe7cfe28
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-spi.h
@@ -0,0 +1,48 @@
1/* arch/arm/plat-samsung/include/plat/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
21#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
22#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
23#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
24#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
25#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
26#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
27
28#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
29#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
30
31#define S3C2410_SPSTA (0x04)
32
33#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
34#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
35#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
36#define S3C2412_SPSTA_READY_ORG (1 << 3)
37
38#define S3C2410_SPPIN (0x08)
39
40#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
41#define S3C2410_SPPIN_RESERVED (1 << 1)
42#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
43
44#define S3C2410_SPPRE (0x0C)
45#define S3C2410_SPTDAT (0x10)
46#define S3C2410_SPRDAT (0x14)
47
48#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-srom.h b/arch/arm/plat-samsung/include/plat/regs-srom.h
new file mode 100644
index 00000000000..9b6729c81cd
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-srom.h
@@ -0,0 +1,54 @@
1/* linux/arch/arm/plat-samsung/include/plat/regs-srom.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P SROMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_REGS_SROM_H
14#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
19
20#define S5P_SROM_BW S5P_SROMREG(0x0)
21#define S5P_SROM_BC0 S5P_SROMREG(0x4)
22#define S5P_SROM_BC1 S5P_SROMREG(0x8)
23#define S5P_SROM_BC2 S5P_SROMREG(0xc)
24#define S5P_SROM_BC3 S5P_SROMREG(0x10)
25#define S5P_SROM_BC4 S5P_SROMREG(0x14)
26#define S5P_SROM_BC5 S5P_SROMREG(0x18)
27
28/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
29
30#define S5P_SROM_BW__DATAWIDTH__SHIFT 0
31#define S5P_SROM_BW__ADDRMODE__SHIFT 1
32#define S5P_SROM_BW__WAITENABLE__SHIFT 2
33#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
34
35#define S5P_SROM_BW__CS_MASK 0xf
36
37#define S5P_SROM_BW__NCS0__SHIFT 0
38#define S5P_SROM_BW__NCS1__SHIFT 4
39#define S5P_SROM_BW__NCS2__SHIFT 8
40#define S5P_SROM_BW__NCS3__SHIFT 12
41#define S5P_SROM_BW__NCS4__SHIFT 16
42#define S5P_SROM_BW__NCS5__SHIFT 20
43
44/* applies to same to BCS0 - BCS3 */
45
46#define S5P_SROM_BCX__PMC__SHIFT 0
47#define S5P_SROM_BCX__TACP__SHIFT 4
48#define S5P_SROM_BCX__TCAH__SHIFT 8
49#define S5P_SROM_BCX__TCOH__SHIFT 12
50#define S5P_SROM_BCX__TACC__SHIFT 16
51#define S5P_SROM_BCX__TCOS__SHIFT 24
52#define S5P_SROM_BCX__TACS__SHIFT 28
53
54#endif /* __PLAT_SAMSUNG_REGS_SROM_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h
new file mode 100644
index 00000000000..4003d3dab4e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-udc.h
@@ -0,0 +1,151 @@
1/* arch/arm/plat-samsung/include/plat/regs-udc.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9*/
10
11#ifndef __ASM_ARCH_REGS_UDC_H
12#define __ASM_ARCH_REGS_UDC_H
13
14#define S3C2410_USBDREG(x) (x)
15
16#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
17#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
18#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
19
20#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
21#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
22
23#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
24
25#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
26#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
27
28#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
29#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
30#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
31#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
32#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
33
34#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
35#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
36#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
37#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
38#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
39#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
40
41#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
42#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
43#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
44#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
45#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
46#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
47
48#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
49#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
50#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
51#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
52#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
53#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
54
55#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
56#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
57#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
58#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
59#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
60#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
61
62#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
63
64/* indexed registers */
65
66#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
67
68#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
69
70#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
71#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
72
73#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
74#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77
78#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)
79
80#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */
81#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */
82#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */
83#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */
84#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */
85
86#define S3C2410_UDC_PWR_DEFAULT (0x00)
87
88#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
89#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
90#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
91#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
92#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
93
94#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
95#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
96#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
97
98#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */
99#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */
100#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */
101#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */
102#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */
103
104#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */
105#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */
106
107#define S3C2410_UDC_INDEX_EP0 (0x00)
108#define S3C2410_UDC_INDEX_EP1 (0x01)
109#define S3C2410_UDC_INDEX_EP2 (0x02)
110#define S3C2410_UDC_INDEX_EP3 (0x03)
111#define S3C2410_UDC_INDEX_EP4 (0x04)
112
113#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */
114#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
115#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */
116#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
117#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
118#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
119
120#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */
121#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */
122#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */
123#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */
124
125#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */
126#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
127#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */
128#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */
129#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */
130#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
131#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
132
133#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */
134#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */
135#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */
136
137#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)
138#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)
139#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)
140#define S3C2410_UDC_EP0_CSR_DE (1 << 3)
141#define S3C2410_UDC_EP0_CSR_SE (1 << 4)
142#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)
143#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)
144#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)
145
146#define S3C2410_UDC_MAXP_8 (1 << 0)
147#define S3C2410_UDC_MAXP_16 (1 << 1)
148#define S3C2410_UDC_MAXP_32 (1 << 2)
149#define S3C2410_UDC_MAXP_64 (1 << 3)
150
151#endif
diff --git a/arch/arm/plat-samsung/include/plat/reset.h b/arch/arm/plat-samsung/include/plat/reset.h
new file mode 100644
index 00000000000..32ca5179c6e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/reset.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/plat-samsung/include/plat/reset.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __PLAT_SAMSUNG_RESET_H
12#define __PLAT_SAMSUNG_RESET_H __FILE__
13
14extern void (*s5p_reset_hook)(void);
15
16#endif /* __PLAT_SAMSUNG_RESET_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
deleted file mode 100644
index bf5e2a9d408..00000000000
--- a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __S3C_PL330_PDATA_H
13#define __S3C_PL330_PDATA_H
14
15#include <plat/s3c-dma-pl330.h>
16
17/*
18 * Every PL330 DMAC has max 32 peripheral interfaces,
19 * of which some may be not be really used in your
20 * DMAC's configuration.
21 * Populate this array of 32 peri i/fs with relevant
22 * channel IDs for used peri i/f and DMACH_MAX for
23 * those unused.
24 *
25 * The platforms just need to provide this info
26 * to the S3C DMA API driver for PL330.
27 */
28struct s3c_pl330_platdata {
29 enum dma_ch peri[32];
30};
31
32#endif /* __S3C_PL330_PDATA_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
new file mode 100644
index 00000000000..3986497dd3f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2410.h
@@ -0,0 +1,33 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 machine directory
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#ifdef CONFIG_CPU_S3C2410
15
16extern int s3c2410_init(void);
17extern int s3c2410a_init(void);
18
19extern void s3c2410_map_io(void);
20
21extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22
23extern void s3c2410_init_clocks(int xtal);
24
25#else
26#define s3c2410_init_clocks NULL
27#define s3c2410_init_uarts NULL
28#define s3c2410_map_io NULL
29#define s3c2410_init NULL
30#define s3c2410a_init NULL
31#endif
32
33extern int s3c2410_baseclk_add(void);
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
new file mode 100644
index 00000000000..5bcfd143ba1
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2412.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2412 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2412
14
15extern int s3c2412_init(void);
16
17extern void s3c2412_map_io(void);
18
19extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
20
21extern void s3c2412_init_clocks(int xtal);
22
23extern int s3c2412_baseclk_add(void);
24#else
25#define s3c2412_init_clocks NULL
26#define s3c2412_init_uarts NULL
27#define s3c2412_map_io NULL
28#define s3c2412_init NULL
29#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
new file mode 100644
index 00000000000..a764f8503f5
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
4 *
5 * Header file for s3c2416 cpu support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifdef CONFIG_CPU_S3C2416
13
14struct s3c2410_uartcfg;
15
16extern int s3c2416_init(void);
17
18extern void s3c2416_map_io(void);
19
20extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
21
22extern void s3c2416_init_clocks(int xtal);
23
24extern int s3c2416_baseclk_add(void);
25
26#else
27#define s3c2416_init_clocks NULL
28#define s3c2416_init_uarts NULL
29#define s3c2416_map_io NULL
30#define s3c2416_init NULL
31#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
new file mode 100644
index 00000000000..7fae1a05069
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -0,0 +1,52 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2443 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2443
14
15struct s3c2410_uartcfg;
16
17extern int s3c2443_init(void);
18
19extern void s3c2443_map_io(void);
20
21extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22
23extern void s3c2443_init_clocks(int xtal);
24
25extern int s3c2443_baseclk_add(void);
26
27#else
28#define s3c2443_init_clocks NULL
29#define s3c2443_init_uarts NULL
30#define s3c2443_map_io NULL
31#define s3c2443_init NULL
32#endif
33
34/* common code used by s3c2443 and others.
35 * note, not to be used outside of arch/arm/mach-s3c* */
36
37struct clk; /* some files don't need clk.h otherwise */
38
39typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
40
41extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
42extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
43 unsigned int *divs, int nr_divs,
44 int divmask);
45
46extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
47extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
48extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
49
50extern struct clksrc_clk clk_epllref;
51extern struct clksrc_clk clk_esysclk;
52extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
new file mode 100644
index 00000000000..ea0c961b760
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c244x.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2440 and S3C2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
14
15extern void s3c244x_map_io(void);
16
17extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18
19extern void s3c244x_init_clocks(int xtal);
20
21#else
22#define s3c244x_init_clocks NULL
23#define s3c244x_init_uarts NULL
24#endif
25
26#ifdef CONFIG_CPU_S3C2440
27extern int s3c2440_init(void);
28
29extern void s3c2440_map_io(void);
30#else
31#define s3c2440_init NULL
32#define s3c2440_map_io NULL
33#endif
34
35#ifdef CONFIG_CPU_S3C2442
36extern int s3c2442_init(void);
37
38extern void s3c2442_map_io(void);
39#else
40#define s3c2442_init NULL
41#define s3c2442_map_io NULL
42#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c6400.h b/arch/arm/plat-samsung/include/plat/s3c6400.h
new file mode 100644
index 00000000000..37d428aaaeb
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c6400.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c6400.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6400 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S3C6400 related SoCs */
16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_setup_clocks(void);
19
20extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
21
22#ifdef CONFIG_CPU_S3C6400
23
24extern int s3c6400_init(void);
25extern void s3c6400_init_irq(void);
26extern void s3c6400_map_io(void);
27extern void s3c6400_init_clocks(int xtal);
28
29#define s3c6400_init_uarts s3c6400_common_init_uarts
30
31#else
32#define s3c6400_init_clocks NULL
33#define s3c6400_init_uarts NULL
34#define s3c6400_map_io NULL
35#define s3c6400_init NULL
36#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c6410.h b/arch/arm/plat-samsung/include/plat/s3c6410.h
new file mode 100644
index 00000000000..20a6675b9d1
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c6410.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c6410.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6410 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifdef CONFIG_CPU_S3C6410
16
17extern int s3c6410_init(void);
18extern void s3c6410_init_irq(void);
19extern void s3c6410_map_io(void);
20extern void s3c6410_init_clocks(int xtal);
21
22#define s3c6410_init_uarts s3c6400_common_init_uarts
23
24#else
25#define s3c6410_init_clocks NULL
26#define s3c6410_init_uarts NULL
27#define s3c6410_map_io NULL
28#define s3c6410_init NULL
29#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
new file mode 100644
index 00000000000..984bf9e7bc8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -0,0 +1,55 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_CLOCK_H
14#define __ASM_PLAT_S5P_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19
20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux
24#define clk_fin_vpll clk_ext_xtal_mux
25#define clk_fin_hpll clk_ext_xtal_mux
26
27extern struct clk clk_ext_xtal_mux;
28extern struct clk clk_xusbxti;
29extern struct clk clk_48m;
30extern struct clk s5p_clk_27m;
31extern struct clk clk_fout_apll;
32extern struct clk clk_fout_mpll;
33extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll;
35extern struct clk clk_fout_vpll;
36extern struct clk clk_arm;
37extern struct clk clk_vpll;
38
39extern struct clksrc_sources clk_src_apll;
40extern struct clksrc_sources clk_src_mpll;
41extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll;
43
44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
45
46/* Common EPLL operations for S5P platform */
47extern int s5p_epll_enable(struct clk *clk, int enable);
48extern unsigned long s5p_epll_get_rate(struct clk *clk);
49
50/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
51extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
52extern unsigned long s5p_spdif_get_rate(struct clk *clk);
53
54extern struct clk_ops s5p_sclk_spdif_ops;
55#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
new file mode 100644
index 00000000000..3a70aebc920
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p-time.h
@@ -0,0 +1,40 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
2 *
3 * Copyright 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5p time support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_TIME_H
14#define __ASM_PLAT_S5P_TIME_H __FILE__
15
16/* S5P HR-Timer Clock mode */
17enum s5p_timer_mode {
18 S5P_PWM0,
19 S5P_PWM1,
20 S5P_PWM2,
21 S5P_PWM3,
22 S5P_PWM4,
23};
24
25struct s5p_timer_source {
26 unsigned int event_id;
27 unsigned int source_id;
28};
29
30/* Be able to sleep for atleast 4 seconds (usually more) */
31#define S5PTIMER_MIN_RANGE 4
32
33#define TCNT_MAX 0xffffffff
34#define NON_PERIODIC 0
35#define PERIODIC 1
36
37extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
38 enum s5p_timer_mode source);
39extern struct sys_timer s5p_timer;
40#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/s5p6440.h b/arch/arm/plat-samsung/include/plat/s5p6440.h
new file mode 100644
index 00000000000..bf85ebbb4fb
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p6440.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p6440.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5p6440 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13 /* Common init code for S5P6440 related SoCs */
14
15extern void s5p6440_register_clocks(void);
16extern void s5p6440_setup_clocks(void);
17
18#ifdef CONFIG_CPU_S5P6440
19
20extern int s5p64x0_init(void);
21extern void s5p6440_init_irq(void);
22extern void s5p6440_map_io(void);
23extern void s5p6440_init_clocks(int xtal);
24
25extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
26
27#else
28#define s5p6440_init_clocks NULL
29#define s5p6440_init_uarts NULL
30#define s5p6440_map_io NULL
31#define s5p64x0_init NULL
32#endif
33
34/* S5P6440 timer */
35
36extern struct sys_timer s5p6440_timer;
diff --git a/arch/arm/plat-samsung/include/plat/s5p6450.h b/arch/arm/plat-samsung/include/plat/s5p6450.h
new file mode 100644
index 00000000000..da25f9a1c54
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5p6450.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p6450 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5P6450 related SoCs */
14
15extern void s5p6450_register_clocks(void);
16extern void s5p6450_setup_clocks(void);
17
18#ifdef CONFIG_CPU_S5P6450
19
20extern int s5p64x0_init(void);
21extern void s5p6450_init_irq(void);
22extern void s5p6450_map_io(void);
23extern void s5p6450_init_clocks(int xtal);
24
25extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
26
27#else
28#define s5p6450_init_clocks NULL
29#define s5p6450_init_uarts NULL
30#define s5p6450_map_io NULL
31#define s5p64x0_init NULL
32#endif
33
34/* S5P6450 timer */
35
36extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-samsung/include/plat/s5pc100.h b/arch/arm/plat-samsung/include/plat/s5pc100.h
new file mode 100644
index 00000000000..9a21aeaaf45
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5pc100.h
@@ -0,0 +1,33 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5pc100.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pc100 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PC100 related SoCs */
14
15extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pc100_register_clocks(void);
17extern void s5pc100_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PC100
20
21extern int s5pc100_init(void);
22extern void s5pc100_init_irq(void);
23extern void s5pc100_map_io(void);
24extern void s5pc100_init_clocks(int xtal);
25
26#define s5pc100_init_uarts s5pc100_common_init_uarts
27
28#else
29#define s5pc100_init_clocks NULL
30#define s5pc100_init_uarts NULL
31#define s5pc100_map_io NULL
32#define s5pc100_init NULL
33#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5pv210.h b/arch/arm/plat-samsung/include/plat/s5pv210.h
new file mode 100644
index 00000000000..b4bc6be7707
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s5pv210.h
@@ -0,0 +1,33 @@
1/* linux/arch/arm/plat-samsung/include/plat/s5pv210.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pv210 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PV210 related SoCs */
14
15extern void s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pv210_register_clocks(void);
17extern void s5pv210_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PV210
20
21extern int s5pv210_init(void);
22extern void s5pv210_init_irq(void);
23extern void s5pv210_map_io(void);
24extern void s5pv210_init_clocks(int xtal);
25
26#define s5pv210_init_uarts s5pv210_common_init_uarts
27
28#else
29#define s5pv210_init_clocks NULL
30#define s5pv210_init_uarts NULL
31#define s5pv210_map_io NULL
32#define s5pv210_init NULL
33#endif
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 4a6552066c7..e7b3c752e91 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -55,10 +55,6 @@ enum clk_types {
55 * cd_type == S3C_SDHCI_CD_GPIO 55 * cd_type == S3C_SDHCI_CD_GPIO
56 * @ext_cd_gpio_invert: invert values for external CD gpio line 56 * @ext_cd_gpio_invert: invert values for external CD gpio line
57 * @cfg_gpio: Configure the GPIO for a specific card bit-width 57 * @cfg_gpio: Configure the GPIO for a specific card bit-width
58 * @cfg_card: Configure the interface for a specific card and speed. This
59 * is necessary the controllers and/or GPIO blocks require the
60 * changing of driver-strength and other controls dependent on
61 * the card and speed of operation.
62 * 58 *
63 * Initialisation data specific to either the machine or the platform 59 * Initialisation data specific to either the machine or the platform
64 * for the device driver to use or call-back when configuring gpio or 60 * for the device driver to use or call-back when configuring gpio or
@@ -80,10 +76,6 @@ struct s3c_sdhci_platdata {
80 int state)); 76 int state));
81 77
82 void (*cfg_gpio)(struct platform_device *dev, int width); 78 void (*cfg_gpio)(struct platform_device *dev, int width);
83 void (*cfg_card)(struct platform_device *dev,
84 void __iomem *regbase,
85 struct mmc_ios *ios,
86 struct mmc_card *card);
87}; 79};
88 80
89/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data 81/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
@@ -139,17 +131,11 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
139#ifdef CONFIG_S3C2416_SETUP_SDHCI 131#ifdef CONFIG_S3C2416_SETUP_SDHCI
140extern char *s3c2416_hsmmc_clksrcs[4]; 132extern char *s3c2416_hsmmc_clksrcs[4];
141 133
142extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
143 void __iomem *r,
144 struct mmc_ios *ios,
145 struct mmc_card *card);
146
147static inline void s3c2416_default_sdhci0(void) 134static inline void s3c2416_default_sdhci0(void)
148{ 135{
149#ifdef CONFIG_S3C_DEV_HSMMC 136#ifdef CONFIG_S3C_DEV_HSMMC
150 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; 137 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
151 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; 138 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
152 s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
153#endif /* CONFIG_S3C_DEV_HSMMC */ 139#endif /* CONFIG_S3C_DEV_HSMMC */
154} 140}
155 141
@@ -158,7 +144,6 @@ static inline void s3c2416_default_sdhci1(void)
158#ifdef CONFIG_S3C_DEV_HSMMC1 144#ifdef CONFIG_S3C_DEV_HSMMC1
159 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; 145 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
160 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; 146 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
161 s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
162#endif /* CONFIG_S3C_DEV_HSMMC1 */ 147#endif /* CONFIG_S3C_DEV_HSMMC1 */
163} 148}
164 149
@@ -172,17 +157,11 @@ static inline void s3c2416_default_sdhci1(void) { }
172#ifdef CONFIG_S3C64XX_SETUP_SDHCI 157#ifdef CONFIG_S3C64XX_SETUP_SDHCI
173extern char *s3c64xx_hsmmc_clksrcs[4]; 158extern char *s3c64xx_hsmmc_clksrcs[4];
174 159
175extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
176 void __iomem *r,
177 struct mmc_ios *ios,
178 struct mmc_card *card);
179
180static inline void s3c6400_default_sdhci0(void) 160static inline void s3c6400_default_sdhci0(void)
181{ 161{
182#ifdef CONFIG_S3C_DEV_HSMMC 162#ifdef CONFIG_S3C_DEV_HSMMC
183 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 163 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
184 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 164 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
185 s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
186#endif 165#endif
187} 166}
188 167
@@ -191,7 +170,6 @@ static inline void s3c6400_default_sdhci1(void)
191#ifdef CONFIG_S3C_DEV_HSMMC1 170#ifdef CONFIG_S3C_DEV_HSMMC1
192 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 171 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
193 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 172 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
194 s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
195#endif 173#endif
196} 174}
197 175
@@ -200,21 +178,14 @@ static inline void s3c6400_default_sdhci2(void)
200#ifdef CONFIG_S3C_DEV_HSMMC2 178#ifdef CONFIG_S3C_DEV_HSMMC2
201 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 179 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
202 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 180 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
203 s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
204#endif 181#endif
205} 182}
206 183
207extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
208 void __iomem *r,
209 struct mmc_ios *ios,
210 struct mmc_card *card);
211
212static inline void s3c6410_default_sdhci0(void) 184static inline void s3c6410_default_sdhci0(void)
213{ 185{
214#ifdef CONFIG_S3C_DEV_HSMMC 186#ifdef CONFIG_S3C_DEV_HSMMC
215 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 187 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
216 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 188 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
217 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
218#endif 189#endif
219} 190}
220 191
@@ -223,7 +194,6 @@ static inline void s3c6410_default_sdhci1(void)
223#ifdef CONFIG_S3C_DEV_HSMMC1 194#ifdef CONFIG_S3C_DEV_HSMMC1
224 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 195 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
225 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 196 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
226 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
227#endif 197#endif
228} 198}
229 199
@@ -232,7 +202,6 @@ static inline void s3c6410_default_sdhci2(void)
232#ifdef CONFIG_S3C_DEV_HSMMC2 202#ifdef CONFIG_S3C_DEV_HSMMC2
233 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; 203 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
234 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 204 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
235 s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
236#endif 205#endif
237} 206}
238 207
@@ -251,17 +220,11 @@ static inline void s3c6400_default_sdhci2(void) { }
251#ifdef CONFIG_S5PC100_SETUP_SDHCI 220#ifdef CONFIG_S5PC100_SETUP_SDHCI
252extern char *s5pc100_hsmmc_clksrcs[4]; 221extern char *s5pc100_hsmmc_clksrcs[4];
253 222
254extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
255 void __iomem *r,
256 struct mmc_ios *ios,
257 struct mmc_card *card);
258
259static inline void s5pc100_default_sdhci0(void) 223static inline void s5pc100_default_sdhci0(void)
260{ 224{
261#ifdef CONFIG_S3C_DEV_HSMMC 225#ifdef CONFIG_S3C_DEV_HSMMC
262 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; 226 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; 227 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
264 s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
265#endif 228#endif
266} 229}
267 230
@@ -270,7 +233,6 @@ static inline void s5pc100_default_sdhci1(void)
270#ifdef CONFIG_S3C_DEV_HSMMC1 233#ifdef CONFIG_S3C_DEV_HSMMC1
271 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; 234 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
272 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; 235 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
273 s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
274#endif 236#endif
275} 237}
276 238
@@ -279,7 +241,6 @@ static inline void s5pc100_default_sdhci2(void)
279#ifdef CONFIG_S3C_DEV_HSMMC2 241#ifdef CONFIG_S3C_DEV_HSMMC2
280 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; 242 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
281 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; 243 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
282 s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
283#endif 244#endif
284} 245}
285 246
@@ -295,17 +256,11 @@ static inline void s5pc100_default_sdhci2(void) { }
295#ifdef CONFIG_S5PV210_SETUP_SDHCI 256#ifdef CONFIG_S5PV210_SETUP_SDHCI
296extern char *s5pv210_hsmmc_clksrcs[4]; 257extern char *s5pv210_hsmmc_clksrcs[4];
297 258
298extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
299 void __iomem *r,
300 struct mmc_ios *ios,
301 struct mmc_card *card);
302
303static inline void s5pv210_default_sdhci0(void) 259static inline void s5pv210_default_sdhci0(void)
304{ 260{
305#ifdef CONFIG_S3C_DEV_HSMMC 261#ifdef CONFIG_S3C_DEV_HSMMC
306 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 262 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
307 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; 263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
308 s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
309#endif 264#endif
310} 265}
311 266
@@ -314,7 +269,6 @@ static inline void s5pv210_default_sdhci1(void)
314#ifdef CONFIG_S3C_DEV_HSMMC1 269#ifdef CONFIG_S3C_DEV_HSMMC1
315 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 270 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
316 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; 271 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
317 s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
318#endif 272#endif
319} 273}
320 274
@@ -323,7 +277,6 @@ static inline void s5pv210_default_sdhci2(void)
323#ifdef CONFIG_S3C_DEV_HSMMC2 277#ifdef CONFIG_S3C_DEV_HSMMC2
324 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 278 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
325 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; 279 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
326 s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
327#endif 280#endif
328} 281}
329 282
@@ -332,7 +285,6 @@ static inline void s5pv210_default_sdhci3(void)
332#ifdef CONFIG_S3C_DEV_HSMMC3 285#ifdef CONFIG_S3C_DEV_HSMMC3
333 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; 286 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
334 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; 287 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
335 s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
336#endif 288#endif
337} 289}
338 290
@@ -348,17 +300,11 @@ static inline void s5pv210_default_sdhci3(void) { }
348#ifdef CONFIG_EXYNOS4_SETUP_SDHCI 300#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
349extern char *exynos4_hsmmc_clksrcs[4]; 301extern char *exynos4_hsmmc_clksrcs[4];
350 302
351extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
352 void __iomem *r,
353 struct mmc_ios *ios,
354 struct mmc_card *card);
355
356static inline void exynos4_default_sdhci0(void) 303static inline void exynos4_default_sdhci0(void)
357{ 304{
358#ifdef CONFIG_S3C_DEV_HSMMC 305#ifdef CONFIG_S3C_DEV_HSMMC
359 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; 306 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
360 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; 307 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
361 s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
362#endif 308#endif
363} 309}
364 310
@@ -367,7 +313,6 @@ static inline void exynos4_default_sdhci1(void)
367#ifdef CONFIG_S3C_DEV_HSMMC1 313#ifdef CONFIG_S3C_DEV_HSMMC1
368 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; 314 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
369 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; 315 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
370 s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
371#endif 316#endif
372} 317}
373 318
@@ -376,7 +321,6 @@ static inline void exynos4_default_sdhci2(void)
376#ifdef CONFIG_S3C_DEV_HSMMC2 321#ifdef CONFIG_S3C_DEV_HSMMC2
377 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; 322 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
378 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; 323 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
379 s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
380#endif 324#endif
381} 325}
382 326
@@ -385,7 +329,6 @@ static inline void exynos4_default_sdhci3(void)
385#ifdef CONFIG_S3C_DEV_HSMMC3 329#ifdef CONFIG_S3C_DEV_HSMMC3
386 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; 330 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
387 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; 331 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
388 s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
389#endif 332#endif
390} 333}
391 334
diff --git a/arch/arm/plat-samsung/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h
new file mode 100644
index 00000000000..5fe8ee01a5b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/sysmmu.h
@@ -0,0 +1,95 @@
1/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung System MMU driver for S5P platform
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_SYSMMU_H
14#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
15
16enum S5P_SYSMMU_INTERRUPT_TYPE {
17 SYSMMU_PAGEFAULT,
18 SYSMMU_AR_MULTIHIT,
19 SYSMMU_AW_MULTIHIT,
20 SYSMMU_BUSERROR,
21 SYSMMU_AR_SECURITY,
22 SYSMMU_AR_ACCESS,
23 SYSMMU_AW_SECURITY,
24 SYSMMU_AW_PROTECTION, /* 7 */
25 SYSMMU_FAULTS_NUM
26};
27
28#ifdef CONFIG_S5P_SYSTEM_MMU
29
30#include <mach/sysmmu.h>
31
32/**
33 * s5p_sysmmu_enable() - enable system mmu of ip
34 * @ips: The ip connected system mmu.
35 * #pgd: Base physical address of the 1st level page table
36 *
37 * This function enable system mmu to transfer address
38 * from virtual address to physical address
39 */
40void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
41
42/**
43 * s5p_sysmmu_disable() - disable sysmmu mmu of ip
44 * @ips: The ip connected system mmu.
45 *
46 * This function disable system mmu to transfer address
47 * from virtual address to physical address
48 */
49void s5p_sysmmu_disable(sysmmu_ips ips);
50
51/**
52 * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
53 * @ips: The ip connected system mmu.
54 * @pgd: The page table base address.
55 *
56 * This function set page table base address
57 * When system mmu transfer address from virtaul address to physical address,
58 * system mmu refer address information from page table
59 */
60void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
61
62/**
63 * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
64 * @ips: The ip connected system mmu.
65 *
66 * This function flush all TLB entry in system mmu
67 */
68void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
69
70/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
71 * @itype: type of fault.
72 * @pgtable_base: the physical address of page table base. This is 0 if @ips is
73 * SYSMMU_BUSERROR.
74 * @fault_addr: the device (virtual) address that the System MMU tried to
75 * translated. This is 0 if @ips is SYSMMU_BUSERROR.
76 * Called when interrupt occurred by the System MMUs
77 * The device drivers of peripheral devices that has a System MMU can implement
78 * a fault handler to resolve address translation fault by System MMU.
79 * The meanings of return value and parameters are described below.
80
81 * return value: non-zero if the fault is correctly resolved.
82 * zero if the fault is not handled.
83 */
84void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
85 int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
86 unsigned long pgtable_base,
87 unsigned long fault_addr));
88#else
89#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
90#define s5p_sysmmu_disable(ips) do { } while (0)
91#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
92#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
93#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
94#endif
95#endif /* __ASM_PLAT_SYSMMU_H */
diff --git a/arch/arm/plat-samsung/include/plat/system-reset.h b/arch/arm/plat-samsung/include/plat/system-reset.h
new file mode 100644
index 00000000000..a448e990964
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/system-reset.h
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-samsung/include/plat/system-reset.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
7 *
8 * S5P - System define for arch_reset()
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/watchdog-reset.h>
16
17void (*s5p_reset_hook)(void);
18
19static void arch_reset(char mode, const char *cmd)
20{
21 /* SWRESET support in s5p_reset_hook() */
22
23 if (s5p_reset_hook)
24 s5p_reset_hook();
25
26 /* Perform reset using Watchdog reset
27 * if there is no s5p_reset_hook()
28 */
29
30 arch_wdt_reset();
31}
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
new file mode 100644
index 00000000000..3bc34f3ce28
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/tv-core.h
@@ -0,0 +1,44 @@
1/*
2 * arch/arm/plat-samsung/include/plat/tv.h
3 *
4 * Copyright 2011 Samsung Electronics Co., Ltd.
5 * Tomasz Stanislawski <t.stanislaws@samsung.com>
6 *
7 * Samsung TV driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __SAMSUNG_PLAT_TV_H
15#define __SAMSUNG_PLAT_TV_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s5p_hdmi_setname(char *name)
24{
25#ifdef CONFIG_S5P_DEV_TV
26 s5p_device_hdmi.name = name;
27#endif
28}
29
30static inline void s5p_mixer_setname(char *name)
31{
32#ifdef CONFIG_S5P_DEV_TV
33 s5p_device_mixer.name = name;
34#endif
35}
36
37static inline void s5p_sdo_setname(char *name)
38{
39#ifdef CONFIG_S5P_DEV_TV
40 s5p_device_sdo.name = name;
41#endif
42}
43
44#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h
new file mode 100644
index 00000000000..8c22d586bef
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/udc.h
@@ -0,0 +1,57 @@
1/* arch/arm/plat-samsung/include/plat/udc.h
2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *
11 * Changelog:
12 * 14-Mar-2005 RTP Created file
13 * 02-Aug-2005 RTP File rename
14 * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
15 * 18-Jan-2007 HMW Add per-platform vbus_draw function
16*/
17
18#ifndef __ASM_ARM_ARCH_UDC_H
19#define __ASM_ARM_ARCH_UDC_H
20
21enum s3c2410_udc_cmd_e {
22 S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
23 S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
24 S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
25};
26
27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma);
30
31 unsigned int pullup_pin;
32 unsigned int pullup_pin_inverted;
33
34 unsigned int vbus_pin;
35 unsigned char vbus_pin_inverted;
36};
37
38extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
39
40/**
41 * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
42 * @epnum: Number of endpoints to be instantiated by the controller driver.
43 * @gpio_init: Platform specific USB related GPIO initialization.
44 * @gpio_uninit: Platform specific USB releted GPIO uninitialzation.
45 *
46 * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
47 * controllers.
48 */
49struct s3c24xx_hsudc_platdata {
50 unsigned int epnum;
51 void (*gpio_init)(void);
52 void (*gpio_uninit)(void);
53};
54
55extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
56
57#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
new file mode 100644
index 00000000000..959bcdb03a2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_SAMSUNG_USB_PHY_H
12#define __PLAT_SAMSUNG_USB_PHY_H __FILE__
13
14enum s5p_usb_phy_type {
15 S5P_USB_PHY_DEVICE,
16 S5P_USB_PHY_HOST,
17};
18
19extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
20extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
21
22#endif /* __PLAT_SAMSUNG_USB_PHY_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 00:40:09 -0400