diff options
Diffstat (limited to 'arch/arm/plat-samsung/include/plat')
-rw-r--r-- | arch/arm/plat-samsung/include/plat/ata.h | 36 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/audio.h | 59 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/hwmon.h | 51 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/iic.h | 76 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/nand.h | 67 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/pd.h | 30 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/pll6553x.h | 51 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-fb.h | 386 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h | 379 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h | 98 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h | 32 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 75 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/ts.h | 25 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/udc-hs.h | 29 | ||||
-rw-r--r-- | arch/arm/plat-samsung/include/plat/usb-control.h | 43 |
16 files changed, 1596 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/ata.h b/arch/arm/plat-samsung/include/plat/ata.h new file mode 100644 index 00000000000..2a3855a8372 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/ata.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/ata.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Samsung CF-ATA platform_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_PLAT_ATA_H | ||
14 | #define __ASM_PLAT_ATA_H __FILE__ | ||
15 | |||
16 | /** | ||
17 | * struct s3c_ide_platdata - S3C IDE driver platform data. | ||
18 | * @setup_gpio: Setup the external GPIO pins to the right state for data | ||
19 | * transfer in true-ide mode. | ||
20 | */ | ||
21 | struct s3c_ide_platdata { | ||
22 | void (*setup_gpio)(void); | ||
23 | }; | ||
24 | |||
25 | /* | ||
26 | * s3c_ide_set_platdata() - Setup the platform specifc data for IDE driver. | ||
27 | * @pdata: Platform data for IDE driver. | ||
28 | */ | ||
29 | extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata); | ||
30 | |||
31 | /* architecture-specific IDE configuration */ | ||
32 | extern void s3c64xx_ide_setup_gpio(void); | ||
33 | extern void s5pc100_ide_setup_gpio(void); | ||
34 | extern void s5pv210_ide_setup_gpio(void); | ||
35 | |||
36 | #endif /*__ASM_PLAT_ATA_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h new file mode 100644 index 00000000000..aa9875f77c4 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/audio.h | |||
@@ -0,0 +1,59 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/audio.h | ||
2 | * | ||
3 | * Copyright (c) 2009 Samsung Electronics Co. Ltd | ||
4 | * Author: Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | /* The machine init code calls s3c*_ac97_setup_gpio with | ||
12 | * one of these defines in order to select appropriate bank | ||
13 | * of GPIO for AC97 pins | ||
14 | */ | ||
15 | #define S3C64XX_AC97_GPD 0 | ||
16 | #define S3C64XX_AC97_GPE 1 | ||
17 | extern void s3c64xx_ac97_setup_gpio(int); | ||
18 | |||
19 | /* | ||
20 | * The machine init code calls s5p*_spdif_setup_gpio with | ||
21 | * one of these defines in order to select appropriate bank | ||
22 | * of GPIO for S/PDIF pins | ||
23 | */ | ||
24 | #define S5PC100_SPDIF_GPD 0 | ||
25 | #define S5PC100_SPDIF_GPG3 1 | ||
26 | extern void s5pc100_spdif_setup_gpio(int); | ||
27 | |||
28 | struct samsung_i2s { | ||
29 | /* If the Primary DAI has 5.1 Channels */ | ||
30 | #define QUIRK_PRI_6CHAN (1 << 0) | ||
31 | /* If the I2S block has a Stereo Overlay Channel */ | ||
32 | #define QUIRK_SEC_DAI (1 << 1) | ||
33 | /* | ||
34 | * If the I2S block has no internal prescalar or MUX (I2SMOD[10] bit) | ||
35 | * The Machine driver must provide suitably set clock to the I2S block. | ||
36 | */ | ||
37 | #define QUIRK_NO_MUXPSR (1 << 2) | ||
38 | #define QUIRK_NEED_RSTCLR (1 << 3) | ||
39 | /* Quirks of the I2S controller */ | ||
40 | u32 quirks; | ||
41 | |||
42 | /* | ||
43 | * Array of clock names that can be used to generate I2S signals. | ||
44 | * Also corresponds to clocks of I2SMOD[10] | ||
45 | */ | ||
46 | const char **src_clk; | ||
47 | dma_addr_t idma_addr; | ||
48 | }; | ||
49 | |||
50 | /** | ||
51 | * struct s3c_audio_pdata - common platform data for audio device drivers | ||
52 | * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode | ||
53 | */ | ||
54 | struct s3c_audio_pdata { | ||
55 | int (*cfg_gpio)(struct platform_device *); | ||
56 | union { | ||
57 | struct samsung_i2s i2s; | ||
58 | } type; | ||
59 | }; | ||
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h new file mode 100644 index 00000000000..c167e4429bc --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/hwmon.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/hwmon.h | ||
2 | * | ||
3 | * Copyright 2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C - HWMon interface for ADC | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_ADC_HWMON_H | ||
15 | #define __ASM_ARCH_ADC_HWMON_H __FILE__ | ||
16 | |||
17 | /** | ||
18 | * s3c_hwmon_chcfg - channel configuration | ||
19 | * @name: The name to give this channel. | ||
20 | * @mult: Multiply the ADC value read by this. | ||
21 | * @div: Divide the value from the ADC by this. | ||
22 | * | ||
23 | * The value read from the ADC is converted to a value that | ||
24 | * hwmon expects (mV) by result = (value_read * @mult) / @div. | ||
25 | */ | ||
26 | struct s3c_hwmon_chcfg { | ||
27 | const char *name; | ||
28 | unsigned int mult; | ||
29 | unsigned int div; | ||
30 | }; | ||
31 | |||
32 | /** | ||
33 | * s3c_hwmon_pdata - HWMON platform data | ||
34 | * @in: One configuration for each possible channel used. | ||
35 | */ | ||
36 | struct s3c_hwmon_pdata { | ||
37 | struct s3c_hwmon_chcfg *in[8]; | ||
38 | }; | ||
39 | |||
40 | /** | ||
41 | * s3c_hwmon_set_platdata - Set platform data for S3C HWMON device | ||
42 | * @pd: Platform data to register to device. | ||
43 | * | ||
44 | * Register the given platform data for use with the S3C HWMON device. | ||
45 | * The call will copy the platform data, so the board definitions can | ||
46 | * make the structure itself __initdata. | ||
47 | */ | ||
48 | extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd); | ||
49 | |||
50 | #endif /* __ASM_ARCH_ADC_HWMON_H */ | ||
51 | |||
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h new file mode 100644 index 00000000000..56b0059439e --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/iic.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/iic.h | ||
2 | * | ||
3 | * Copyright 2004-2009 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C - I2C Controller platform_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_IIC_H | ||
14 | #define __ASM_ARCH_IIC_H __FILE__ | ||
15 | |||
16 | #define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */ | ||
17 | |||
18 | /** | ||
19 | * struct s3c2410_platform_i2c - Platform data for s3c I2C. | ||
20 | * @bus_num: The bus number to use (if possible). | ||
21 | * @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER). | ||
22 | * @slave_addr: The I2C address for the slave device (if enabled). | ||
23 | * @frequency: The desired frequency in Hz of the bus. This is | ||
24 | * guaranteed to not be exceeded. If the caller does | ||
25 | * not care, use zero and the driver will select a | ||
26 | * useful default. | ||
27 | * @sda_delay: The delay (in ns) applied to SDA edges. | ||
28 | * @cfg_gpio: A callback to configure the pins for I2C operation. | ||
29 | */ | ||
30 | struct s3c2410_platform_i2c { | ||
31 | int bus_num; | ||
32 | unsigned int flags; | ||
33 | unsigned int slave_addr; | ||
34 | unsigned long frequency; | ||
35 | unsigned int sda_delay; | ||
36 | |||
37 | void (*cfg_gpio)(struct platform_device *dev); | ||
38 | }; | ||
39 | |||
40 | /** | ||
41 | * s3c_i2c0_set_platdata - set platform data for i2c0 device | ||
42 | * @i2c: The platform data to set, or NULL for default data. | ||
43 | * | ||
44 | * Register the given platform data for use with the i2c0 device. This | ||
45 | * call copies the platform data, so the caller can use __initdata for | ||
46 | * their copy. | ||
47 | * | ||
48 | * This call will set cfg_gpio if is null to the default platform | ||
49 | * implementation. | ||
50 | * | ||
51 | * Any user of s3c_device_i2c0 should call this, even if it is with | ||
52 | * NULL to ensure that the device is given the default platform data | ||
53 | * as the driver will no longer carry defaults. | ||
54 | */ | ||
55 | extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
56 | extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
57 | extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
58 | extern void s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
59 | extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
60 | extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
61 | extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
62 | extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
63 | |||
64 | /* defined by architecture to configure gpio */ | ||
65 | extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); | ||
66 | extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); | ||
67 | extern void s3c_i2c2_cfg_gpio(struct platform_device *dev); | ||
68 | extern void s3c_i2c3_cfg_gpio(struct platform_device *dev); | ||
69 | extern void s3c_i2c4_cfg_gpio(struct platform_device *dev); | ||
70 | extern void s3c_i2c5_cfg_gpio(struct platform_device *dev); | ||
71 | extern void s3c_i2c6_cfg_gpio(struct platform_device *dev); | ||
72 | extern void s3c_i2c7_cfg_gpio(struct platform_device *dev); | ||
73 | |||
74 | extern struct s3c2410_platform_i2c default_i2c_data; | ||
75 | |||
76 | #endif /* __ASM_ARCH_IIC_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h new file mode 100644 index 00000000000..b64115fa93a --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/nand.h | |||
@@ -0,0 +1,67 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/nand.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - NAND device controller platform_device info | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /** | ||
14 | * struct s3c2410_nand_set - define a set of one or more nand chips | ||
15 | * @disable_ecc: Entirely disable ECC - Dangerous | ||
16 | * @flash_bbt: Openmoko u-boot can create a Bad Block Table | ||
17 | * Setting this flag will allow the kernel to | ||
18 | * look for it at boot time and also skip the NAND | ||
19 | * scan. | ||
20 | * @options: Default value to set into 'struct nand_chip' options. | ||
21 | * @nr_chips: Number of chips in this set | ||
22 | * @nr_partitions: Number of partitions pointed to by @partitions | ||
23 | * @name: Name of set (optional) | ||
24 | * @nr_map: Map for low-layer logical to physical chip numbers (option) | ||
25 | * @partitions: The mtd partition list | ||
26 | * | ||
27 | * define a set of one or more nand chips registered with an unique mtd. Also | ||
28 | * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger | ||
29 | * a warning at boot time. | ||
30 | */ | ||
31 | struct s3c2410_nand_set { | ||
32 | unsigned int disable_ecc:1; | ||
33 | unsigned int flash_bbt:1; | ||
34 | |||
35 | unsigned int options; | ||
36 | int nr_chips; | ||
37 | int nr_partitions; | ||
38 | char *name; | ||
39 | int *nr_map; | ||
40 | struct mtd_partition *partitions; | ||
41 | struct nand_ecclayout *ecc_layout; | ||
42 | }; | ||
43 | |||
44 | struct s3c2410_platform_nand { | ||
45 | /* timing information for controller, all times in nanoseconds */ | ||
46 | |||
47 | int tacls; /* time for active CLE/ALE to nWE/nOE */ | ||
48 | int twrph0; /* active time for nWE/nOE */ | ||
49 | int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ | ||
50 | |||
51 | unsigned int ignore_unset_ecc:1; | ||
52 | |||
53 | int nr_sets; | ||
54 | struct s3c2410_nand_set *sets; | ||
55 | |||
56 | void (*select_chip)(struct s3c2410_nand_set *, | ||
57 | int chip); | ||
58 | }; | ||
59 | |||
60 | /** | ||
61 | * s3c_nand_set_platdata() - register NAND platform data. | ||
62 | * @nand: The NAND platform data to register with s3c_device_nand. | ||
63 | * | ||
64 | * This function copies the given NAND platform data, @nand and registers | ||
65 | * it with the s3c_device_nand. This allows @nand to be __initdata. | ||
66 | */ | ||
67 | extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand); | ||
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h new file mode 100644 index 00000000000..abb4bc32716 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pd.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/pd.h | ||
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_PLAT_SAMSUNG_PD_H | ||
12 | #define __ASM_PLAT_SAMSUNG_PD_H __FILE__ | ||
13 | |||
14 | struct samsung_pd_info { | ||
15 | int (*enable)(struct device *dev); | ||
16 | int (*disable)(struct device *dev); | ||
17 | void __iomem *base; | ||
18 | }; | ||
19 | |||
20 | enum exynos4_pd_block { | ||
21 | PD_MFC, | ||
22 | PD_G3D, | ||
23 | PD_LCD0, | ||
24 | PD_LCD1, | ||
25 | PD_TV, | ||
26 | PD_CAM, | ||
27 | PD_GPS | ||
28 | }; | ||
29 | |||
30 | #endif /* __ASM_PLAT_SAMSUNG_PD_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h new file mode 100644 index 00000000000..b8b7e1d884f --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/pll6553x.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/pll6553x.h | ||
2 | * partially from arch/arm/mach-s3c64xx/include/mach/pll.h | ||
3 | * | ||
4 | * Copyright 2008 Openmoko, Inc. | ||
5 | * Copyright 2008 Simtec Electronics | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * http://armlinux.simtec.co.uk/ | ||
8 | * | ||
9 | * Samsung PLL6553x PLL code | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | /* S3C6400 and compatible (S3C2416, etc.) EPLL code */ | ||
17 | |||
18 | #define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1) | ||
19 | #define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1) | ||
20 | #define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1) | ||
21 | #define PLL6553X_MDIV_SHIFT (16) | ||
22 | #define PLL6553X_PDIV_SHIFT (8) | ||
23 | #define PLL6553X_SDIV_SHIFT (0) | ||
24 | #define PLL6553X_KDIV_MASK (0xffff) | ||
25 | |||
26 | static inline unsigned long s3c_get_pll6553x(unsigned long baseclk, | ||
27 | u32 pll0, u32 pll1) | ||
28 | { | ||
29 | unsigned long result; | ||
30 | u32 mdiv, pdiv, sdiv, kdiv; | ||
31 | u64 tmp; | ||
32 | |||
33 | mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK; | ||
34 | pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK; | ||
35 | sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK; | ||
36 | kdiv = pll1 & PLL6553X_KDIV_MASK; | ||
37 | |||
38 | /* We need to multiple baseclk by mdiv (the integer part) and kdiv | ||
39 | * which is in 2^16ths, so shift mdiv up (does not overflow) and | ||
40 | * add kdiv before multiplying. The use of tmp is to avoid any | ||
41 | * overflows before shifting bac down into result when multipling | ||
42 | * by the mdiv and kdiv pair. | ||
43 | */ | ||
44 | |||
45 | tmp = baseclk; | ||
46 | tmp *= (mdiv << 16) + kdiv; | ||
47 | do_div(tmp, (pdiv << sdiv)); | ||
48 | result = tmp >> 16; | ||
49 | |||
50 | return result; | ||
51 | } | ||
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h new file mode 100644 index 00000000000..4c3647f8005 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h | |||
@@ -0,0 +1,159 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/regs-fb-v4.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C64XX - new-style framebuffer register definitions | ||
9 | * | ||
10 | * This is the register set for the new style framebuffer interface | ||
11 | * found from the S3C2443 onwards and specifically the S3C64XX series | ||
12 | * S3C6400 and S3C6410. | ||
13 | * | ||
14 | * The file contains the cpu specific items which change between whichever | ||
15 | * architecture is selected. See <plat/regs-fb.h> for the core definitions | ||
16 | * that are the same. | ||
17 | * | ||
18 | * This program is free software; you can redistribute it and/or modify | ||
19 | * it under the terms of the GNU General Public License version 2 as | ||
20 | * published by the Free Software Foundation. | ||
21 | */ | ||
22 | |||
23 | /* include the core definitions here, in case we really do need to | ||
24 | * override them at a later date. | ||
25 | */ | ||
26 | |||
27 | #include <plat/regs-fb.h> | ||
28 | |||
29 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ | ||
30 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | ||
31 | |||
32 | /* Video timing controls */ | ||
33 | #define VIDTCON0 (0x10) | ||
34 | #define VIDTCON1 (0x14) | ||
35 | #define VIDTCON2 (0x18) | ||
36 | |||
37 | /* Window position controls */ | ||
38 | |||
39 | #define WINCON(_win) (0x20 + ((_win) * 4)) | ||
40 | |||
41 | /* OSD1 and OSD4 do not have register D */ | ||
42 | |||
43 | #define VIDOSD_BASE (0x40) | ||
44 | |||
45 | #define VIDINTCON0 (0x130) | ||
46 | |||
47 | /* WINCONx */ | ||
48 | |||
49 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | ||
50 | #define WINCONx_CSCWIDTH_SHIFT (26) | ||
51 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | ||
52 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | ||
53 | |||
54 | #define WINCONx_ENLOCAL (1 << 22) | ||
55 | #define WINCONx_BUFSTATUS (1 << 21) | ||
56 | #define WINCONx_BUFSEL (1 << 20) | ||
57 | #define WINCONx_BUFAUTOEN (1 << 19) | ||
58 | #define WINCONx_YCbCr (1 << 13) | ||
59 | |||
60 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) | ||
61 | |||
62 | #define WINCON2_LOCALSEL_CAMIF (1 << 23) | ||
63 | #define WINCON2_BLD_PIX (1 << 6) | ||
64 | |||
65 | #define WINCON2_ALPHA_SEL (1 << 1) | ||
66 | #define WINCON2_BPPMODE_MASK (0xf << 2) | ||
67 | #define WINCON2_BPPMODE_SHIFT (2) | ||
68 | #define WINCON2_BPPMODE_1BPP (0x0 << 2) | ||
69 | #define WINCON2_BPPMODE_2BPP (0x1 << 2) | ||
70 | #define WINCON2_BPPMODE_4BPP (0x2 << 2) | ||
71 | #define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) | ||
72 | #define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) | ||
73 | #define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
74 | #define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
75 | #define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) | ||
76 | #define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
77 | #define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) | ||
78 | #define WINCON2_BPPMODE_24BPP_888 (0xb << 2) | ||
79 | #define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) | ||
80 | #define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) | ||
81 | #define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) | ||
82 | |||
83 | #define WINCON3_BLD_PIX (1 << 6) | ||
84 | |||
85 | #define WINCON3_ALPHA_SEL (1 << 1) | ||
86 | #define WINCON3_BPPMODE_MASK (0xf << 2) | ||
87 | #define WINCON3_BPPMODE_SHIFT (2) | ||
88 | #define WINCON3_BPPMODE_1BPP (0x0 << 2) | ||
89 | #define WINCON3_BPPMODE_2BPP (0x1 << 2) | ||
90 | #define WINCON3_BPPMODE_4BPP (0x2 << 2) | ||
91 | #define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) | ||
92 | #define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
93 | #define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
94 | #define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) | ||
95 | #define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
96 | #define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) | ||
97 | #define WINCON3_BPPMODE_24BPP_888 (0xb << 2) | ||
98 | #define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) | ||
99 | #define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) | ||
100 | #define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) | ||
101 | |||
102 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) | ||
103 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | ||
104 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | ||
105 | |||
106 | #define DITHMODE (0x170) | ||
107 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | ||
108 | |||
109 | |||
110 | #define DITHMODE_R_POS_MASK (0x3 << 5) | ||
111 | #define DITHMODE_R_POS_SHIFT (5) | ||
112 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | ||
113 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | ||
114 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | ||
115 | |||
116 | #define DITHMODE_G_POS_MASK (0x3 << 3) | ||
117 | #define DITHMODE_G_POS_SHIFT (3) | ||
118 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | ||
119 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | ||
120 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | ||
121 | |||
122 | #define DITHMODE_B_POS_MASK (0x3 << 1) | ||
123 | #define DITHMODE_B_POS_SHIFT (1) | ||
124 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | ||
125 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | ||
126 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | ||
127 | |||
128 | #define DITHMODE_DITH_EN (1 << 0) | ||
129 | |||
130 | #define WPALCON (0x1A0) | ||
131 | |||
132 | /* Palette control */ | ||
133 | /* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), | ||
134 | * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ | ||
135 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | ||
136 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | ||
137 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | ||
138 | |||
139 | |||
140 | /* Notes on per-window bpp settings | ||
141 | * | ||
142 | * Value Win0 Win1 Win2 Win3 Win 4 | ||
143 | * 0000 1(P) 1(P) 1(P) 1(P) 1(P) | ||
144 | * 0001 2(P) 2(P) 2(P) 2(P) 2(P) | ||
145 | * 0010 4(P) 4(P) 4(P) 4(P) -none- | ||
146 | * 0011 8(P) 8(P) -none- -none- -none- | ||
147 | * 0100 -none- 8(A232) 8(A232) -none- -none- | ||
148 | * 0101 16(565) 16(565) 16(565) 16(565) 16(565) | ||
149 | * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) | ||
150 | * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) | ||
151 | * 1000 18(666) 18(666) 18(666) 18(666) 18(666) | ||
152 | * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) | ||
153 | * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) | ||
154 | * 1011 24(888) 24(888) 24(888) 24(888) 24(888) | ||
155 | * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) | ||
156 | * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) | ||
157 | * 1110 -none- -none- -none- -none- -none- | ||
158 | * 1111 -none- -none- -none- -none- -none- | ||
159 | */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h new file mode 100644 index 00000000000..8f39aa5b26e --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h | |||
@@ -0,0 +1,386 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/regs-fb.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - new-style framebuffer register definitions | ||
9 | * | ||
10 | * This is the register set for the new style framebuffer interface | ||
11 | * found from the S3C2443 onwards into the S3C2416, S3C2450 and the | ||
12 | * S3C64XX series such as the S3C6400 and S3C6410. | ||
13 | * | ||
14 | * The file does not contain the cpu specific items which are based on | ||
15 | * whichever architecture is selected, it only contains the core of the | ||
16 | * register set. See <mach/regs-fb.h> to get the specifics. | ||
17 | * | ||
18 | * Note, we changed to using regs-fb.h as it avoids any clashes with | ||
19 | * the original regs-lcd.h so out of the way of regs-lcd.h as well as | ||
20 | * indicating the newer block is much more than just an LCD interface. | ||
21 | * | ||
22 | * This program is free software; you can redistribute it and/or modify | ||
23 | * it under the terms of the GNU General Public License version 2 as | ||
24 | * published by the Free Software Foundation. | ||
25 | */ | ||
26 | |||
27 | /* Please do not include this file directly, use <mach/regs-fb.h> to | ||
28 | * ensure all the localised SoC support is included as necessary. | ||
29 | */ | ||
30 | |||
31 | /* VIDCON0 */ | ||
32 | |||
33 | #define VIDCON0 (0x00) | ||
34 | #define VIDCON0_INTERLACE (1 << 29) | ||
35 | #define VIDCON0_VIDOUT_MASK (0x3 << 26) | ||
36 | #define VIDCON0_VIDOUT_SHIFT (26) | ||
37 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) | ||
38 | #define VIDCON0_VIDOUT_TV (0x1 << 26) | ||
39 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) | ||
40 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) | ||
41 | |||
42 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) | ||
43 | #define VIDCON0_L1_DATA_SHIFT (23) | ||
44 | #define VIDCON0_L1_DATA_16BPP (0x0 << 23) | ||
45 | #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) | ||
46 | #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) | ||
47 | #define VIDCON0_L1_DATA_24BPP (0x3 << 23) | ||
48 | #define VIDCON0_L1_DATA_18BPP (0x4 << 23) | ||
49 | #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) | ||
50 | |||
51 | #define VIDCON0_L0_DATA_MASK (0x7 << 20) | ||
52 | #define VIDCON0_L0_DATA_SHIFT (20) | ||
53 | #define VIDCON0_L0_DATA_16BPP (0x0 << 20) | ||
54 | #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) | ||
55 | #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) | ||
56 | #define VIDCON0_L0_DATA_24BPP (0x3 << 20) | ||
57 | #define VIDCON0_L0_DATA_18BPP (0x4 << 20) | ||
58 | #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) | ||
59 | |||
60 | #define VIDCON0_PNRMODE_MASK (0x3 << 17) | ||
61 | #define VIDCON0_PNRMODE_SHIFT (17) | ||
62 | #define VIDCON0_PNRMODE_RGB (0x0 << 17) | ||
63 | #define VIDCON0_PNRMODE_BGR (0x1 << 17) | ||
64 | #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) | ||
65 | #define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) | ||
66 | |||
67 | #define VIDCON0_CLKVALUP (1 << 16) | ||
68 | #define VIDCON0_CLKVAL_F_MASK (0xff << 6) | ||
69 | #define VIDCON0_CLKVAL_F_SHIFT (6) | ||
70 | #define VIDCON0_CLKVAL_F_LIMIT (0xff) | ||
71 | #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) | ||
72 | #define VIDCON0_VLCKFREE (1 << 5) | ||
73 | #define VIDCON0_CLKDIR (1 << 4) | ||
74 | |||
75 | #define VIDCON0_CLKSEL_MASK (0x3 << 2) | ||
76 | #define VIDCON0_CLKSEL_SHIFT (2) | ||
77 | #define VIDCON0_CLKSEL_HCLK (0x0 << 2) | ||
78 | #define VIDCON0_CLKSEL_LCD (0x1 << 2) | ||
79 | #define VIDCON0_CLKSEL_27M (0x3 << 2) | ||
80 | |||
81 | #define VIDCON0_ENVID (1 << 1) | ||
82 | #define VIDCON0_ENVID_F (1 << 0) | ||
83 | |||
84 | #define VIDCON1 (0x04) | ||
85 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) | ||
86 | #define VIDCON1_LINECNT_SHIFT (16) | ||
87 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) | ||
88 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) | ||
89 | #define VIDCON1_VSTATUS_SHIFT (13) | ||
90 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) | ||
91 | #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) | ||
92 | #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) | ||
93 | #define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) | ||
94 | |||
95 | #define VIDCON1_INV_VCLK (1 << 7) | ||
96 | #define VIDCON1_INV_HSYNC (1 << 6) | ||
97 | #define VIDCON1_INV_VSYNC (1 << 5) | ||
98 | #define VIDCON1_INV_VDEN (1 << 4) | ||
99 | |||
100 | /* VIDCON2 */ | ||
101 | |||
102 | #define VIDCON2 (0x08) | ||
103 | #define VIDCON2_EN601 (1 << 23) | ||
104 | #define VIDCON2_TVFMTSEL_SW (1 << 14) | ||
105 | |||
106 | #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) | ||
107 | #define VIDCON2_TVFMTSEL1_SHIFT (12) | ||
108 | #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) | ||
109 | #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) | ||
110 | #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) | ||
111 | |||
112 | #define VIDCON2_ORGYCbCr (1 << 8) | ||
113 | #define VIDCON2_YUVORDCrCb (1 << 7) | ||
114 | |||
115 | /* PRTCON (S3C6410, S5PC100) | ||
116 | * Might not be present in the S3C6410 documentation, | ||
117 | * but tests prove it's there almost for sure; shouldn't hurt in any case. | ||
118 | */ | ||
119 | #define PRTCON (0x0c) | ||
120 | #define PRTCON_PROTECT (1 << 11) | ||
121 | |||
122 | /* VIDTCON0 */ | ||
123 | |||
124 | #define VIDTCON0_VBPDE_MASK (0xff << 24) | ||
125 | #define VIDTCON0_VBPDE_SHIFT (24) | ||
126 | #define VIDTCON0_VBPDE_LIMIT (0xff) | ||
127 | #define VIDTCON0_VBPDE(_x) ((_x) << 24) | ||
128 | |||
129 | #define VIDTCON0_VBPD_MASK (0xff << 16) | ||
130 | #define VIDTCON0_VBPD_SHIFT (16) | ||
131 | #define VIDTCON0_VBPD_LIMIT (0xff) | ||
132 | #define VIDTCON0_VBPD(_x) ((_x) << 16) | ||
133 | |||
134 | #define VIDTCON0_VFPD_MASK (0xff << 8) | ||
135 | #define VIDTCON0_VFPD_SHIFT (8) | ||
136 | #define VIDTCON0_VFPD_LIMIT (0xff) | ||
137 | #define VIDTCON0_VFPD(_x) ((_x) << 8) | ||
138 | |||
139 | #define VIDTCON0_VSPW_MASK (0xff << 0) | ||
140 | #define VIDTCON0_VSPW_SHIFT (0) | ||
141 | #define VIDTCON0_VSPW_LIMIT (0xff) | ||
142 | #define VIDTCON0_VSPW(_x) ((_x) << 0) | ||
143 | |||
144 | /* VIDTCON1 */ | ||
145 | |||
146 | #define VIDTCON1_VFPDE_MASK (0xff << 24) | ||
147 | #define VIDTCON1_VFPDE_SHIFT (24) | ||
148 | #define VIDTCON1_VFPDE_LIMIT (0xff) | ||
149 | #define VIDTCON1_VFPDE(_x) ((_x) << 24) | ||
150 | |||
151 | #define VIDTCON1_HBPD_MASK (0xff << 16) | ||
152 | #define VIDTCON1_HBPD_SHIFT (16) | ||
153 | #define VIDTCON1_HBPD_LIMIT (0xff) | ||
154 | #define VIDTCON1_HBPD(_x) ((_x) << 16) | ||
155 | |||
156 | #define VIDTCON1_HFPD_MASK (0xff << 8) | ||
157 | #define VIDTCON1_HFPD_SHIFT (8) | ||
158 | #define VIDTCON1_HFPD_LIMIT (0xff) | ||
159 | #define VIDTCON1_HFPD(_x) ((_x) << 8) | ||
160 | |||
161 | #define VIDTCON1_HSPW_MASK (0xff << 0) | ||
162 | #define VIDTCON1_HSPW_SHIFT (0) | ||
163 | #define VIDTCON1_HSPW_LIMIT (0xff) | ||
164 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | ||
165 | |||
166 | #define VIDTCON2 (0x18) | ||
167 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) | ||
168 | #define VIDTCON2_LINEVAL_SHIFT (11) | ||
169 | #define VIDTCON2_LINEVAL_LIMIT (0x7ff) | ||
170 | #define VIDTCON2_LINEVAL(_x) ((_x) << 11) | ||
171 | |||
172 | #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) | ||
173 | #define VIDTCON2_HOZVAL_SHIFT (0) | ||
174 | #define VIDTCON2_HOZVAL_LIMIT (0x7ff) | ||
175 | #define VIDTCON2_HOZVAL(_x) ((_x) << 0) | ||
176 | |||
177 | /* WINCONx */ | ||
178 | |||
179 | |||
180 | #define WINCONx_BITSWP (1 << 18) | ||
181 | #define WINCONx_BYTSWP (1 << 17) | ||
182 | #define WINCONx_HAWSWP (1 << 16) | ||
183 | #define WINCONx_WSWP (1 << 15) | ||
184 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) | ||
185 | #define WINCONx_BURSTLEN_SHIFT (9) | ||
186 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) | ||
187 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) | ||
188 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) | ||
189 | |||
190 | #define WINCONx_ENWIN (1 << 0) | ||
191 | #define WINCON0_BPPMODE_MASK (0xf << 2) | ||
192 | #define WINCON0_BPPMODE_SHIFT (2) | ||
193 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) | ||
194 | #define WINCON0_BPPMODE_2BPP (0x1 << 2) | ||
195 | #define WINCON0_BPPMODE_4BPP (0x2 << 2) | ||
196 | #define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) | ||
197 | #define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) | ||
198 | #define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) | ||
199 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) | ||
200 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) | ||
201 | |||
202 | #define WINCON1_BLD_PIX (1 << 6) | ||
203 | |||
204 | #define WINCON1_ALPHA_SEL (1 << 1) | ||
205 | #define WINCON1_BPPMODE_MASK (0xf << 2) | ||
206 | #define WINCON1_BPPMODE_SHIFT (2) | ||
207 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) | ||
208 | #define WINCON1_BPPMODE_2BPP (0x1 << 2) | ||
209 | #define WINCON1_BPPMODE_4BPP (0x2 << 2) | ||
210 | #define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) | ||
211 | #define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) | ||
212 | #define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) | ||
213 | #define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
214 | #define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
215 | #define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) | ||
216 | #define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
217 | #define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) | ||
218 | #define WINCON1_BPPMODE_24BPP_888 (0xb << 2) | ||
219 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) | ||
220 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) | ||
221 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) | ||
222 | |||
223 | /* S5PV210 */ | ||
224 | #define SHADOWCON (0x34) | ||
225 | #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) | ||
226 | /* DMA channels (all windows) */ | ||
227 | #define SHADOWCON_CHx_ENABLE(_win) (1 << (_win)) | ||
228 | /* Local input channels (windows 0-2) */ | ||
229 | #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) | ||
230 | |||
231 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) | ||
232 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) | ||
233 | #define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) | ||
234 | #define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) | ||
235 | |||
236 | #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) | ||
237 | #define VIDOSDxA_TOPLEFT_Y_SHIFT (0) | ||
238 | #define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) | ||
239 | #define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) | ||
240 | |||
241 | #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) | ||
242 | #define VIDOSDxB_BOTRIGHT_X_SHIFT (11) | ||
243 | #define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) | ||
244 | #define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) | ||
245 | |||
246 | #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) | ||
247 | #define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) | ||
248 | #define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) | ||
249 | #define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) | ||
250 | |||
251 | /* For VIDOSD[1..4]C */ | ||
252 | #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) | ||
253 | #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) | ||
254 | #define VIDISD14C_ALPHA0_G_SHIFT (16) | ||
255 | #define VIDISD14C_ALPHA0_G_LIMIT (0xf) | ||
256 | #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) | ||
257 | #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) | ||
258 | #define VIDISD14C_ALPHA0_B_SHIFT (12) | ||
259 | #define VIDISD14C_ALPHA0_B_LIMIT (0xf) | ||
260 | #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) | ||
261 | #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) | ||
262 | #define VIDISD14C_ALPHA1_R_SHIFT (8) | ||
263 | #define VIDISD14C_ALPHA1_R_LIMIT (0xf) | ||
264 | #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) | ||
265 | #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) | ||
266 | #define VIDISD14C_ALPHA1_G_SHIFT (4) | ||
267 | #define VIDISD14C_ALPHA1_G_LIMIT (0xf) | ||
268 | #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) | ||
269 | #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) | ||
270 | #define VIDISD14C_ALPHA1_B_SHIFT (0) | ||
271 | #define VIDISD14C_ALPHA1_B_LIMIT (0xf) | ||
272 | #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) | ||
273 | |||
274 | /* Video buffer addresses */ | ||
275 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | ||
276 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | ||
277 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | ||
278 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | ||
279 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | ||
280 | |||
281 | #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) | ||
282 | #define VIDW_BUF_SIZE_OFFSET_SHIFT (13) | ||
283 | #define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) | ||
284 | #define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) | ||
285 | |||
286 | #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) | ||
287 | #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) | ||
288 | #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) | ||
289 | #define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) | ||
290 | |||
291 | /* Interrupt controls and status */ | ||
292 | |||
293 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) | ||
294 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) | ||
295 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) | ||
296 | #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) | ||
297 | |||
298 | #define VIDINTCON0_INT_SYSMAINCON (1 << 19) | ||
299 | #define VIDINTCON0_INT_SYSSUBCON (1 << 18) | ||
300 | #define VIDINTCON0_INT_I80IFDONE (1 << 17) | ||
301 | |||
302 | #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) | ||
303 | #define VIDINTCON0_FRAMESEL0_SHIFT (15) | ||
304 | #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) | ||
305 | #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) | ||
306 | #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) | ||
307 | #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) | ||
308 | |||
309 | #define VIDINTCON0_FRAMESEL1 (1 << 13) | ||
310 | #define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13) | ||
311 | #define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13) | ||
312 | #define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13) | ||
313 | #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13) | ||
314 | #define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13) | ||
315 | |||
316 | #define VIDINTCON0_INT_FRAME (1 << 12) | ||
317 | #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) | ||
318 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) | ||
319 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) | ||
320 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) | ||
321 | |||
322 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) | ||
323 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) | ||
324 | #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) | ||
325 | #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) | ||
326 | #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) | ||
327 | #define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) | ||
328 | #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) | ||
329 | |||
330 | #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) | ||
331 | #define VIDINTCON0_INT_FIFO_SHIFT (0) | ||
332 | #define VIDINTCON0_INT_ENABLE (1 << 0) | ||
333 | |||
334 | #define VIDINTCON1 (0x134) | ||
335 | #define VIDINTCON1_INT_I180 (1 << 2) | ||
336 | #define VIDINTCON1_INT_FRAME (1 << 1) | ||
337 | #define VIDINTCON1_INT_FIFO (1 << 0) | ||
338 | |||
339 | /* Window colour-key control registers */ | ||
340 | #define WKEYCON (0x140) /* 6410,V210 */ | ||
341 | |||
342 | #define WKEYCON0 (0x00) | ||
343 | #define WKEYCON1 (0x04) | ||
344 | |||
345 | #define WxKEYCON0_KEYBL_EN (1 << 26) | ||
346 | #define WxKEYCON0_KEYEN_F (1 << 25) | ||
347 | #define WxKEYCON0_DIRCON (1 << 24) | ||
348 | #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) | ||
349 | #define WxKEYCON0_COMPKEY_SHIFT (0) | ||
350 | #define WxKEYCON0_COMPKEY_LIMIT (0xffffff) | ||
351 | #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) | ||
352 | #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) | ||
353 | #define WxKEYCON1_COLVAL_SHIFT (0) | ||
354 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) | ||
355 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) | ||
356 | |||
357 | |||
358 | /* Window blanking (MAP) */ | ||
359 | |||
360 | #define WINxMAP_MAP (1 << 24) | ||
361 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) | ||
362 | #define WINxMAP_MAP_COLOUR_SHIFT (0) | ||
363 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) | ||
364 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) | ||
365 | |||
366 | #define WPALCON_PAL_UPDATE (1 << 9) | ||
367 | #define WPALCON_W1PAL_MASK (0x7 << 3) | ||
368 | #define WPALCON_W1PAL_SHIFT (3) | ||
369 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) | ||
370 | #define WPALCON_W1PAL_24BPP (0x1 << 3) | ||
371 | #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) | ||
372 | #define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) | ||
373 | #define WPALCON_W1PAL_18BPP (0x4 << 3) | ||
374 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) | ||
375 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) | ||
376 | |||
377 | #define WPALCON_W0PAL_MASK (0x7 << 0) | ||
378 | #define WPALCON_W0PAL_SHIFT (0) | ||
379 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) | ||
380 | #define WPALCON_W0PAL_24BPP (0x1 << 0) | ||
381 | #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) | ||
382 | #define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) | ||
383 | #define WPALCON_W0PAL_18BPP (0x4 << 0) | ||
384 | #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) | ||
385 | #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) | ||
386 | |||
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h new file mode 100644 index 00000000000..dc90f5ede88 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h | |||
@@ -0,0 +1,379 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C - USB2.0 Highspeed/OtG device block registers | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H | ||
16 | #define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__ | ||
17 | |||
18 | #define S3C_HSOTG_REG(x) (x) | ||
19 | |||
20 | #define S3C_GOTGCTL S3C_HSOTG_REG(0x000) | ||
21 | #define S3C_GOTGCTL_BSESVLD (1 << 19) | ||
22 | #define S3C_GOTGCTL_ASESVLD (1 << 18) | ||
23 | #define S3C_GOTGCTL_DBNC_SHORT (1 << 17) | ||
24 | #define S3C_GOTGCTL_CONID_B (1 << 16) | ||
25 | #define S3C_GOTGCTL_DEVHNPEN (1 << 11) | ||
26 | #define S3C_GOTGCTL_HSSETHNPEN (1 << 10) | ||
27 | #define S3C_GOTGCTL_HNPREQ (1 << 9) | ||
28 | #define S3C_GOTGCTL_HSTNEGSCS (1 << 8) | ||
29 | #define S3C_GOTGCTL_SESREQ (1 << 1) | ||
30 | #define S3C_GOTGCTL_SESREQSCS (1 << 0) | ||
31 | |||
32 | #define S3C_GOTGINT S3C_HSOTG_REG(0x004) | ||
33 | #define S3C_GOTGINT_DbnceDone (1 << 19) | ||
34 | #define S3C_GOTGINT_ADevTOUTChg (1 << 18) | ||
35 | #define S3C_GOTGINT_HstNegDet (1 << 17) | ||
36 | #define S3C_GOTGINT_HstnegSucStsChng (1 << 9) | ||
37 | #define S3C_GOTGINT_SesReqSucStsChng (1 << 8) | ||
38 | #define S3C_GOTGINT_SesEndDet (1 << 2) | ||
39 | |||
40 | #define S3C_GAHBCFG S3C_HSOTG_REG(0x008) | ||
41 | #define S3C_GAHBCFG_PTxFEmpLvl (1 << 8) | ||
42 | #define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7) | ||
43 | #define S3C_GAHBCFG_DMAEn (1 << 5) | ||
44 | #define S3C_GAHBCFG_HBstLen_MASK (0xf << 1) | ||
45 | #define S3C_GAHBCFG_HBstLen_SHIFT (1) | ||
46 | #define S3C_GAHBCFG_HBstLen_Single (0x0 << 1) | ||
47 | #define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1) | ||
48 | #define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1) | ||
49 | #define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1) | ||
50 | #define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1) | ||
51 | #define S3C_GAHBCFG_GlblIntrEn (1 << 0) | ||
52 | |||
53 | #define S3C_GUSBCFG S3C_HSOTG_REG(0x00C) | ||
54 | #define S3C_GUSBCFG_PHYLPClkSel (1 << 15) | ||
55 | #define S3C_GUSBCFG_HNPCap (1 << 9) | ||
56 | #define S3C_GUSBCFG_SRPCap (1 << 8) | ||
57 | #define S3C_GUSBCFG_PHYIf16 (1 << 3) | ||
58 | #define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0) | ||
59 | #define S3C_GUSBCFG_TOutCal_SHIFT (0) | ||
60 | #define S3C_GUSBCFG_TOutCal_LIMIT (0x7) | ||
61 | #define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0) | ||
62 | |||
63 | #define S3C_GRSTCTL S3C_HSOTG_REG(0x010) | ||
64 | |||
65 | #define S3C_GRSTCTL_AHBIdle (1 << 31) | ||
66 | #define S3C_GRSTCTL_DMAReq (1 << 30) | ||
67 | #define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6) | ||
68 | #define S3C_GRSTCTL_TxFNum_SHIFT (6) | ||
69 | #define S3C_GRSTCTL_TxFNum_LIMIT (0x1f) | ||
70 | #define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6) | ||
71 | #define S3C_GRSTCTL_TxFFlsh (1 << 5) | ||
72 | #define S3C_GRSTCTL_RxFFlsh (1 << 4) | ||
73 | #define S3C_GRSTCTL_INTknQFlsh (1 << 3) | ||
74 | #define S3C_GRSTCTL_FrmCntrRst (1 << 2) | ||
75 | #define S3C_GRSTCTL_HSftRst (1 << 1) | ||
76 | #define S3C_GRSTCTL_CSftRst (1 << 0) | ||
77 | |||
78 | #define S3C_GINTSTS S3C_HSOTG_REG(0x014) | ||
79 | #define S3C_GINTMSK S3C_HSOTG_REG(0x018) | ||
80 | |||
81 | #define S3C_GINTSTS_WkUpInt (1 << 31) | ||
82 | #define S3C_GINTSTS_SessReqInt (1 << 30) | ||
83 | #define S3C_GINTSTS_DisconnInt (1 << 29) | ||
84 | #define S3C_GINTSTS_ConIDStsChng (1 << 28) | ||
85 | #define S3C_GINTSTS_PTxFEmp (1 << 26) | ||
86 | #define S3C_GINTSTS_HChInt (1 << 25) | ||
87 | #define S3C_GINTSTS_PrtInt (1 << 24) | ||
88 | #define S3C_GINTSTS_FetSusp (1 << 22) | ||
89 | #define S3C_GINTSTS_incompIP (1 << 21) | ||
90 | #define S3C_GINTSTS_IncomplSOIN (1 << 20) | ||
91 | #define S3C_GINTSTS_OEPInt (1 << 19) | ||
92 | #define S3C_GINTSTS_IEPInt (1 << 18) | ||
93 | #define S3C_GINTSTS_EPMis (1 << 17) | ||
94 | #define S3C_GINTSTS_EOPF (1 << 15) | ||
95 | #define S3C_GINTSTS_ISOutDrop (1 << 14) | ||
96 | #define S3C_GINTSTS_EnumDone (1 << 13) | ||
97 | #define S3C_GINTSTS_USBRst (1 << 12) | ||
98 | #define S3C_GINTSTS_USBSusp (1 << 11) | ||
99 | #define S3C_GINTSTS_ErlySusp (1 << 10) | ||
100 | #define S3C_GINTSTS_GOUTNakEff (1 << 7) | ||
101 | #define S3C_GINTSTS_GINNakEff (1 << 6) | ||
102 | #define S3C_GINTSTS_NPTxFEmp (1 << 5) | ||
103 | #define S3C_GINTSTS_RxFLvl (1 << 4) | ||
104 | #define S3C_GINTSTS_SOF (1 << 3) | ||
105 | #define S3C_GINTSTS_OTGInt (1 << 2) | ||
106 | #define S3C_GINTSTS_ModeMis (1 << 1) | ||
107 | #define S3C_GINTSTS_CurMod_Host (1 << 0) | ||
108 | |||
109 | #define S3C_GRXSTSR S3C_HSOTG_REG(0x01C) | ||
110 | #define S3C_GRXSTSP S3C_HSOTG_REG(0x020) | ||
111 | |||
112 | #define S3C_GRXSTS_FN_MASK (0x7f << 25) | ||
113 | #define S3C_GRXSTS_FN_SHIFT (25) | ||
114 | |||
115 | #define S3C_GRXSTS_PktSts_MASK (0xf << 17) | ||
116 | #define S3C_GRXSTS_PktSts_SHIFT (17) | ||
117 | #define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) | ||
118 | #define S3C_GRXSTS_PktSts_OutRX (0x2 << 17) | ||
119 | #define S3C_GRXSTS_PktSts_OutDone (0x3 << 17) | ||
120 | #define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17) | ||
121 | #define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17) | ||
122 | |||
123 | #define S3C_GRXSTS_DPID_MASK (0x3 << 15) | ||
124 | #define S3C_GRXSTS_DPID_SHIFT (15) | ||
125 | #define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4) | ||
126 | #define S3C_GRXSTS_ByteCnt_SHIFT (4) | ||
127 | #define S3C_GRXSTS_EPNum_MASK (0xf << 0) | ||
128 | #define S3C_GRXSTS_EPNum_SHIFT (0) | ||
129 | |||
130 | #define S3C_GRXFSIZ S3C_HSOTG_REG(0x024) | ||
131 | |||
132 | #define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028) | ||
133 | |||
134 | #define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) | ||
135 | #define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16) | ||
136 | #define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) | ||
137 | #define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) | ||
138 | #define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) | ||
139 | #define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0) | ||
140 | #define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) | ||
141 | #define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) | ||
142 | |||
143 | #define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C) | ||
144 | |||
145 | #define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24) | ||
146 | #define S3C_GNPTXSTS_NPtxQTop_SHIFT (24) | ||
147 | |||
148 | #define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) | ||
149 | #define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16) | ||
150 | #define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) | ||
151 | |||
152 | #define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) | ||
153 | #define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0) | ||
154 | #define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) | ||
155 | |||
156 | |||
157 | #define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100) | ||
158 | |||
159 | #define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4)) | ||
160 | |||
161 | #define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) | ||
162 | #define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16) | ||
163 | #define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) | ||
164 | #define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff) | ||
165 | #define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) | ||
166 | |||
167 | #define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) | ||
168 | #define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0) | ||
169 | |||
170 | /* Device mode registers */ | ||
171 | #define S3C_DCFG S3C_HSOTG_REG(0x800) | ||
172 | |||
173 | #define S3C_DCFG_EPMisCnt_MASK (0x1f << 18) | ||
174 | #define S3C_DCFG_EPMisCnt_SHIFT (18) | ||
175 | #define S3C_DCFG_EPMisCnt_LIMIT (0x1f) | ||
176 | #define S3C_DCFG_EPMisCnt(_x) ((_x) << 18) | ||
177 | |||
178 | #define S3C_DCFG_PerFrInt_MASK (0x3 << 11) | ||
179 | #define S3C_DCFG_PerFrInt_SHIFT (11) | ||
180 | #define S3C_DCFG_PerFrInt_LIMIT (0x3) | ||
181 | #define S3C_DCFG_PerFrInt(_x) ((_x) << 11) | ||
182 | |||
183 | #define S3C_DCFG_DevAddr_MASK (0x7f << 4) | ||
184 | #define S3C_DCFG_DevAddr_SHIFT (4) | ||
185 | #define S3C_DCFG_DevAddr_LIMIT (0x7f) | ||
186 | #define S3C_DCFG_DevAddr(_x) ((_x) << 4) | ||
187 | |||
188 | #define S3C_DCFG_NZStsOUTHShk (1 << 2) | ||
189 | |||
190 | #define S3C_DCFG_DevSpd_MASK (0x3 << 0) | ||
191 | #define S3C_DCFG_DevSpd_SHIFT (0) | ||
192 | #define S3C_DCFG_DevSpd_HS (0x0 << 0) | ||
193 | #define S3C_DCFG_DevSpd_FS (0x1 << 0) | ||
194 | #define S3C_DCFG_DevSpd_LS (0x2 << 0) | ||
195 | #define S3C_DCFG_DevSpd_FS48 (0x3 << 0) | ||
196 | |||
197 | #define S3C_DCTL S3C_HSOTG_REG(0x804) | ||
198 | |||
199 | #define S3C_DCTL_PWROnPrgDone (1 << 11) | ||
200 | #define S3C_DCTL_CGOUTNak (1 << 10) | ||
201 | #define S3C_DCTL_SGOUTNak (1 << 9) | ||
202 | #define S3C_DCTL_CGNPInNAK (1 << 8) | ||
203 | #define S3C_DCTL_SGNPInNAK (1 << 7) | ||
204 | #define S3C_DCTL_TstCtl_MASK (0x7 << 4) | ||
205 | #define S3C_DCTL_TstCtl_SHIFT (4) | ||
206 | #define S3C_DCTL_GOUTNakSts (1 << 3) | ||
207 | #define S3C_DCTL_GNPINNakSts (1 << 2) | ||
208 | #define S3C_DCTL_SftDiscon (1 << 1) | ||
209 | #define S3C_DCTL_RmtWkUpSig (1 << 0) | ||
210 | |||
211 | #define S3C_DSTS S3C_HSOTG_REG(0x808) | ||
212 | |||
213 | #define S3C_DSTS_SOFFN_MASK (0x3fff << 8) | ||
214 | #define S3C_DSTS_SOFFN_SHIFT (8) | ||
215 | #define S3C_DSTS_SOFFN_LIMIT (0x3fff) | ||
216 | #define S3C_DSTS_SOFFN(_x) ((_x) << 8) | ||
217 | #define S3C_DSTS_ErraticErr (1 << 3) | ||
218 | #define S3C_DSTS_EnumSpd_MASK (0x3 << 1) | ||
219 | #define S3C_DSTS_EnumSpd_SHIFT (1) | ||
220 | #define S3C_DSTS_EnumSpd_HS (0x0 << 1) | ||
221 | #define S3C_DSTS_EnumSpd_FS (0x1 << 1) | ||
222 | #define S3C_DSTS_EnumSpd_LS (0x2 << 1) | ||
223 | #define S3C_DSTS_EnumSpd_FS48 (0x3 << 1) | ||
224 | |||
225 | #define S3C_DSTS_SuspSts (1 << 0) | ||
226 | |||
227 | #define S3C_DIEPMSK S3C_HSOTG_REG(0x810) | ||
228 | |||
229 | #define S3C_DIEPMSK_TxFIFOEmpty (1 << 7) | ||
230 | #define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) | ||
231 | #define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) | ||
232 | #define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) | ||
233 | #define S3C_DIEPMSK_TimeOUTMsk (1 << 3) | ||
234 | #define S3C_DIEPMSK_AHBErrMsk (1 << 2) | ||
235 | #define S3C_DIEPMSK_EPDisbldMsk (1 << 1) | ||
236 | #define S3C_DIEPMSK_XferComplMsk (1 << 0) | ||
237 | |||
238 | #define S3C_DOEPMSK S3C_HSOTG_REG(0x814) | ||
239 | |||
240 | #define S3C_DOEPMSK_Back2BackSetup (1 << 6) | ||
241 | #define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4) | ||
242 | #define S3C_DOEPMSK_SetupMsk (1 << 3) | ||
243 | #define S3C_DOEPMSK_AHBErrMsk (1 << 2) | ||
244 | #define S3C_DOEPMSK_EPDisbldMsk (1 << 1) | ||
245 | #define S3C_DOEPMSK_XferComplMsk (1 << 0) | ||
246 | |||
247 | #define S3C_DAINT S3C_HSOTG_REG(0x818) | ||
248 | #define S3C_DAINTMSK S3C_HSOTG_REG(0x81C) | ||
249 | |||
250 | #define S3C_DAINT_OutEP_SHIFT (16) | ||
251 | #define S3C_DAINT_OutEP(x) (1 << ((x) + 16)) | ||
252 | #define S3C_DAINT_InEP(x) (1 << (x)) | ||
253 | |||
254 | #define S3C_DTKNQR1 S3C_HSOTG_REG(0x820) | ||
255 | #define S3C_DTKNQR2 S3C_HSOTG_REG(0x824) | ||
256 | #define S3C_DTKNQR3 S3C_HSOTG_REG(0x830) | ||
257 | #define S3C_DTKNQR4 S3C_HSOTG_REG(0x834) | ||
258 | |||
259 | #define S3C_DVBUSDIS S3C_HSOTG_REG(0x828) | ||
260 | #define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C) | ||
261 | |||
262 | #define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900) | ||
263 | #define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00) | ||
264 | #define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20)) | ||
265 | #define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20)) | ||
266 | |||
267 | /* EP0 specialness: | ||
268 | * bits[29..28] - reserved (no SetD0PID, SetD1PID) | ||
269 | * bits[25..22] - should always be zero, this isn't a periodic endpoint | ||
270 | * bits[10..0] - MPS setting differenct for EP0 | ||
271 | */ | ||
272 | #define S3C_D0EPCTL_MPS_MASK (0x3 << 0) | ||
273 | #define S3C_D0EPCTL_MPS_SHIFT (0) | ||
274 | #define S3C_D0EPCTL_MPS_64 (0x0 << 0) | ||
275 | #define S3C_D0EPCTL_MPS_32 (0x1 << 0) | ||
276 | #define S3C_D0EPCTL_MPS_16 (0x2 << 0) | ||
277 | #define S3C_D0EPCTL_MPS_8 (0x3 << 0) | ||
278 | |||
279 | #define S3C_DxEPCTL_EPEna (1 << 31) | ||
280 | #define S3C_DxEPCTL_EPDis (1 << 30) | ||
281 | #define S3C_DxEPCTL_SetD1PID (1 << 29) | ||
282 | #define S3C_DxEPCTL_SetOddFr (1 << 29) | ||
283 | #define S3C_DxEPCTL_SetD0PID (1 << 28) | ||
284 | #define S3C_DxEPCTL_SetEvenFr (1 << 28) | ||
285 | #define S3C_DxEPCTL_SNAK (1 << 27) | ||
286 | #define S3C_DxEPCTL_CNAK (1 << 26) | ||
287 | #define S3C_DxEPCTL_TxFNum_MASK (0xf << 22) | ||
288 | #define S3C_DxEPCTL_TxFNum_SHIFT (22) | ||
289 | #define S3C_DxEPCTL_TxFNum_LIMIT (0xf) | ||
290 | #define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22) | ||
291 | |||
292 | #define S3C_DxEPCTL_Stall (1 << 21) | ||
293 | #define S3C_DxEPCTL_Snp (1 << 20) | ||
294 | #define S3C_DxEPCTL_EPType_MASK (0x3 << 18) | ||
295 | #define S3C_DxEPCTL_EPType_SHIFT (18) | ||
296 | #define S3C_DxEPCTL_EPType_Control (0x0 << 18) | ||
297 | #define S3C_DxEPCTL_EPType_Iso (0x1 << 18) | ||
298 | #define S3C_DxEPCTL_EPType_Bulk (0x2 << 18) | ||
299 | #define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18) | ||
300 | |||
301 | #define S3C_DxEPCTL_NAKsts (1 << 17) | ||
302 | #define S3C_DxEPCTL_DPID (1 << 16) | ||
303 | #define S3C_DxEPCTL_EOFrNum (1 << 16) | ||
304 | #define S3C_DxEPCTL_USBActEp (1 << 15) | ||
305 | #define S3C_DxEPCTL_NextEp_MASK (0xf << 11) | ||
306 | #define S3C_DxEPCTL_NextEp_SHIFT (11) | ||
307 | #define S3C_DxEPCTL_NextEp_LIMIT (0xf) | ||
308 | #define S3C_DxEPCTL_NextEp(_x) ((_x) << 11) | ||
309 | |||
310 | #define S3C_DxEPCTL_MPS_MASK (0x7ff << 0) | ||
311 | #define S3C_DxEPCTL_MPS_SHIFT (0) | ||
312 | #define S3C_DxEPCTL_MPS_LIMIT (0x7ff) | ||
313 | #define S3C_DxEPCTL_MPS(_x) ((_x) << 0) | ||
314 | |||
315 | #define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20)) | ||
316 | #define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20)) | ||
317 | |||
318 | #define S3C_DxEPINT_INEPNakEff (1 << 6) | ||
319 | #define S3C_DxEPINT_Back2BackSetup (1 << 6) | ||
320 | #define S3C_DxEPINT_INTknEPMis (1 << 5) | ||
321 | #define S3C_DxEPINT_INTknTXFEmp (1 << 4) | ||
322 | #define S3C_DxEPINT_OUTTknEPdis (1 << 4) | ||
323 | #define S3C_DxEPINT_Timeout (1 << 3) | ||
324 | #define S3C_DxEPINT_Setup (1 << 3) | ||
325 | #define S3C_DxEPINT_AHBErr (1 << 2) | ||
326 | #define S3C_DxEPINT_EPDisbld (1 << 1) | ||
327 | #define S3C_DxEPINT_XferCompl (1 << 0) | ||
328 | |||
329 | #define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910) | ||
330 | |||
331 | #define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19) | ||
332 | #define S3C_DIEPTSIZ0_PktCnt_SHIFT (19) | ||
333 | #define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3) | ||
334 | #define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19) | ||
335 | |||
336 | #define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0) | ||
337 | #define S3C_DIEPTSIZ0_XferSize_SHIFT (0) | ||
338 | #define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f) | ||
339 | #define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0) | ||
340 | |||
341 | |||
342 | #define DOEPTSIZ0 S3C_HSOTG_REG(0xB10) | ||
343 | #define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) | ||
344 | #define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29) | ||
345 | #define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3) | ||
346 | #define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) | ||
347 | |||
348 | #define S3C_DOEPTSIZ0_PktCnt (1 << 19) | ||
349 | #define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0) | ||
350 | #define S3C_DOEPTSIZ0_XferSize_SHIFT (0) | ||
351 | |||
352 | #define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20)) | ||
353 | #define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20)) | ||
354 | |||
355 | #define S3C_DxEPTSIZ_MC_MASK (0x3 << 29) | ||
356 | #define S3C_DxEPTSIZ_MC_SHIFT (29) | ||
357 | #define S3C_DxEPTSIZ_MC_LIMIT (0x3) | ||
358 | #define S3C_DxEPTSIZ_MC(_x) ((_x) << 29) | ||
359 | |||
360 | #define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19) | ||
361 | #define S3C_DxEPTSIZ_PktCnt_SHIFT (19) | ||
362 | #define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) | ||
363 | #define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff) | ||
364 | #define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19) | ||
365 | |||
366 | #define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0) | ||
367 | #define S3C_DxEPTSIZ_XferSize_SHIFT (0) | ||
368 | #define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) | ||
369 | #define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff) | ||
370 | #define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0) | ||
371 | |||
372 | |||
373 | #define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) | ||
374 | #define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) | ||
375 | #define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20)) | ||
376 | |||
377 | #define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) | ||
378 | |||
379 | #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h new file mode 100644 index 00000000000..81074421312 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h | |||
@@ -0,0 +1,98 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | */ | ||
10 | |||
11 | #ifndef __S3C_DMA_PL330_H_ | ||
12 | #define __S3C_DMA_PL330_H_ | ||
13 | |||
14 | #define S3C2410_DMAF_AUTOSTART (1 << 0) | ||
15 | #define S3C2410_DMAF_CIRCULAR (1 << 1) | ||
16 | |||
17 | /* | ||
18 | * PL330 can assign any channel to communicate with | ||
19 | * any of the peripherals attched to the DMAC. | ||
20 | * For the sake of consistency across client drivers, | ||
21 | * We keep the channel names unchanged and only add | ||
22 | * missing peripherals are added. | ||
23 | * Order is not important since S3C PL330 API driver | ||
24 | * use these just as IDs. | ||
25 | */ | ||
26 | enum dma_ch { | ||
27 | DMACH_UART0_RX, | ||
28 | DMACH_UART0_TX, | ||
29 | DMACH_UART1_RX, | ||
30 | DMACH_UART1_TX, | ||
31 | DMACH_UART2_RX, | ||
32 | DMACH_UART2_TX, | ||
33 | DMACH_UART3_RX, | ||
34 | DMACH_UART3_TX, | ||
35 | DMACH_UART4_RX, | ||
36 | DMACH_UART4_TX, | ||
37 | DMACH_UART5_RX, | ||
38 | DMACH_UART5_TX, | ||
39 | DMACH_USI_RX, | ||
40 | DMACH_USI_TX, | ||
41 | DMACH_IRDA, | ||
42 | DMACH_I2S0_RX, | ||
43 | DMACH_I2S0_TX, | ||
44 | DMACH_I2S0S_TX, | ||
45 | DMACH_I2S1_RX, | ||
46 | DMACH_I2S1_TX, | ||
47 | DMACH_I2S2_RX, | ||
48 | DMACH_I2S2_TX, | ||
49 | DMACH_SPI0_RX, | ||
50 | DMACH_SPI0_TX, | ||
51 | DMACH_SPI1_RX, | ||
52 | DMACH_SPI1_TX, | ||
53 | DMACH_SPI2_RX, | ||
54 | DMACH_SPI2_TX, | ||
55 | DMACH_AC97_MICIN, | ||
56 | DMACH_AC97_PCMIN, | ||
57 | DMACH_AC97_PCMOUT, | ||
58 | DMACH_EXTERNAL, | ||
59 | DMACH_PWM, | ||
60 | DMACH_SPDIF, | ||
61 | DMACH_HSI_RX, | ||
62 | DMACH_HSI_TX, | ||
63 | DMACH_PCM0_TX, | ||
64 | DMACH_PCM0_RX, | ||
65 | DMACH_PCM1_TX, | ||
66 | DMACH_PCM1_RX, | ||
67 | DMACH_PCM2_TX, | ||
68 | DMACH_PCM2_RX, | ||
69 | DMACH_MSM_REQ3, | ||
70 | DMACH_MSM_REQ2, | ||
71 | DMACH_MSM_REQ1, | ||
72 | DMACH_MSM_REQ0, | ||
73 | DMACH_SLIMBUS0_RX, | ||
74 | DMACH_SLIMBUS0_TX, | ||
75 | DMACH_SLIMBUS0AUX_RX, | ||
76 | DMACH_SLIMBUS0AUX_TX, | ||
77 | DMACH_SLIMBUS1_RX, | ||
78 | DMACH_SLIMBUS1_TX, | ||
79 | DMACH_SLIMBUS2_RX, | ||
80 | DMACH_SLIMBUS2_TX, | ||
81 | DMACH_SLIMBUS3_RX, | ||
82 | DMACH_SLIMBUS3_TX, | ||
83 | DMACH_SLIMBUS4_RX, | ||
84 | DMACH_SLIMBUS4_TX, | ||
85 | DMACH_SLIMBUS5_RX, | ||
86 | DMACH_SLIMBUS5_TX, | ||
87 | /* END Marker, also used to denote a reserved channel */ | ||
88 | DMACH_MAX, | ||
89 | }; | ||
90 | |||
91 | static inline bool s3c_dma_has_circular(void) | ||
92 | { | ||
93 | return true; | ||
94 | } | ||
95 | |||
96 | #include <plat/dma.h> | ||
97 | |||
98 | #endif /* __S3C_DMA_PL330_H_ */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h new file mode 100644 index 00000000000..bf5e2a9d408 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h | ||
2 | * | ||
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef __S3C_PL330_PDATA_H | ||
13 | #define __S3C_PL330_PDATA_H | ||
14 | |||
15 | #include <plat/s3c-dma-pl330.h> | ||
16 | |||
17 | /* | ||
18 | * Every PL330 DMAC has max 32 peripheral interfaces, | ||
19 | * of which some may be not be really used in your | ||
20 | * DMAC's configuration. | ||
21 | * Populate this array of 32 peri i/fs with relevant | ||
22 | * channel IDs for used peri i/f and DMACH_MAX for | ||
23 | * those unused. | ||
24 | * | ||
25 | * The platforms just need to provide this info | ||
26 | * to the S3C DMA API driver for PL330. | ||
27 | */ | ||
28 | struct s3c_pl330_platdata { | ||
29 | enum dma_ch peri[32]; | ||
30 | }; | ||
31 | |||
32 | #endif /* __S3C_PL330_PDATA_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h new file mode 100644 index 00000000000..4c16fa3621b --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | |||
@@ -0,0 +1,75 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | ||
2 | * | ||
3 | * Copyright (C) 2009 Samsung Electronics Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __S3C64XX_PLAT_SPI_H | ||
12 | #define __S3C64XX_PLAT_SPI_H | ||
13 | |||
14 | /** | ||
15 | * struct s3c64xx_spi_csinfo - ChipSelect description | ||
16 | * @fb_delay: Slave specific feedback delay. | ||
17 | * Refer to FB_CLK_SEL register definition in SPI chapter. | ||
18 | * @line: Custom 'identity' of the CS line. | ||
19 | * @set_level: CS line control. | ||
20 | * | ||
21 | * This is per SPI-Slave Chipselect information. | ||
22 | * Allocate and initialize one in machine init code and make the | ||
23 | * spi_board_info.controller_data point to it. | ||
24 | */ | ||
25 | struct s3c64xx_spi_csinfo { | ||
26 | u8 fb_delay; | ||
27 | unsigned line; | ||
28 | void (*set_level)(unsigned line_id, int lvl); | ||
29 | }; | ||
30 | |||
31 | /** | ||
32 | * struct s3c64xx_spi_info - SPI Controller defining structure | ||
33 | * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. | ||
34 | * @src_clk_name: Platform name of the corresponding clock. | ||
35 | * @clk_from_cmu: If the SPI clock/prescalar control block is present | ||
36 | * by the platform's clock-management-unit and not in SPI controller. | ||
37 | * @num_cs: Number of CS this controller emulates. | ||
38 | * @cfg_gpio: Configure pins for this SPI controller. | ||
39 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 | ||
40 | * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number | ||
41 | * @high_speed: If the controller supports HIGH_SPEED_EN bit | ||
42 | * @tx_st_done: Depends on tx fifo_lvl field | ||
43 | */ | ||
44 | struct s3c64xx_spi_info { | ||
45 | int src_clk_nr; | ||
46 | char *src_clk_name; | ||
47 | bool clk_from_cmu; | ||
48 | |||
49 | int num_cs; | ||
50 | |||
51 | int (*cfg_gpio)(struct platform_device *pdev); | ||
52 | |||
53 | /* Following two fields are for future compatibility */ | ||
54 | int fifo_lvl_mask; | ||
55 | int rx_lvl_offset; | ||
56 | int high_speed; | ||
57 | int tx_st_done; | ||
58 | }; | ||
59 | |||
60 | /** | ||
61 | * s3c64xx_spi_set_info - SPI Controller configure callback by the board | ||
62 | * initialization code. | ||
63 | * @cntrlr: SPI controller number the configuration is for. | ||
64 | * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. | ||
65 | * @num_cs: Number of elements in the 'cs' array. | ||
66 | * | ||
67 | * Call this from machine init code for each SPI Controller that | ||
68 | * has some chips attached to it. | ||
69 | */ | ||
70 | extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
71 | extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
72 | extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
73 | extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
74 | |||
75 | #endif /* __S3C64XX_PLAT_SPI_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/ts.h b/arch/arm/plat-samsung/include/plat/ts.h new file mode 100644 index 00000000000..26fdb22e0fc --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/ts.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/ts.h | ||
2 | * | ||
3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASM_ARM_TS_H | ||
11 | #define __ASM_ARM_TS_H | ||
12 | |||
13 | struct s3c2410_ts_mach_info { | ||
14 | int delay; | ||
15 | int presc; | ||
16 | int oversampling_shift; | ||
17 | void (*cfg_gpio)(struct platform_device *dev); | ||
18 | }; | ||
19 | |||
20 | extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *); | ||
21 | |||
22 | /* defined by architecture to configure gpio */ | ||
23 | extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev); | ||
24 | |||
25 | #endif /* __ASM_ARM_TS_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h new file mode 100644 index 00000000000..a22a4f2eea9 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/udc-hs.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/udc-hs.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C USB2.0 High-speed / OtG platform information | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | enum s3c_hsotg_dmamode { | ||
16 | S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ | ||
17 | S3C_HSOTG_DMA_ONLY, /* always use DMA */ | ||
18 | S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ | ||
19 | }; | ||
20 | |||
21 | /** | ||
22 | * struct s3c_hsotg_plat - platform data for high-speed otg/udc | ||
23 | * @dma: Whether to use DMA or not. | ||
24 | * @is_osc: The clock source is an oscillator, not a crystal | ||
25 | */ | ||
26 | struct s3c_hsotg_plat { | ||
27 | enum s3c_hsotg_dmamode dma; | ||
28 | unsigned int is_osc : 1; | ||
29 | }; | ||
diff --git a/arch/arm/plat-samsung/include/plat/usb-control.h b/arch/arm/plat-samsung/include/plat/usb-control.h new file mode 100644 index 00000000000..7fa1fbefc3f --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/usb-control.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* arch/arm/plat-samsung/include/plat/usb-control.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C - USB host port information | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_USBCONTROL_H | ||
14 | #define __ASM_ARCH_USBCONTROL_H | ||
15 | |||
16 | #define S3C_HCDFLG_USED (1) | ||
17 | |||
18 | struct s3c2410_hcd_port { | ||
19 | unsigned char flags; | ||
20 | unsigned char power; | ||
21 | unsigned char oc_status; | ||
22 | unsigned char oc_changed; | ||
23 | }; | ||
24 | |||
25 | struct s3c2410_hcd_info { | ||
26 | struct usb_hcd *hcd; | ||
27 | struct s3c2410_hcd_port port[2]; | ||
28 | |||
29 | void (*power_control)(int port, int to); | ||
30 | void (*enable_oc)(struct s3c2410_hcd_info *, int on); | ||
31 | void (*report_oc)(struct s3c2410_hcd_info *, int ports); | ||
32 | }; | ||
33 | |||
34 | static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports) | ||
35 | { | ||
36 | if (info->report_oc != NULL) { | ||
37 | (info->report_oc)(info, ports); | ||
38 | } | ||
39 | } | ||
40 | |||
41 | extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info); | ||
42 | |||
43 | #endif /*__ASM_ARCH_USBCONTROL_H */ | ||