diff options
Diffstat (limited to 'arch/arm/plat-s5p/include/plat/pll.h')
-rw-r--r-- | arch/arm/plat-s5p/include/plat/pll.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index bf28fadee7a..8b24b366c65 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h | |||
@@ -46,15 +46,24 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, | |||
46 | return (unsigned long)fvco; | 46 | return (unsigned long)fvco; |
47 | } | 47 | } |
48 | 48 | ||
49 | #define PLL46XX_KDIV_MASK (0xFFFF) | 49 | /* CON0 bit-fields */ |
50 | #define PLL4650C_KDIV_MASK (0xFFF) | ||
51 | #define PLL46XX_MDIV_MASK (0x1FF) | 50 | #define PLL46XX_MDIV_MASK (0x1FF) |
52 | #define PLL46XX_PDIV_MASK (0x3F) | 51 | #define PLL46XX_PDIV_MASK (0x3F) |
53 | #define PLL46XX_SDIV_MASK (0x7) | 52 | #define PLL46XX_SDIV_MASK (0x7) |
53 | #define PLL46XX_LOCKED_SHIFT (29) | ||
54 | #define PLL46XX_MDIV_SHIFT (16) | 54 | #define PLL46XX_MDIV_SHIFT (16) |
55 | #define PLL46XX_PDIV_SHIFT (8) | 55 | #define PLL46XX_PDIV_SHIFT (8) |
56 | #define PLL46XX_SDIV_SHIFT (0) | 56 | #define PLL46XX_SDIV_SHIFT (0) |
57 | 57 | ||
58 | /* CON1 bit-fields */ | ||
59 | #define PLL46XX_MRR_MASK (0x1F) | ||
60 | #define PLL46XX_MFR_MASK (0x3F) | ||
61 | #define PLL46XX_KDIV_MASK (0xFFFF) | ||
62 | #define PLL4650C_KDIV_MASK (0xFFF) | ||
63 | #define PLL46XX_MRR_SHIFT (24) | ||
64 | #define PLL46XX_MFR_SHIFT (16) | ||
65 | #define PLL46XX_KDIV_SHIFT (0) | ||
66 | |||
58 | enum pll46xx_type_t { | 67 | enum pll46xx_type_t { |
59 | pll_4600, | 68 | pll_4600, |
60 | pll_4650, | 69 | pll_4650, |
@@ -98,6 +107,7 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, | |||
98 | #define PLL90XX_PDIV_MASK (0x3F) | 107 | #define PLL90XX_PDIV_MASK (0x3F) |
99 | #define PLL90XX_SDIV_MASK (0x7) | 108 | #define PLL90XX_SDIV_MASK (0x7) |
100 | #define PLL90XX_KDIV_MASK (0xffff) | 109 | #define PLL90XX_KDIV_MASK (0xffff) |
110 | #define PLL90XX_LOCKED_SHIFT (29) | ||
101 | #define PLL90XX_MDIV_SHIFT (16) | 111 | #define PLL90XX_MDIV_SHIFT (16) |
102 | #define PLL90XX_PDIV_SHIFT (8) | 112 | #define PLL90XX_PDIV_SHIFT (8) |
103 | #define PLL90XX_SDIV_SHIFT (0) | 113 | #define PLL90XX_SDIV_SHIFT (0) |