43 files changed, 3627 insertions, 0 deletions

diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
new file mode 100644
index 00000000000..9843c954c04
--- /dev/null
+++ b/arch/arm/plat-s5p/Kconfig
@@ -0,0 +1,107 @@
+# arch/arm/plat-s5p/Kconfig
+#
+# Copyright (c) 2009 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+config PLAT_S5P
+        bool
+        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
+        default y
+        select ARM_VIC if !ARCH_EXYNOS4
+        select ARM_GIC if ARCH_EXYNOS4
+        select NO_IOPORT
+        select ARCH_REQUIRE_GPIOLIB
+        select S3C_GPIO_TRACK
+        select S5P_GPIO_DRVSTR
+        select SAMSUNG_GPIOLIB_4BIT
+        select S3C_GPIO_CFG_S3C64XX
+        select S3C_GPIO_PULL_UPDOWN
+        select S3C_GPIO_CFG_S3C24XX
+        select PLAT_SAMSUNG
+        select SAMSUNG_CLKSRC
+        select SAMSUNG_IRQ_VIC_TIMER
+        select SAMSUNG_IRQ_UART
+        help
+          Base platform code for Samsung's S5P series SoC.
+
+config S5P_EXT_INT
+        bool
+        help
+          Use the external interrupts (other than GPIO interrupts.)
+          Note: Do not choose this for S5P6440 and S5P6450.
+
+config S5P_GPIO_INT
+        bool
+        help
+          Common code for the GPIO interrupts (other than external interrupts.)
+
+config S5P_HRT
+        bool
+        select SAMSUNG_DEV_PWM
+        help
+          Use the High Resolution timer support
+
+comment "System MMU"
+
+config S5P_SYSTEM_MMU
+        bool "S5P SYSTEM MMU"
+        depends on ARCH_EXYNOS4
+        help
+          Say Y here if you want to enable System MMU
+
+config S5P_DEV_FIMC0
+        bool
+        help
+          Compile in platform device definitions for FIMC controller 0
+
+config S5P_DEV_FIMC1
+        bool
+        help
+          Compile in platform device definitions for FIMC controller 1
+
+config S5P_DEV_FIMC2
+        bool
+        help
+          Compile in platform device definitions for FIMC controller 2
+
+config S5P_DEV_FIMC3
+        bool
+        help
+          Compile in platform device definitions for FIMC controller 3
+
+config S5P_DEV_FIMD0
+        bool
+        help
+          Compile in platform device definitions for FIMD controller 0
+
+config S5P_DEV_MFC
+        bool
+        help
+          Compile in platform device definitions for MFC
+
+config S5P_DEV_ONENAND
+        bool
+        help
+          Compile in platform device definition for OneNAND controller
+
+config S5P_DEV_CSIS0
+        bool
+        help
+          Compile in platform device definitions for MIPI-CSIS channel 0
+
+config S5P_DEV_CSIS1
+        bool
+        help
+          Compile in platform device definitions for MIPI-CSIS channel 1
+
+config S5P_DEV_USB_EHCI
+        bool
+        help
+          Compile in platform device definition for USB EHCI
+
+config S5P_SETUP_MIPIPHY
+        bool
+        help
+          Compile in common setup code for MIPI-CSIS and MIPI-DSIM devices
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
new file mode 100644
index 00000000000..4b53e04eeca
--- /dev/null
+++ b/arch/arm/plat-s5p/Makefile
@@ -0,0 +1,38 @@
+# arch/arm/plat-s5p/Makefile
+#
+# Copyright (c) 2009 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           := dummy.o
+obj-                            :=
+
+# Core files
+
+obj-y                           += dev-pmu.o
+obj-y                           += dev-uart.o
+obj-y                           += cpu.o
+obj-y                           += clock.o
+obj-y                           += irq.o
+obj-$(CONFIG_S5P_EXT_INT)       += irq-eint.o
+obj-$(CONFIG_S5P_GPIO_INT)      += irq-gpioint.o
+obj-$(CONFIG_S5P_SYSTEM_MMU)    += sysmmu.o
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += irq-pm.o
+obj-$(CONFIG_S5P_HRT)           += s5p-time.o
+
+# devices
+obj-$(CONFIG_S5P_DEV_MFC)       += dev-mfc.o
+obj-$(CONFIG_S5P_DEV_FIMC0)     += dev-fimc0.o
+obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
+obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
+obj-$(CONFIG_S5P_DEV_FIMC3)     += dev-fimc3.o
+obj-$(CONFIG_S5P_DEV_FIMD0)     += dev-fimd0.o
+obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
+obj-$(CONFIG_S5P_DEV_CSIS0)     += dev-csis0.o
+obj-$(CONFIG_S5P_DEV_CSIS1)     += dev-csis1.o
+obj-$(CONFIG_S5P_DEV_USB_EHCI)  += dev-ehci.o
+obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
new file mode 100644
index 00000000000..5f84a3f13ef
--- /dev/null
+++ b/arch/arm/plat-s5p/clock.c
@@ -0,0 +1,228 @@
+/* linux/arch/arm/plat-s5p/clock.c
+ *
+ * Copyright 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P - Common clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <asm/div64.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/s5p-clock.h>
+
+/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
+ * clk_ext_xtal_mux.
+*/
+struct clk clk_ext_xtal_mux = {
+        .name           = "ext_xtal",
+        .id             = -1,
+};
+
+struct clk clk_xusbxti = {
+        .name           = "xusbxti",
+        .id             = -1,
+};
+
+struct clk s5p_clk_27m = {
+        .name           = "clk_27m",
+        .id             = -1,
+        .rate           = 27000000,
+};
+
+/* 48MHz USB Phy clock output */
+struct clk clk_48m = {
+        .name           = "clk_48m",
+        .id             = -1,
+        .rate           = 48000000,
+};
+
+/* APLL clock output
+ * No need .ctrlbit, this is always on
+*/
+struct clk clk_fout_apll = {
+        .name           = "fout_apll",
+        .id             = -1,
+};
+
+/* MPLL clock output
+ * No need .ctrlbit, this is always on
+*/
+struct clk clk_fout_mpll = {
+        .name           = "fout_mpll",
+        .id             = -1,
+};
+
+/* EPLL clock output */
+struct clk clk_fout_epll = {
+        .name           = "fout_epll",
+        .id             = -1,
+        .ctrlbit        = (1 << 31),
+};
+
+/* DPLL clock output */
+struct clk clk_fout_dpll = {
+        .name           = "fout_dpll",
+        .id             = -1,
+        .ctrlbit        = (1 << 31),
+};
+
+/* VPLL clock output */
+struct clk clk_fout_vpll = {
+        .name           = "fout_vpll",
+        .id             = -1,
+        .ctrlbit        = (1 << 31),
+};
+
+/* Possible clock sources for APLL Mux */
+static struct clk *clk_src_apll_list[] = {
+        [0] = &clk_fin_apll,
+        [1] = &clk_fout_apll,
+};
+
+struct clksrc_sources clk_src_apll = {
+        .sources        = clk_src_apll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+};
+
+/* Possible clock sources for MPLL Mux */
+static struct clk *clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &clk_fout_mpll,
+};
+
+struct clksrc_sources clk_src_mpll = {
+        .sources        = clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
+};
+
+/* Possible clock sources for EPLL Mux */
+static struct clk *clk_src_epll_list[] = {
+        [0] = &clk_fin_epll,
+        [1] = &clk_fout_epll,
+};
+
+struct clksrc_sources clk_src_epll = {
+        .sources        = clk_src_epll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
+};
+
+/* Possible clock sources for DPLL Mux */
+static struct clk *clk_src_dpll_list[] = {
+        [0] = &clk_fin_dpll,
+        [1] = &clk_fout_dpll,
+};
+
+struct clksrc_sources clk_src_dpll = {
+        .sources        = clk_src_dpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_dpll_list),
+};
+
+struct clk clk_vpll = {
+        .name           = "vpll",
+        .id             = -1,
+};
+
+int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        u32 con;
+
+        con = __raw_readl(reg);
+        con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
+        __raw_writel(con, reg);
+        return 0;
+}
+
+int s5p_epll_enable(struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
+
+        if (enable)
+                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
+        else
+                __raw_writel(epll_con, S5P_EPLL_CON);
+
+        return 0;
+}
+
+unsigned long s5p_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *pclk;
+        int ret;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        ret = pclk->ops->set_rate(pclk, rate);
+        clk_put(pclk);
+
+        return ret;
+}
+
+unsigned long s5p_spdif_get_rate(struct clk *clk)
+{
+        struct clk *pclk;
+        int rate;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        rate = pclk->ops->get_rate(pclk);
+        clk_put(pclk);
+
+        return rate;
+}
+
+struct clk_ops s5p_sclk_spdif_ops = {
+        .set_rate       = s5p_spdif_set_rate,
+        .get_rate       = s5p_spdif_get_rate,
+};
+
+static struct clk *s5p_clks[] __initdata = {
+        &clk_ext_xtal_mux,
+        &clk_48m,
+        &s5p_clk_27m,
+        &clk_fout_apll,
+        &clk_fout_mpll,
+        &clk_fout_epll,
+        &clk_fout_dpll,
+        &clk_fout_vpll,
+        &clk_vpll,
+        &clk_xusbxti,
+};
+
+void __init s5p_register_clocks(unsigned long xtal_freq)
+{
+        int ret;
+
+        clk_ext_xtal_mux.rate = xtal_freq;
+
+        ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
+        if (ret > 0)
+                printk(KERN_ERR "Failed to register s5p clocks\n");
+}
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
new file mode 100644
index 00000000000..bbc2aa7449c
--- /dev/null
+++ b/arch/arm/plat-s5p/cpu.c
@@ -0,0 +1,126 @@
+/* linux/arch/arm/plat-s5p/cpu.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P CPU Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/s5p6440.h>
+#include <plat/s5p6450.h>
+#include <plat/s5pc100.h>
+#include <plat/s5pv210.h>
+#include <plat/exynos4.h>
+
+/* table of supported CPUs */
+
+static const char name_s5p6440[] = "S5P6440";
+static const char name_s5p6450[] = "S5P6450";
+static const char name_s5pc100[] = "S5PC100";
+static const char name_s5pv210[] = "S5PV210/S5PC110";
+static const char name_exynos4210[] = "EXYNOS4210";
+
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = 0x56440100,
+                .idmask         = 0xfffff000,
+                .map_io         = s5p6440_map_io,
+                .init_clocks    = s5p6440_init_clocks,
+                .init_uarts     = s5p6440_init_uarts,
+                .init           = s5p64x0_init,
+                .name           = name_s5p6440,
+        }, {
+                .idcode         = 0x36450000,
+                .idmask         = 0xfffff000,
+                .map_io         = s5p6450_map_io,
+                .init_clocks    = s5p6450_init_clocks,
+                .init_uarts     = s5p6450_init_uarts,
+                .init           = s5p64x0_init,
+                .name           = name_s5p6450,
+        }, {
+                .idcode         = 0x43100000,
+                .idmask         = 0xfffff000,
+                .map_io         = s5pc100_map_io,
+                .init_clocks    = s5pc100_init_clocks,
+                .init_uarts     = s5pc100_init_uarts,
+                .init           = s5pc100_init,
+                .name           = name_s5pc100,
+        }, {
+                .idcode         = 0x43110000,
+                .idmask         = 0xfffff000,
+                .map_io         = s5pv210_map_io,
+                .init_clocks    = s5pv210_init_clocks,
+                .init_uarts     = s5pv210_init_uarts,
+                .init           = s5pv210_init,
+                .name           = name_s5pv210,
+        }, {
+                .idcode         = 0x43210000,
+                .idmask         = 0xfffe0000,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4210,
+        },
+};
+
+/* minimal IO mapping */
+
+static struct map_desc s5p_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(S5P_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(S5P_PA_SYSCON),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(S5P_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(S3C_PA_WDT),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(S5P_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+/* read cpu identification code */
+
+void __init s5p_init_io(struct map_desc *mach_desc,
+                        int size, void __iomem *cpuid_addr)
+{
+        unsigned long idcode;
+
+        /* initialize the io descriptors we need for initialization */
+        iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
+        if (mach_desc)
+                iotable_init(mach_desc, size);
+
+        idcode = __raw_readl(cpuid_addr);
+        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
new file mode 100644
index 00000000000..e3aabef5e34
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-csis0.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series device definition for MIPI-CSIS channel 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+
+static struct resource s5p_mipi_csis0_resource[] = {
+        [0] = {
+                .start = S5P_PA_MIPI_CSIS0,
+                .end   = S5P_PA_MIPI_CSIS0 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_MIPI_CSIS0,
+                .end   = IRQ_MIPI_CSIS0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s5p_device_mipi_csis0 = {
+        .name             = "s5p-mipi-csis",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5p_mipi_csis0_resource),
+        .resource         = s5p_mipi_csis0_resource,
+};
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
new file mode 100644
index 00000000000..08b91b58020
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-csis1.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series device definition for MIPI-CSIS channel 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+
+static struct resource s5p_mipi_csis1_resource[] = {
+        [0] = {
+                .start = S5P_PA_MIPI_CSIS1,
+                .end   = S5P_PA_MIPI_CSIS1 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_MIPI_CSIS1,
+                .end   = IRQ_MIPI_CSIS1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_mipi_csis1 = {
+        .name             = "s5p-mipi-csis",
+        .id               = 1,
+        .num_resources    = ARRAY_SIZE(s5p_mipi_csis1_resource),
+        .resource         = s5p_mipi_csis1_resource,
+};
diff --git a/arch/arm/plat-s5p/dev-ehci.c b/arch/arm/plat-s5p/dev-ehci.c
new file mode 100644
index 00000000000..94080fff9e9
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-ehci.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/ehci.h>
+#include <plat/usb-phy.h>
+
+/* USB EHCI Host Controller registration */
+static struct resource s5p_ehci_resource[] = {
+        [0] = {
+                .start  = S5P_PA_EHCI,
+                .end    = S5P_PA_EHCI + SZ_256 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_USB_HOST,
+                .end    = IRQ_USB_HOST,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static u64 s5p_device_ehci_dmamask = 0xffffffffUL;
+
+struct platform_device s5p_device_ehci = {
+        .name           = "s5p-ehci",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_ehci_resource),
+        .resource       = s5p_ehci_resource,
+        .dev            = {
+                .dma_mask = &s5p_device_ehci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+
+void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
+{
+        struct s5p_ehci_platdata *npd;
+
+        npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
+                        &s5p_device_ehci);
+
+        if (!npd->phy_init)
+                npd->phy_init = s5p_usb_phy_init;
+        if (!npd->phy_exit)
+                npd->phy_exit = s5p_usb_phy_exit;
+}
diff --git a/arch/arm/plat-s5p/dev-fimc0.c b/arch/arm/plat-s5p/dev-fimc0.c
new file mode 100644
index 00000000000..608770fc153
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc0.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/plat-s5p/dev-fimc0.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC0 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+
+static struct resource s5p_fimc0_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMC0,
+                .end    = S5P_PA_FIMC0 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMC0,
+                .end    = IRQ_FIMC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 s5p_fimc0_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimc0 = {
+        .name           = "s5p-fimc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_fimc0_resource),
+        .resource       = s5p_fimc0_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc0_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/plat-s5p/dev-fimc1.c b/arch/arm/plat-s5p/dev-fimc1.c
new file mode 100644
index 00000000000..76e3a97a87d
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc1.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/plat-s5p/dev-fimc1.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC1 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+
+static struct resource s5p_fimc1_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMC1,
+                .end    = S5P_PA_FIMC1 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMC1,
+                .end    = IRQ_FIMC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 s5p_fimc1_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimc1 = {
+        .name           = "s5p-fimc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p_fimc1_resource),
+        .resource       = s5p_fimc1_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc1_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/plat-s5p/dev-fimc2.c b/arch/arm/plat-s5p/dev-fimc2.c
new file mode 100644
index 00000000000..24d29816fa2
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc2.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/plat-s5p/dev-fimc2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC2 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+
+static struct resource s5p_fimc2_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMC2,
+                .end    = S5P_PA_FIMC2 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMC2,
+                .end    = IRQ_FIMC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 s5p_fimc2_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimc2 = {
+        .name           = "s5p-fimc",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s5p_fimc2_resource),
+        .resource       = s5p_fimc2_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc2_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/plat-s5p/dev-fimc3.c b/arch/arm/plat-s5p/dev-fimc3.c
new file mode 100644
index 00000000000..ef31beca386
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc3.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/plat-s5p/dev-fimc3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC3 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <mach/map.h>
+
+static struct resource s5p_fimc3_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMC3,
+                .end    = S5P_PA_FIMC3 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMC3,
+                .end    = IRQ_FIMC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 s5p_fimc3_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimc3 = {
+        .name           = "s5p-fimc",
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(s5p_fimc3_resource),
+        .resource       = s5p_fimc3_resource,
+        .dev            = {
+                .dma_mask               = &s5p_fimc3_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c
new file mode 100644
index 00000000000..f728bb5abce
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimd0.c
@@ -0,0 +1,67 @@
+/* linux/arch/arm/plat-s5p/dev-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Core file for Samsung Display Controller (FIMD) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/gfp.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/fb.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s5p_fimd0_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMD0,
+                .end    = S5P_PA_FIMD0 + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMD0_VSYNC,
+                .end    = IRQ_FIMD0_VSYNC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_FIMD0_FIFO,
+                .end    = IRQ_FIMD0_FIFO,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_FIMD0_SYSTEM,
+                .end    = IRQ_FIMD0_SYSTEM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 fimd0_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimd0 = {
+        .name           = "s5p-fb",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_fimd0_resource),
+        .resource       = s5p_fimd0_resource,
+        .dev            = {
+                .dma_mask               = &fimd0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
+{
+        s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
+                        &s5p_device_fimd0);
+}
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c
new file mode 100644
index 00000000000..94226a0010f
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-mfc.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/plat-s5p/dev-mfc.c
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ *
+ * Base S5P MFC resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/memblock.h>
+#include <linux/ioport.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/irqs.h>
+#include <plat/mfc.h>
+
+static struct resource s5p_mfc_resource[] = {
+        [0] = {
+                .start  = S5P_PA_MFC,
+                .end    = S5P_PA_MFC + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_MFC,
+                .end    = IRQ_MFC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s5p_device_mfc = {
+        .name           = "s5p-mfc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
+        .resource       = s5p_mfc_resource,
+};
+
+/*
+ * MFC hardware has 2 memory interfaces which are modelled as two separate
+ * platform devices to let dma-mapping distinguish between them.
+ *
+ * MFC parent device (s5p_device_mfc) must be registered before memory
+ * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
+ */
+
+static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_mfc_l = {
+        .name           = "s5p-mfc-l",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_mfc_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct platform_device s5p_device_mfc_r = {
+        .name           = "s5p-mfc-r",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_mfc_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct s5p_mfc_reserved_mem {
+        phys_addr_t     base;
+        unsigned long   size;
+        struct device   *dev;
+};
+
+static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
+
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+                                phys_addr_t lbase, unsigned int lsize)
+{
+        int i;
+
+        s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
+        s5p_mfc_mem[0].base = rbase;
+        s5p_mfc_mem[0].size = rsize;
+
+        s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
+        s5p_mfc_mem[1].base = lbase;
+        s5p_mfc_mem[1].size = lsize;
+
+        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+                if (memblock_remove(area->base, area->size)) {
+                        printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
+                               area->size, (unsigned long) area->base);
+                        area->base = 0;
+                }
+        }
+}
+
+static int __init s5p_mfc_memory_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+                if (!area->base)
+                        continue;
+
+                if (dma_declare_coherent_memory(area->dev, area->base,
+                                area->base, area->size,
+                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
+                        printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
+                               area->size, (unsigned long) area->base);
+        }
+        return 0;
+}
+device_initcall(s5p_mfc_memory_init);
diff --git a/arch/arm/plat-s5p/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c
new file mode 100644
index 00000000000..20336c8f247
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-onenand.c
@@ -0,0 +1,45 @@
+/* linux/arch/arm/plat-s5p/dev-onenand.c
+ *
+ * Copyright 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ *  Copyright (c) 2008-2010 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5P series device definition for OneNAND devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+static struct resource s5p_onenand_resources[] = {
+        [0] = {
+                .start  = S5P_PA_ONENAND,
+                .end    = S5P_PA_ONENAND + SZ_128K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = S5P_PA_ONENAND_DMA,
+                .end    = S5P_PA_ONENAND_DMA + SZ_8K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = IRQ_ONENAND_AUDI,
+                .end    = IRQ_ONENAND_AUDI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_onenand = {
+        .name           = "s5pc110-onenand",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_onenand_resources),
+        .resource       = s5p_onenand_resources,
+};
diff --git a/arch/arm/plat-s5p/dev-pmu.c b/arch/arm/plat-s5p/dev-pmu.c
new file mode 100644
index 00000000000..a08576da72b
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-pmu.c
@@ -0,0 +1,36 @@
+/*
+ * linux/arch/arm/plat-s5p/dev-pmu.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/pmu.h>
+#include <mach/irqs.h>
+
+static struct resource s5p_pmu_resource = {
+        .start  = IRQ_PMU,
+        .end    = IRQ_PMU,
+        .flags  = IORESOURCE_IRQ,
+};
+
+struct platform_device s5p_device_pmu = {
+        .name           = "arm-pmu",
+        .id             = ARM_PMU_DEVICE_CPU,
+        .num_resources  = 1,
+        .resource       = &s5p_pmu_resource,
+};
+
+static int __init s5p_pmu_init(void)
+{
+        platform_device_register(&s5p_device_pmu);
+        return 0;
+}
+arch_initcall(s5p_pmu_init);
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
new file mode 100644
index 00000000000..afaf87fdb93
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -0,0 +1,197 @@
+/* linux/arch/arm/plat-s5p/dev-uart.c
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Base S5P UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+ /* Serial port registrations */
+
+static struct resource s5p_uart0_resource[] = {
+        [0] = {
+                .start  = S5P_PA_UART0,
+                .end    = S5P_PA_UART0 + S5P_SZ_UART - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX0,
+                .end    = IRQ_S5P_UART_RX0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX0,
+                .end    = IRQ_S5P_UART_TX0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR0,
+                .end    = IRQ_S5P_UART_ERR0,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource s5p_uart1_resource[] = {
+        [0] = {
+                .start  = S5P_PA_UART1,
+                .end    = S5P_PA_UART1 + S5P_SZ_UART - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX1,
+                .end    = IRQ_S5P_UART_RX1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX1,
+                .end    = IRQ_S5P_UART_TX1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR1,
+                .end    = IRQ_S5P_UART_ERR1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource s5p_uart2_resource[] = {
+        [0] = {
+                .start  = S5P_PA_UART2,
+                .end    = S5P_PA_UART2 + S5P_SZ_UART - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX2,
+                .end    = IRQ_S5P_UART_RX2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX2,
+                .end    = IRQ_S5P_UART_TX2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR2,
+                .end    = IRQ_S5P_UART_ERR2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource s5p_uart3_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
+        [0] = {
+                .start  = S5P_PA_UART3,
+                .end    = S5P_PA_UART3 + S5P_SZ_UART - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX3,
+                .end    = IRQ_S5P_UART_RX3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX3,
+                .end    = IRQ_S5P_UART_TX3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR3,
+                .end    = IRQ_S5P_UART_ERR3,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
+static struct resource s5p_uart4_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
+        [0] = {
+                .start  = S5P_PA_UART4,
+                .end    = S5P_PA_UART4 + S5P_SZ_UART - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX4,
+                .end    = IRQ_S5P_UART_RX4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX4,
+                .end    = IRQ_S5P_UART_TX4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR4,
+                .end    = IRQ_S5P_UART_ERR4,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
+static struct resource s5p_uart5_resource[] = {
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
+        [0] = {
+                .start  = S5P_PA_UART5,
+                .end    = S5P_PA_UART5 + S5P_SZ_UART - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S5P_UART_RX5,
+                .end    = IRQ_S5P_UART_RX5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S5P_UART_TX5,
+                .end    = IRQ_S5P_UART_TX5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S5P_UART_ERR5,
+                .end    = IRQ_S5P_UART_ERR5,
+                .flags  = IORESOURCE_IRQ,
+        },
+#endif
+};
+
+struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
+        [0] = {
+                .resources      = s5p_uart0_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart0_resource),
+        },
+        [1] = {
+                .resources      = s5p_uart1_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart1_resource),
+        },
+        [2] = {
+                .resources      = s5p_uart2_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart2_resource),
+        },
+        [3] = {
+                .resources      = s5p_uart3_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart3_resource),
+        },
+        [4] = {
+                .resources      = s5p_uart4_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart4_resource),
+        },
+        [5] = {
+                .resources      = s5p_uart5_resource,
+                .nr_resources   = ARRAY_SIZE(s5p_uart5_resource),
+        },
+};
diff --git a/arch/arm/plat-s5p/include/plat/camport.h b/arch/arm/plat-s5p/include/plat/camport.h
new file mode 100644
index 00000000000..71688c8ba28
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/camport.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series camera interface helper functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_CAMPORT_H_
+#define PLAT_S5P_CAMPORT_H_ __FILE__
+
+enum s5p_camport_id {
+        S5P_CAMPORT_A,
+        S5P_CAMPORT_B,
+};
+
+/*
+ * The helper functions to configure GPIO for the camera parallel bus.
+ * The camera port can be multiplexed with any FIMC entity, even multiple
+ * FIMC entities are allowed to be attached to a single port simultaneously.
+ * These functions are to be used in the board setup code.
+ */
+int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
+int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
+
+#endif
diff --git a/arch/arm/plat-s5p/include/plat/ehci.h b/arch/arm/plat-s5p/include/plat/ehci.h
new file mode 100644
index 00000000000..6ae6810c756
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/ehci.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_EHCI_H
+#define __PLAT_S5P_EHCI_H
+
+struct s5p_ehci_platdata {
+        int (*phy_init)(struct platform_device *pdev, int type);
+        int (*phy_exit)(struct platform_device *pdev, int type);
+};
+
+extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
+
+#endif /* __PLAT_S5P_EHCI_H */
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
new file mode 100644
index 00000000000..907caab53dc
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -0,0 +1,34 @@
+/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for EXYNOS4 related SoCs */
+
+extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void exynos4_register_clocks(void);
+extern void exynos4_setup_clocks(void);
+
+#ifdef CONFIG_CPU_EXYNOS4210
+
+extern  int exynos4_init(void);
+extern void exynos4_init_irq(void);
+extern void exynos4_map_io(void);
+extern void exynos4_init_clocks(int xtal);
+extern struct sys_timer exynos4_timer;
+
+#define exynos4_init_uarts exynos4_common_init_uarts
+
+#else
+#define exynos4_init_clocks NULL
+#define exynos4_init_uarts NULL
+#define exynos4_map_io NULL
+#define exynos4_init NULL
+#endif
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
new file mode 100644
index 00000000000..ba9121c60a2
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -0,0 +1,115 @@
+/* linux/arch/arm/plat-s5p/include/plat/irqs.h
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P Common IRQ support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_IRQS_H
+#define __ASM_PLAT_S5P_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S5P_IRQ_OFFSET          (32)
+
+#define S5P_IRQ(x)              ((x) + S5P_IRQ_OFFSET)
+
+#define S5P_VIC0_BASE           S5P_IRQ(0)
+#define S5P_VIC1_BASE           S5P_IRQ(32)
+#define S5P_VIC2_BASE           S5P_IRQ(64)
+#define S5P_VIC3_BASE           S5P_IRQ(96)
+
+#define VIC_BASE(x)             (S5P_VIC0_BASE + ((x)*32))
+
+#define IRQ_VIC0_BASE           S5P_VIC0_BASE
+#define IRQ_VIC1_BASE           S5P_VIC1_BASE
+#define IRQ_VIC2_BASE           S5P_VIC2_BASE
+
+/* UART interrupts, each UART has 4 intterupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+
+#define IRQ_S5P_UART_BASE0      (16)
+#define IRQ_S5P_UART_BASE1      (20)
+#define IRQ_S5P_UART_BASE2      (24)
+#define IRQ_S5P_UART_BASE3      (28)
+
+#define UART_IRQ_RXD            (0)
+#define UART_IRQ_ERR            (1)
+#define UART_IRQ_TXD            (2)
+
+#define IRQ_S5P_UART_RX0        (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX0        (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR0       (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR)
+
+#define IRQ_S5P_UART_RX1        (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX1        (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR1       (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR)
+
+#define IRQ_S5P_UART_RX2        (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX2        (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR2       (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR)
+
+#define IRQ_S5P_UART_RX3        (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S5P_UART_TX3        (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S5P_UART_ERR3       (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR)
+
+/* S3C compatibilty defines */
+#define IRQ_S3CUART_RX0         IRQ_S5P_UART_RX0
+#define IRQ_S3CUART_RX1         IRQ_S5P_UART_RX1
+#define IRQ_S3CUART_RX2         IRQ_S5P_UART_RX2
+#define IRQ_S3CUART_RX3         IRQ_S5P_UART_RX3
+
+/* VIC based IRQs */
+
+#define S5P_IRQ_VIC0(x)         (S5P_VIC0_BASE + (x))
+#define S5P_IRQ_VIC1(x)         (S5P_VIC1_BASE + (x))
+#define S5P_IRQ_VIC2(x)         (S5P_VIC2_BASE + (x))
+#define S5P_IRQ_VIC3(x)         (S5P_VIC3_BASE + (x))
+
+#define S5P_TIMER_IRQ(x)        (11 + (x))
+
+#define IRQ_TIMER0              S5P_TIMER_IRQ(0)
+#define IRQ_TIMER1              S5P_TIMER_IRQ(1)
+#define IRQ_TIMER2              S5P_TIMER_IRQ(2)
+#define IRQ_TIMER3              S5P_TIMER_IRQ(3)
+#define IRQ_TIMER4              S5P_TIMER_IRQ(4)
+
+#define IRQ_EINT(x)             ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
+                                        : ((x) - 16 + S5P_EINT_BASE2))
+
+#define EINT_OFFSET(irq)        ((irq) < S5P_EINT_BASE2 ? \
+                                                ((irq) - S5P_EINT_BASE1) : \
+                                                ((irq) + 16 - S5P_EINT_BASE2))
+
+#define IRQ_EINT_BIT(x)         EINT_OFFSET(x)
+
+/* Typically only a few gpio chips require gpio interrupt support.
+   To avoid memory waste irq descriptors are allocated only for
+   S5P_GPIOINT_GROUP_COUNT chips, each with total number of
+   S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
+   to any gpio chip with the s5p_register_gpio_interrupt() function */
+#define S5P_GPIOINT_GROUP_COUNT 4
+#define S5P_GPIOINT_GROUP_SIZE  8
+#define S5P_GPIOINT_COUNT       (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
+
+/* IRQ types common for all s5p platforms */
+#define S5P_IRQ_TYPE_LEVEL_LOW          (0x00)
+#define S5P_IRQ_TYPE_LEVEL_HIGH         (0x01)
+#define S5P_IRQ_TYPE_EDGE_FALLING       (0x02)
+#define S5P_IRQ_TYPE_EDGE_RISING        (0x03)
+#define S5P_IRQ_TYPE_EDGE_BOTH          (0x04)
+
+#endif /* __ASM_PLAT_S5P_IRQS_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
new file mode 100644
index 00000000000..36d3551173b
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -0,0 +1,61 @@
+/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_S5P_H
+#define __ASM_PLAT_MAP_S5P_H __FILE__
+
+#define S5P_VA_CHIPID           S3C_ADDR(0x02000000)
+#define S5P_VA_CMU              S3C_ADDR(0x02100000)
+#define S5P_VA_PMU              S3C_ADDR(0x02180000)
+#define S5P_VA_GPIO             S3C_ADDR(0x02200000)
+#define S5P_VA_GPIO1            S5P_VA_GPIO
+#define S5P_VA_GPIO2            S3C_ADDR(0x02240000)
+#define S5P_VA_GPIO3            S3C_ADDR(0x02280000)
+
+#define S5P_VA_SYSRAM           S3C_ADDR(0x02400000)
+#define S5P_VA_DMC0             S3C_ADDR(0x02440000)
+#define S5P_VA_DMC1             S3C_ADDR(0x02480000)
+#define S5P_VA_SROMC            S3C_ADDR(0x024C0000)
+
+#define S5P_VA_SYSTIMER         S3C_ADDR(0x02500000)
+#define S5P_VA_L2CC             S3C_ADDR(0x02600000)
+
+#define S5P_VA_COMBINER_BASE    S3C_ADDR(0x02700000)
+#define S5P_VA_COMBINER(x)      (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
+
+#define S5P_VA_COREPERI_BASE    S3C_ADDR(0x02800000)
+#define S5P_VA_COREPERI(x)      (S5P_VA_COREPERI_BASE + (x))
+#define S5P_VA_SCU              S5P_VA_COREPERI(0x0)
+#define S5P_VA_TWD              S5P_VA_COREPERI(0x600)
+
+#define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
+#define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
+
+#define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
+
+#define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
+#define VA_VIC0                 VA_VIC(0)
+#define VA_VIC1                 VA_VIC(1)
+#define VA_VIC2                 VA_VIC(2)
+#define VA_VIC3                 VA_VIC(3)
+
+#define S5P_VA_UART(x)          (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_VA_UART0            S5P_VA_UART(0)
+#define S5P_VA_UART1            S5P_VA_UART(1)
+#define S5P_VA_UART2            S5P_VA_UART(2)
+#define S5P_VA_UART3            S5P_VA_UART(3)
+
+#ifndef S3C_UART_OFFSET
+#define S3C_UART_OFFSET         (0x400)
+#endif
+
+#endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h
new file mode 100644
index 00000000000..6697f8cb294
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mfc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_MFC_H
+#define __PLAT_S5P_MFC_H
+
+/**
+ * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
+ * @rbase:      base address for MFC 'right' memory interface
+ * @rsize:      size of the memory reserved for MFC 'right' interface
+ * @lbase:      base address for MFC 'left' memory interface
+ * @lsize:      size of the memory reserved for MFC 'left' interface
+ *
+ * This function reserves system memory for both MFC device memory
+ * interfaces and registers it to respective struct device entries as
+ * coherent memory.
+ */
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+                                phys_addr_t lbase, unsigned int lsize);
+
+#endif /* __PLAT_S5P_MFC_H */
diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-s5p/include/plat/mipi_csis.h
new file mode 100644
index 00000000000..9bd254c5ed2
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mipi_csis.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series MIPI CSI slave device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_MIPI_CSIS_H_
+#define PLAT_S5P_MIPI_CSIS_H_ __FILE__
+
+struct platform_device;
+
+/**
+ * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
+ * @clk_rate: bus clock frequency
+ * @lanes: number of data lanes used
+ * @alignment: data alignment in bits
+ * @hs_settle: HS-RX settle time
+ * @fixed_phy_vdd: false to enable external D-PHY regulator management in the
+ *                 driver or true in case this regulator has no enable function
+ * @phy_enable: pointer to a callback controlling D-PHY enable/reset
+ */
+struct s5p_platform_mipi_csis {
+        unsigned long clk_rate;
+        u8 lanes;
+        u8 alignment;
+        u8 hs_settle;
+        bool fixed_phy_vdd;
+        int (*phy_enable)(struct platform_device *pdev, bool on);
+};
+
+/**
+ * s5p_csis_phy_enable - global MIPI-CSI receiver D-PHY control
+ * @pdev: MIPI-CSIS platform device
+ * @on: true to enable D-PHY and deassert its reset
+ *      false to disable D-PHY
+ */
+int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
+
+#endif /* PLAT_S5P_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
new file mode 100644
index 00000000000..bf28fadee7a
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -0,0 +1,153 @@
+/* arch/arm/plat-s5p/include/plat/pll.h
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P PLL code
+ *
+ * Based on arch/arm/plat-s3c64xx/include/plat/pll.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define PLL45XX_MDIV_MASK       (0x3FF)
+#define PLL45XX_PDIV_MASK       (0x3F)
+#define PLL45XX_SDIV_MASK       (0x7)
+#define PLL45XX_MDIV_SHIFT      (16)
+#define PLL45XX_PDIV_SHIFT      (8)
+#define PLL45XX_SDIV_SHIFT      (0)
+
+#include <asm/div64.h>
+
+enum pll45xx_type_t {
+        pll_4500,
+        pll_4502,
+        pll_4508
+};
+
+static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
+                                            enum pll45xx_type_t pll_type)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+        if (pll_type == pll_4508)
+                sdiv = sdiv - 1;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+#define PLL46XX_KDIV_MASK       (0xFFFF)
+#define PLL4650C_KDIV_MASK      (0xFFF)
+#define PLL46XX_MDIV_MASK       (0x1FF)
+#define PLL46XX_PDIV_MASK       (0x3F)
+#define PLL46XX_SDIV_MASK       (0x7)
+#define PLL46XX_MDIV_SHIFT      (16)
+#define PLL46XX_PDIV_SHIFT      (8)
+#define PLL46XX_SDIV_SHIFT      (0)
+
+enum pll46xx_type_t {
+        pll_4600,
+        pll_4650,
+        pll_4650c,
+};
+
+static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
+                                            u32 pll_con0, u32 pll_con1,
+                                            enum pll46xx_type_t pll_type)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+        if (pll_type == pll_4650c)
+                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
+        else
+                kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+        tmp = baseclk;
+
+        if (pll_type == pll_4600) {
+                tmp *= (mdiv << 16) + kdiv;
+                do_div(tmp, (pdiv << sdiv));
+                result = tmp >> 16;
+        } else {
+                tmp *= (mdiv << 10) + kdiv;
+                do_div(tmp, (pdiv << sdiv));
+                result = tmp >> 10;
+        }
+
+        return result;
+}
+
+#define PLL90XX_MDIV_MASK       (0xFF)
+#define PLL90XX_PDIV_MASK       (0x3F)
+#define PLL90XX_SDIV_MASK       (0x7)
+#define PLL90XX_KDIV_MASK       (0xffff)
+#define PLL90XX_MDIV_SHIFT      (16)
+#define PLL90XX_PDIV_SHIFT      (8)
+#define PLL90XX_SDIV_SHIFT      (0)
+#define PLL90XX_KDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
+                                            u32 pll_con, u32 pll_conk)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
+        kdiv = pll_conk & PLL90XX_KDIV_MASK;
+
+        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
+         * which is in 2^16ths, so shift mdiv up (does not overflow) and
+         * add kdiv before multiplying. The use of tmp is to avoid any
+         * overflows before shifting bac down into result when multipling
+         * by the mdiv and kdiv pair.
+         */
+
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
+
+#define PLL65XX_MDIV_MASK       (0x3FF)
+#define PLL65XX_PDIV_MASK       (0x3F)
+#define PLL65XX_SDIV_MASK       (0x7)
+#define PLL65XX_MDIV_SHIFT      (16)
+#define PLL65XX_PDIV_SHIFT      (8)
+#define PLL65XX_SDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h
new file mode 100644
index 00000000000..f121ab5e76c
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/regs-srom.h
@@ -0,0 +1,54 @@
+/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_REGS_SROM_H
+#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_SROMREG(x)          (S5P_VA_SROMC + (x))
+
+#define S5P_SROM_BW             S5P_SROMREG(0x0)
+#define S5P_SROM_BC0            S5P_SROMREG(0x4)
+#define S5P_SROM_BC1            S5P_SROMREG(0x8)
+#define S5P_SROM_BC2            S5P_SROMREG(0xc)
+#define S5P_SROM_BC3            S5P_SROMREG(0x10)
+#define S5P_SROM_BC4            S5P_SROMREG(0x14)
+#define S5P_SROM_BC5            S5P_SROMREG(0x18)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define S5P_SROM_BW__DATAWIDTH__SHIFT           0
+#define S5P_SROM_BW__ADDRMODE__SHIFT            1
+#define S5P_SROM_BW__WAITENABLE__SHIFT          2
+#define S5P_SROM_BW__BYTEENABLE__SHIFT          3
+
+#define S5P_SROM_BW__CS_MASK                    0xf
+
+#define S5P_SROM_BW__NCS0__SHIFT                0
+#define S5P_SROM_BW__NCS1__SHIFT                4
+#define S5P_SROM_BW__NCS2__SHIFT                8
+#define S5P_SROM_BW__NCS3__SHIFT                12
+#define S5P_SROM_BW__NCS4__SHIFT                16
+#define S5P_SROM_BW__NCS5__SHIFT                20
+
+/* applies to same to BCS0 - BCS3 */
+
+#define S5P_SROM_BCX__PMC__SHIFT                0
+#define S5P_SROM_BCX__TACP__SHIFT               4
+#define S5P_SROM_BCX__TCAH__SHIFT               8
+#define S5P_SROM_BCX__TCOH__SHIFT               12
+#define S5P_SROM_BCX__TACC__SHIFT               16
+#define S5P_SROM_BCX__TCOS__SHIFT               24
+#define S5P_SROM_BCX__TACS__SHIFT               28
+
+#endif /* __ASM_PLAT_S5P_REGS_SROM_H */
diff --git a/arch/arm/plat-s5p/include/plat/reset.h b/arch/arm/plat-s5p/include/plat/reset.h
new file mode 100644
index 00000000000..335e97812ee
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/reset.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/plat-s5p/include/plat/reset.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_RESET_H
+#define __ASM_PLAT_S5P_RESET_H __FILE__
+
+extern void (*s5p_reset_hook)(void);
+
+#endif /* __ASM_PLAT_S5P_RESET_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
new file mode 100644
index 00000000000..769b5bdfb04
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -0,0 +1,55 @@
+/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_CLOCK_H
+#define __ASM_PLAT_S5P_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
+
+#define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_mpll clk_ext_xtal_mux
+#define clk_fin_epll clk_ext_xtal_mux
+#define clk_fin_dpll clk_ext_xtal_mux
+#define clk_fin_vpll clk_ext_xtal_mux
+#define clk_fin_hpll clk_ext_xtal_mux
+
+extern struct clk clk_ext_xtal_mux;
+extern struct clk clk_xusbxti;
+extern struct clk clk_48m;
+extern struct clk s5p_clk_27m;
+extern struct clk clk_fout_apll;
+extern struct clk clk_fout_mpll;
+extern struct clk clk_fout_epll;
+extern struct clk clk_fout_dpll;
+extern struct clk clk_fout_vpll;
+extern struct clk clk_arm;
+extern struct clk clk_vpll;
+
+extern struct clksrc_sources clk_src_apll;
+extern struct clksrc_sources clk_src_mpll;
+extern struct clksrc_sources clk_src_epll;
+extern struct clksrc_sources clk_src_dpll;
+
+extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
+
+/* Common EPLL operations for S5P platform */
+extern int s5p_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p_epll_get_rate(struct clk *clk);
+
+/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
+extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
+extern unsigned long s5p_spdif_get_rate(struct clk *clk);
+
+extern struct clk_ops s5p_sclk_spdif_ops;
+#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-time.h b/arch/arm/plat-s5p/include/plat/s5p-time.h
new file mode 100644
index 00000000000..575e88109db
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p-time.h
@@ -0,0 +1,40 @@
+/* linux/arch/arm/plat-s5p/include/plat/s5p-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S5P_TIME_H
+#define __ASM_PLAT_S5P_TIME_H __FILE__
+
+/* S5P HR-Timer Clock mode */
+enum s5p_timer_mode {
+        S5P_PWM0,
+        S5P_PWM1,
+        S5P_PWM2,
+        S5P_PWM3,
+        S5P_PWM4,
+};
+
+struct s5p_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define S5PTIMER_MIN_RANGE      4
+
+#define TCNT_MAX                0xffffffff
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
+                                        enum s5p_timer_mode source);
+extern  struct sys_timer s5p_timer;
+#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h
new file mode 100644
index 00000000000..528585d2caf
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p6440.h
@@ -0,0 +1,36 @@
+/* arch/arm/plat-s5p/include/plat/s5p6440.h
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for s5p6440 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+ /* Common init code for S5P6440 related SoCs */
+
+extern void s5p6440_register_clocks(void);
+extern void s5p6440_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5P6440
+
+extern  int s5p64x0_init(void);
+extern void s5p6440_init_irq(void);
+extern void s5p6440_map_io(void);
+extern void s5p6440_init_clocks(int xtal);
+
+extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+#else
+#define s5p6440_init_clocks NULL
+#define s5p6440_init_uarts NULL
+#define s5p6440_map_io NULL
+#define s5p64x0_init NULL
+#endif
+
+/* S5P6440 timer */
+
+extern struct sys_timer s5p6440_timer;
diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-s5p/include/plat/s5p6450.h
new file mode 100644
index 00000000000..640a41c26be
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
+/* arch/arm/plat-s5p/include/plat/s5p6450.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for s5p6450 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5P6450 related SoCs */
+
+extern void s5p6450_register_clocks(void);
+extern void s5p6450_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5P6450
+
+extern  int s5p64x0_init(void);
+extern void s5p6450_init_irq(void);
+extern void s5p6450_map_io(void);
+extern void s5p6450_init_clocks(int xtal);
+
+extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+#else
+#define s5p6450_init_clocks NULL
+#define s5p6450_init_uarts NULL
+#define s5p6450_map_io NULL
+#define s5p64x0_init NULL
+#endif
+
+/* S5P6450 timer */
+
+extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h
new file mode 100644
index 00000000000..5f6099dd7ca
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5pc100.h
@@ -0,0 +1,33 @@
+/* arch/arm/plat-s5p/include/plat/s5pc100.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for s5pc100 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PC100 related SoCs */
+
+extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc100_register_clocks(void);
+extern void s5pc100_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5PC100
+
+extern  int s5pc100_init(void);
+extern void s5pc100_init_irq(void);
+extern void s5pc100_map_io(void);
+extern void s5pc100_init_clocks(int xtal);
+
+#define s5pc100_init_uarts s5pc100_common_init_uarts
+
+#else
+#define s5pc100_init_clocks NULL
+#define s5pc100_init_uarts NULL
+#define s5pc100_map_io NULL
+#define s5pc100_init NULL
+#endif
diff --git a/arch/arm/plat-s5p/include/plat/s5pv210.h b/arch/arm/plat-s5p/include/plat/s5pv210.h
new file mode 100644
index 00000000000..6c93a0c7810
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5pv210.h
@@ -0,0 +1,33 @@
+/* linux/arch/arm/plat-s5p/include/plat/s5pv210.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for s5pv210 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PV210 related SoCs */
+
+extern void s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pv210_register_clocks(void);
+extern void s5pv210_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5PV210
+
+extern  int s5pv210_init(void);
+extern void s5pv210_init_irq(void);
+extern void s5pv210_map_io(void);
+extern void s5pv210_init_clocks(int xtal);
+
+#define s5pv210_init_uarts s5pv210_common_init_uarts
+
+#else
+#define s5pv210_init_clocks NULL
+#define s5pv210_init_uarts NULL
+#define s5pv210_map_io NULL
+#define s5pv210_init NULL
+#endif
diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h
new file mode 100644
index 00000000000..bf5283c2a19
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/sysmmu.h
@@ -0,0 +1,95 @@
+/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung System MMU driver for S5P platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM__PLAT_SYSMMU_H
+#define __ASM__PLAT_SYSMMU_H __FILE__
+
+enum S5P_SYSMMU_INTERRUPT_TYPE {
+        SYSMMU_PAGEFAULT,
+        SYSMMU_AR_MULTIHIT,
+        SYSMMU_AW_MULTIHIT,
+        SYSMMU_BUSERROR,
+        SYSMMU_AR_SECURITY,
+        SYSMMU_AR_ACCESS,
+        SYSMMU_AW_SECURITY,
+        SYSMMU_AW_PROTECTION, /* 7 */
+        SYSMMU_FAULTS_NUM
+};
+
+#ifdef CONFIG_S5P_SYSTEM_MMU
+
+#include <mach/sysmmu.h>
+
+/**
+ * s5p_sysmmu_enable() - enable system mmu of ip
+ * @ips: The ip connected system mmu.
+ * #pgd: Base physical address of the 1st level page table
+ *
+ * This function enable system mmu to transfer address
+ * from virtual address to physical address
+ */
+void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
+
+/**
+ * s5p_sysmmu_disable() - disable sysmmu mmu of ip
+ * @ips: The ip connected system mmu.
+ *
+ * This function disable system mmu to transfer address
+ * from virtual address to physical address
+ */
+void s5p_sysmmu_disable(sysmmu_ips ips);
+
+/**
+ * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
+ * @ips: The ip connected system mmu.
+ * @pgd: The page table base address.
+ *
+ * This function set page table base address
+ * When system mmu transfer address from virtaul address to physical address,
+ * system mmu refer address information from page table
+ */
+void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
+
+/**
+ * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
+ * @ips: The ip connected system mmu.
+ *
+ * This function flush all TLB entry in system mmu
+ */
+void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
+
+/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
+ * @itype: type of fault.
+ * @pgtable_base: the physical address of page table base. This is 0 if @ips is
+ *               SYSMMU_BUSERROR.
+ * @fault_addr: the device (virtual) address that the System MMU tried to
+ *             translated. This is 0 if @ips is SYSMMU_BUSERROR.
+ * Called when interrupt occurred by the System MMUs
+ * The device drivers of peripheral devices that has a System MMU can implement
+ * a fault handler to resolve address translation fault by System MMU.
+ * The meanings of return value and parameters are described below.
+
+ * return value: non-zero if the fault is correctly resolved.
+ *         zero if the fault is not handled.
+ */
+void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
+                        int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+                                        unsigned long pgtable_base,
+                                        unsigned long fault_addr));
+#else
+#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
+#define s5p_sysmmu_disable(ips) do { } while (0)
+#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
+#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
+#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
+#endif
+#endif /* __ASM_PLAT_SYSMMU_H */
diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h
new file mode 100644
index 00000000000..f307f34e642
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/system-reset.h
@@ -0,0 +1,31 @@
+/* linux/arch/arm/plat-s5p/include/plat/system-reset.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
+ *
+ * S5P - System define for arch_reset()
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/watchdog-reset.h>
+
+void (*s5p_reset_hook)(void);
+
+static void arch_reset(char mode, const char *cmd)
+{
+        /* SWRESET support in s5p_reset_hook() */
+
+        if (s5p_reset_hook)
+                s5p_reset_hook();
+
+        /* Perform reset using Watchdog reset
+         * if there is no s5p_reset_hook()
+         */
+
+        arch_wdt_reset();
+}
diff --git a/arch/arm/plat-s5p/include/plat/usb-phy.h b/arch/arm/plat-s5p/include/plat/usb-phy.h
new file mode 100644
index 00000000000..6dd6bcfca3c
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/usb-phy.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_USB_PHY_H
+#define __PLAT_S5P_USB_PHY_H
+
+enum s5p_usb_phy_type {
+        S5P_USB_PHY_DEVICE,
+        S5P_USB_PHY_HOST,
+};
+
+extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
+extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+
+#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
new file mode 100644
index 00000000000..b5bb774985b
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -0,0 +1,219 @@
+/* linux/arch/arm/plat-s5p/irq-eint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware/vic.h>
+
+#include <plat/regs-irqtype.h>
+
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+#include <plat/gpio-cfg.h>
+#include <mach/regs-gpio.h>
+
+static inline void s5p_irq_eint_mask(struct irq_data *data)
+{
+        u32 mask;
+
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask |= eint_irq_to_bit(data->irq);
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+}
+
+static void s5p_irq_eint_unmask(struct irq_data *data)
+{
+        u32 mask;
+
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask &= ~(eint_irq_to_bit(data->irq));
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+}
+
+static inline void s5p_irq_eint_ack(struct irq_data *data)
+{
+        __raw_writel(eint_irq_to_bit(data->irq),
+                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+}
+
+static void s5p_irq_eint_maskack(struct irq_data *data)
+{
+        /* compiler should in-line these */
+        s5p_irq_eint_mask(data);
+        s5p_irq_eint_ack(data);
+}
+
+static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+        int offs = EINT_OFFSET(data->irq);
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+                break;
+
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+                break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+                break;
+
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+                break;
+
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+
+        shift = (offs & 0x7) * 4;
+        mask = 0x7 << shift;
+
+        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+        ctrl &= ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+
+        if ((0 <= offs) && (offs < 8))
+                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+
+        else if ((8 <= offs) && (offs < 16))
+                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+
+        else if ((16 <= offs) && (offs < 24))
+                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+
+        else if ((24 <= offs) && (offs < 32))
+                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+
+        else
+                printk(KERN_ERR "No such irq number %d", offs);
+
+        return 0;
+}
+
+static struct irq_chip s5p_irq_eint = {
+        .name           = "s5p-eint",
+        .irq_mask       = s5p_irq_eint_mask,
+        .irq_unmask     = s5p_irq_eint_unmask,
+        .irq_mask_ack   = s5p_irq_eint_maskack,
+        .irq_ack        = s5p_irq_eint_ack,
+        .irq_set_type   = s5p_irq_eint_set_type,
+#ifdef CONFIG_PM
+        .irq_set_wake   = s3c_irqext_wake,
+#endif
+};
+
+/* s5p_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from EINTs 16 to 31. It is designed to be inlined into the specific
+ * handler s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void s5p_irq_demux_eint(unsigned int start)
+{
+        u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+        unsigned int irq;
+
+        status &= ~mask;
+        status &= 0xff;
+
+        while (status) {
+                irq = fls(status) - 1;
+                generic_handle_irq(irq + start);
+                status &= ~(1 << irq);
+        }
+}
+
+static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+        s5p_irq_demux_eint(IRQ_EINT(16));
+        s5p_irq_demux_eint(IRQ_EINT(24));
+}
+
+static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
+{
+        void __iomem *base = irq_data_get_irq_chip_data(data);
+
+        s5p_irq_eint_mask(data);
+        writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
+}
+
+static void s5p_irq_vic_eint_unmask(struct irq_data *data)
+{
+        void __iomem *base = irq_data_get_irq_chip_data(data);
+
+        s5p_irq_eint_unmask(data);
+        writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
+}
+
+static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
+{
+        __raw_writel(eint_irq_to_bit(data->irq),
+                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+}
+
+static void s5p_irq_vic_eint_maskack(struct irq_data *data)
+{
+        s5p_irq_vic_eint_mask(data);
+        s5p_irq_vic_eint_ack(data);
+}
+
+static struct irq_chip s5p_irq_vic_eint = {
+        .name           = "s5p_vic_eint",
+        .irq_mask       = s5p_irq_vic_eint_mask,
+        .irq_unmask     = s5p_irq_vic_eint_unmask,
+        .irq_mask_ack   = s5p_irq_vic_eint_maskack,
+        .irq_ack        = s5p_irq_vic_eint_ack,
+        .irq_set_type   = s5p_irq_eint_set_type,
+#ifdef CONFIG_PM
+        .irq_set_wake   = s3c_irqext_wake,
+#endif
+};
+
+int __init s5p_init_irq_eint(void)
+{
+        int irq;
+
+        for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
+                irq_set_chip(irq, &s5p_irq_vic_eint);
+
+        for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
+                irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
+        return 0;
+}
+
+arch_initcall(s5p_init_irq_eint);
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
new file mode 100644
index 00000000000..c65eb791d1b
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -0,0 +1,216 @@
+/* linux/arch/arm/plat-s5p/irq-gpioint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Author: Kyungmin Park <kyungmin.park@samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+
+#include <mach/map.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+
+#include <asm/mach/irq.h>
+
+#define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
+
+#define CON_OFFSET              0x700
+#define MASK_OFFSET             0x900
+#define PEND_OFFSET             0xA00
+#define REG_OFFSET(x)           ((x) << 2)
+
+struct s5p_gpioint_bank {
+        struct list_head        list;
+        int                     start;
+        int                     nr_groups;
+        int                     irq;
+        struct s3c_gpio_chip    **chips;
+        void                    (*handler)(unsigned int, struct irq_desc *);
+};
+
+LIST_HEAD(banks);
+
+static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        unsigned int shift = (d->irq - gc->irq_base) << 2;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                type = S5P_IRQ_TYPE_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type = S5P_IRQ_TYPE_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                type = S5P_IRQ_TYPE_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                type = S5P_IRQ_TYPE_LEVEL_HIGH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                type = S5P_IRQ_TYPE_LEVEL_LOW;
+                break;
+        case IRQ_TYPE_NONE:
+        default:
+                printk(KERN_WARNING "No irq type\n");
+                return -EINVAL;
+        }
+
+        gc->type_cache &= ~(0x7 << shift);
+        gc->type_cache |= type << shift;
+        writel(gc->type_cache, gc->reg_base + ct->regs.type);
+        return 0;
+}
+
+static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
+        int group, pend_offset, mask_offset;
+        unsigned int pend, mask;
+
+        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
+
+        for (group = 0; group < bank->nr_groups; group++) {
+                struct s3c_gpio_chip *chip = bank->chips[group];
+                if (!chip)
+                        continue;
+
+                pend_offset = REG_OFFSET(group);
+                pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
+                if (!pend)
+                        continue;
+
+                mask_offset = REG_OFFSET(group);
+                mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
+                pend &= ~mask;
+
+                while (pend) {
+                        int offset = fls(pend) - 1;
+                        int real_irq = chip->irq_base + offset;
+                        generic_handle_irq(real_irq);
+                        pend &= ~BIT(offset);
+                }
+        }
+        chained_irq_exit(chip, desc);
+}
+
+static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
+{
+        static int used_gpioint_groups = 0;
+        int group = chip->group;
+        struct s5p_gpioint_bank *b, *bank = NULL;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
+                return -ENOMEM;
+
+        list_for_each_entry(b, &banks, list) {
+                if (group >= b->start && group < b->start + b->nr_groups) {
+                        bank = b;
+                        break;
+                }
+        }
+        if (!bank)
+                return -EINVAL;
+
+        if (!bank->handler) {
+                bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) *
+                                      bank->nr_groups, GFP_KERNEL);
+                if (!bank->chips)
+                        return -ENOMEM;
+
+                irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
+                irq_set_handler_data(bank->irq, bank);
+                bank->handler = s5p_gpioint_handler;
+                printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
+                       bank->irq);
+        }
+
+        /*
+         * chained GPIO irq has been successfully registered, allocate new gpio
+         * int group and assign irq nubmers
+         */
+        chip->irq_base = S5P_GPIOINT_BASE +
+                         used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
+        used_gpioint_groups++;
+
+        bank->chips[group - bank->start] = chip;
+
+        gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
+                                    (void __iomem *)GPIO_BASE(chip),
+                                    handle_level_irq);
+        if (!gc)
+                return -ENOMEM;
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_type = s5p_gpioint_set_type,
+        ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
+        ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
+        ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
+        irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
+                               IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+        return 0;
+}
+
+int __init s5p_register_gpio_interrupt(int pin)
+{
+        struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
+        int offset, group;
+        int ret;
+
+        if (!my_chip)
+                return -EINVAL;
+
+        offset = pin - my_chip->chip.base;
+        group = my_chip->group;
+
+        /* check if the group has been already registered */
+        if (my_chip->irq_base)
+                return my_chip->irq_base + offset;
+
+        /* register gpio group */
+        ret = s5p_gpioint_add(my_chip);
+        if (ret == 0) {
+                my_chip->chip.to_irq = samsung_gpiolib_to_irq;
+                printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
+                       group);
+                return my_chip->irq_base + offset;
+        }
+        return ret;
+}
+
+int __init s5p_register_gpioint_bank(int chain_irq, int start, int nr_groups)
+{
+        struct s5p_gpioint_bank *bank;
+
+        bank = kzalloc(sizeof(*bank), GFP_KERNEL);
+        if (!bank)
+                return -ENOMEM;
+
+        bank->start = start;
+        bank->nr_groups = nr_groups;
+        bank->irq = chain_irq;
+
+        list_add_tail(&bank->list, &banks);
+        return 0;
+}
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
new file mode 100644
index 00000000000..327acb3a446
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -0,0 +1,90 @@
+/* linux/arch/arm/plat-s5p/irq-pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Based on arch/arm/plat-s3c24xx/irq-pm.c,
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+
+#include <plat/cpu.h>
+#include <plat/irqs.h>
+#include <plat/pm.h>
+#include <mach/map.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
+
+/* state for IRQs over sleep */
+
+/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
+ * as wakeup sources
+ *
+ * set bit to 1 in allow bitfield to enable the wakeup settings on it
+*/
+
+unsigned long s3c_irqwake_intallow      = 0x00000006L;
+unsigned long s3c_irqwake_eintallow     = 0xffffffffL;
+
+int s3c_irq_wake(struct irq_data *data, unsigned int state)
+{
+        unsigned long irqbit;
+
+        switch (data->irq) {
+        case IRQ_RTC_TIC:
+        case IRQ_RTC_ALARM:
+                irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
+                if (!state)
+                        s3c_irqwake_intmask |= irqbit;
+                else
+                        s3c_irqwake_intmask &= ~irqbit;
+                break;
+        default:
+                return -ENOENT;
+        }
+        return 0;
+}
+
+static struct sleep_save eint_save[] = {
+        SAVE_ITEM(S5P_EINT_CON(0)),
+        SAVE_ITEM(S5P_EINT_CON(1)),
+        SAVE_ITEM(S5P_EINT_CON(2)),
+        SAVE_ITEM(S5P_EINT_CON(3)),
+
+        SAVE_ITEM(S5P_EINT_FLTCON(0)),
+        SAVE_ITEM(S5P_EINT_FLTCON(1)),
+        SAVE_ITEM(S5P_EINT_FLTCON(2)),
+        SAVE_ITEM(S5P_EINT_FLTCON(3)),
+        SAVE_ITEM(S5P_EINT_FLTCON(4)),
+        SAVE_ITEM(S5P_EINT_FLTCON(5)),
+        SAVE_ITEM(S5P_EINT_FLTCON(6)),
+        SAVE_ITEM(S5P_EINT_FLTCON(7)),
+
+        SAVE_ITEM(S5P_EINT_MASK(0)),
+        SAVE_ITEM(S5P_EINT_MASK(1)),
+        SAVE_ITEM(S5P_EINT_MASK(2)),
+        SAVE_ITEM(S5P_EINT_MASK(3)),
+};
+
+int s3c24xx_irq_suspend(void)
+{
+        s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
+
+        return 0;
+}
+
+void s3c24xx_irq_resume(void)
+{
+        s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
+}
+
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
new file mode 100644
index 00000000000..a97c08957f4
--- /dev/null
+++ b/arch/arm/plat-s5p/irq.c
@@ -0,0 +1,70 @@
+/* arch/arm/plat-s5p/irq.c
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P - Interrupt handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/vic.h>
+
+#include <linux/serial_core.h>
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+#include <plat/irq-vic-timer.h>
+#include <plat/irq-uart.h>
+
+/*
+ * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
+ * are consecutive when looking up the interrupt in the demux routines.
+ */
+static struct s3c_uart_irq uart_irqs[] = {
+        [0] = {
+                .regs           = S5P_VA_UART0,
+                .base_irq       = IRQ_S5P_UART_BASE0,
+                .parent_irq     = IRQ_UART0,
+        },
+        [1] = {
+                .regs           = S5P_VA_UART1,
+                .base_irq       = IRQ_S5P_UART_BASE1,
+                .parent_irq     = IRQ_UART1,
+        },
+        [2] = {
+                .regs           = S5P_VA_UART2,
+                .base_irq       = IRQ_S5P_UART_BASE2,
+                .parent_irq     = IRQ_UART2,
+        },
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
+        [3] = {
+                .regs           = S5P_VA_UART3,
+                .base_irq       = IRQ_S5P_UART_BASE3,
+                .parent_irq     = IRQ_UART3,
+        },
+#endif
+};
+
+void __init s5p_init_irq(u32 *vic, u32 num_vic)
+{
+#ifdef CONFIG_ARM_VIC
+        int irq;
+
+        /* initialize the VICs */
+        for (irq = 0; irq < num_vic; irq++)
+                vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
+#endif
+
+        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
+
+        s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
+}
diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
new file mode 100644
index 00000000000..d15dc47b0e3
--- /dev/null
+++ b/arch/arm/plat-s5p/pm.c
@@ -0,0 +1,41 @@
+/* linux/arch/arm/plat-s5p/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P Power Manager (Suspend-To-RAM) support
+ *
+ * Based on arch/arm/plat-s3c24xx/pm.c
+ * Copyright (c) 2004,2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <plat/pm.h>
+
+#define PFX "s5p pm: "
+
+/* s3c_pm_configure_extint
+ *
+ * configure all external interrupt pins
+*/
+
+void s3c_pm_configure_extint(void)
+{
+        /* nothing here yet */
+}
+
+void s3c_pm_restore_core(void)
+{
+        /* nothing here yet */
+}
+
+void s3c_pm_save_core(void)
+{
+        /* nothing here yet */
+}
+
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
new file mode 100644
index 00000000000..c833e7b5759
--- /dev/null
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -0,0 +1,419 @@
+/* linux/arch/arm/plat-s5p/s5p-time.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P - Common hr-timer support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+
+#include <asm/smp_twd.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/sched_clock.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/regs-timer.h>
+#include <plat/s5p-time.h>
+
+static struct clk *tin_event;
+static struct clk *tin_source;
+static struct clk *tdiv_event;
+static struct clk *tdiv_source;
+static struct clk *timerclk;
+static struct s5p_timer_source timer_source;
+static unsigned long clock_count_per_tick;
+static void s5p_timer_resume(void);
+
+static void s5p_time_stop(enum s5p_timer_mode mode)
+{
+        unsigned long tcon;
+
+        tcon = __raw_readl(S3C2410_TCON);
+
+        switch (mode) {
+        case S5P_PWM0:
+                tcon &= ~S3C2410_TCON_T0START;
+                break;
+
+        case S5P_PWM1:
+                tcon &= ~S3C2410_TCON_T1START;
+                break;
+
+        case S5P_PWM2:
+                tcon &= ~S3C2410_TCON_T2START;
+                break;
+
+        case S5P_PWM3:
+                tcon &= ~S3C2410_TCON_T3START;
+                break;
+
+        case S5P_PWM4:
+                tcon &= ~S3C2410_TCON_T4START;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", mode);
+                break;
+        }
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+{
+        unsigned long tcon;
+
+        tcon = __raw_readl(S3C2410_TCON);
+
+        tcnt--;
+
+        switch (mode) {
+        case S5P_PWM0:
+                tcon &= ~(0x0f << 0);
+                tcon |= S3C2410_TCON_T0MANUALUPD;
+                break;
+
+        case S5P_PWM1:
+                tcon &= ~(0x0f << 8);
+                tcon |= S3C2410_TCON_T1MANUALUPD;
+                break;
+
+        case S5P_PWM2:
+                tcon &= ~(0x0f << 12);
+                tcon |= S3C2410_TCON_T2MANUALUPD;
+                break;
+
+        case S5P_PWM3:
+                tcon &= ~(0x0f << 16);
+                tcon |= S3C2410_TCON_T3MANUALUPD;
+                break;
+
+        case S5P_PWM4:
+                tcon &= ~(0x07 << 20);
+                tcon |= S3C2410_TCON_T4MANUALUPD;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", mode);
+                break;
+        }
+
+        __raw_writel(tcnt, S3C2410_TCNTB(mode));
+        __raw_writel(tcnt, S3C2410_TCMPB(mode));
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+{
+        unsigned long tcon;
+
+        tcon  = __raw_readl(S3C2410_TCON);
+
+        switch (mode) {
+        case S5P_PWM0:
+                tcon |= S3C2410_TCON_T0START;
+                tcon &= ~S3C2410_TCON_T0MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T0RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T0RELOAD;
+                break;
+
+        case S5P_PWM1:
+                tcon |= S3C2410_TCON_T1START;
+                tcon &= ~S3C2410_TCON_T1MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T1RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T1RELOAD;
+                break;
+
+        case S5P_PWM2:
+                tcon |= S3C2410_TCON_T2START;
+                tcon &= ~S3C2410_TCON_T2MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T2RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T2RELOAD;
+                break;
+
+        case S5P_PWM3:
+                tcon |= S3C2410_TCON_T3START;
+                tcon &= ~S3C2410_TCON_T3MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T3RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T3RELOAD;
+                break;
+
+        case S5P_PWM4:
+                tcon |= S3C2410_TCON_T4START;
+                tcon &= ~S3C2410_TCON_T4MANUALUPD;
+
+                if (periodic)
+                        tcon |= S3C2410_TCON_T4RELOAD;
+                else
+                        tcon &= ~S3C2410_TCON_T4RELOAD;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", mode);
+                break;
+        }
+        __raw_writel(tcon, S3C2410_TCON);
+}
+
+static int s5p_set_next_event(unsigned long cycles,
+                                struct clock_event_device *evt)
+{
+        s5p_time_setup(timer_source.event_id, cycles);
+        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+
+        return 0;
+}
+
+static void s5p_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        s5p_time_stop(timer_source.event_id);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
+                s5p_time_start(timer_source.event_id, PERIODIC);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                break;
+
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                break;
+
+        case CLOCK_EVT_MODE_RESUME:
+                s5p_timer_resume();
+                break;
+        }
+}
+
+static void s5p_timer_resume(void)
+{
+        /* event timer restart */
+        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
+        s5p_time_start(timer_source.event_id, PERIODIC);
+
+        /* source timer restart */
+        s5p_time_setup(timer_source.source_id, TCNT_MAX);
+        s5p_time_start(timer_source.source_id, PERIODIC);
+}
+
+void __init s5p_set_timer_source(enum s5p_timer_mode event,
+                                 enum s5p_timer_mode source)
+{
+        s3c_device_timer[event].dev.bus = &platform_bus_type;
+        s3c_device_timer[source].dev.bus = &platform_bus_type;
+
+        timer_source.event_id = event;
+        timer_source.source_id = source;
+}
+
+static struct clock_event_device time_event_device = {
+        .name           = "s5p_event_timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 200,
+        .set_next_event = s5p_set_next_event,
+        .set_mode       = s5p_set_mode,
+};
+
+static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction s5p_clock_event_irq = {
+        .name           = "s5p_time_irq",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = s5p_clock_event_isr,
+        .dev_id         = &time_event_device,
+};
+
+static void __init s5p_clockevent_init(void)
+{
+        unsigned long pclk;
+        unsigned long clock_rate;
+        unsigned int irq_number;
+        struct clk *tscaler;
+
+        pclk = clk_get_rate(timerclk);
+
+        tscaler = clk_get_parent(tdiv_event);
+
+        clk_set_rate(tscaler, pclk / 2);
+        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_parent(tin_event, tdiv_event);
+
+        clock_rate = clk_get_rate(tin_event);
+        clock_count_per_tick = clock_rate / HZ;
+
+        clockevents_calc_mult_shift(&time_event_device,
+                                    clock_rate, S5PTIMER_MIN_RANGE);
+        time_event_device.max_delta_ns =
+                clockevent_delta2ns(-1, &time_event_device);
+        time_event_device.min_delta_ns =
+                clockevent_delta2ns(1, &time_event_device);
+
+        time_event_device.cpumask = cpumask_of(0);
+        clockevents_register_device(&time_event_device);
+
+        irq_number = timer_source.event_id + IRQ_TIMER0;
+        setup_irq(irq_number, &s5p_clock_event_irq);
+}
+
+static void __iomem *s5p_timer_reg(void)
+{
+        unsigned long offset = 0;
+
+        switch (timer_source.source_id) {
+        case S5P_PWM0:
+        case S5P_PWM1:
+        case S5P_PWM2:
+        case S5P_PWM3:
+                offset = (timer_source.source_id * 0x0c) + 0x14;
+                break;
+
+        case S5P_PWM4:
+                offset = 0x40;
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
+                return NULL;
+        }
+
+        return S3C_TIMERREG(offset);
+}
+
+/*
+ * Override the global weak sched_clock symbol with this
+ * local implementation which uses the clocksource to get some
+ * better resolution when scheduling the kernel. We accept that
+ * this wraps around for now, since it is just a relative time
+ * stamp. (Inspired by U300 implementation.)
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+unsigned long long notrace sched_clock(void)
+{
+        void __iomem *reg = s5p_timer_reg();
+
+        if (!reg)
+                return 0;
+
+        return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
+}
+
+static void notrace s5p_update_sched_clock(void)
+{
+        void __iomem *reg = s5p_timer_reg();
+
+        if (!reg)
+                return;
+
+        update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
+}
+
+static void __init s5p_clocksource_init(void)
+{
+        unsigned long pclk;
+        unsigned long clock_rate;
+
+        pclk = clk_get_rate(timerclk);
+
+        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_parent(tin_source, tdiv_source);
+
+        clock_rate = clk_get_rate(tin_source);
+
+        s5p_time_setup(timer_source.source_id, TCNT_MAX);
+        s5p_time_start(timer_source.source_id, PERIODIC);
+
+        init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
+
+        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
+                        clock_rate, 250, 32, clocksource_mmio_readl_down))
+                panic("s5p_clocksource_timer: can't register clocksource\n");
+}
+
+static void __init s5p_timer_resources(void)
+{
+
+        unsigned long event_id = timer_source.event_id;
+        unsigned long source_id = timer_source.source_id;
+        char devname[15];
+
+        timerclk = clk_get(NULL, "timers");
+        if (IS_ERR(timerclk))
+                panic("failed to get timers clock for timer");
+
+        clk_enable(timerclk);
+
+        sprintf(devname, "s3c24xx-pwm.%lu", event_id);
+        s3c_device_timer[event_id].id = event_id;
+        s3c_device_timer[event_id].dev.init_name = devname;
+
+        tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
+        if (IS_ERR(tin_event))
+                panic("failed to get pwm-tin clock for event timer");
+
+        tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv");
+        if (IS_ERR(tdiv_event))
+                panic("failed to get pwm-tdiv clock for event timer");
+
+        clk_enable(tin_event);
+
+        sprintf(devname, "s3c24xx-pwm.%lu", source_id);
+        s3c_device_timer[source_id].id = source_id;
+        s3c_device_timer[source_id].dev.init_name = devname;
+
+        tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
+        if (IS_ERR(tin_source))
+                panic("failed to get pwm-tin clock for source timer");
+
+        tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv");
+        if (IS_ERR(tdiv_source))
+                panic("failed to get pwm-tdiv clock for source timer");
+
+        clk_enable(tin_source);
+}
+
+static void __init s5p_timer_init(void)
+{
+        s5p_timer_resources();
+        s5p_clockevent_init();
+        s5p_clocksource_init();
+}
+
+struct sys_timer s5p_timer = {
+        .init           = s5p_timer_init,
+};
diff --git a/arch/arm/plat-s5p/setup-mipiphy.c b/arch/arm/plat-s5p/setup-mipiphy.c
new file mode 100644
index 00000000000..683c466c0e6
--- /dev/null
+++ b/arch/arm/plat-s5p/setup-mipiphy.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P - Helper functions for MIPI-CSIS and MIPI-DSIM D-PHY control
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <mach/regs-clock.h>
+
+static int __s5p_mipi_phy_control(struct platform_device *pdev,
+                                  bool on, u32 reset)
+{
+        static DEFINE_SPINLOCK(lock);
+        void __iomem *addr;
+        unsigned long flags;
+        int pid;
+        u32 cfg;
+
+        if (!pdev)
+                return -EINVAL;
+
+        pid = (pdev->id == -1) ? 0 : pdev->id;
+
+        if (pid != 0 && pid != 1)
+                return -EINVAL;
+
+        addr = S5P_MIPI_DPHY_CONTROL(pid);
+
+        spin_lock_irqsave(&lock, flags);
+
+        cfg = __raw_readl(addr);
+        cfg = on ? (cfg | reset) : (cfg & ~reset);
+        __raw_writel(cfg, addr);
+
+        if (on) {
+                cfg |= S5P_MIPI_DPHY_ENABLE;
+        } else if (!(cfg & (S5P_MIPI_DPHY_SRESETN |
+                            S5P_MIPI_DPHY_MRESETN) & ~reset)) {
+                cfg &= ~S5P_MIPI_DPHY_ENABLE;
+        }
+
+        __raw_writel(cfg, addr);
+        spin_unlock_irqrestore(&lock, flags);
+
+        return 0;
+}
+
+int s5p_csis_phy_enable(struct platform_device *pdev, bool on)
+{
+        return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN);
+}
+
+int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
+{
+        return __s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN);
+}
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
new file mode 100644
index 00000000000..e1cbc728c77
--- /dev/null
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -0,0 +1,312 @@
+/* linux/arch/arm/plat-s5p/sysmmu.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+
+#include <asm/pgtable.h>
+
+#include <mach/map.h>
+#include <mach/regs-sysmmu.h>
+#include <plat/sysmmu.h>
+
+#define CTRL_ENABLE     0x5
+#define CTRL_BLOCK      0x7
+#define CTRL_DISABLE    0x0
+
+static struct device *dev;
+
+static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
+        S5P_PAGE_FAULT_ADDR,
+        S5P_AR_FAULT_ADDR,
+        S5P_AW_FAULT_ADDR,
+        S5P_DEFAULT_SLAVE_ADDR,
+        S5P_AR_FAULT_ADDR,
+        S5P_AR_FAULT_ADDR,
+        S5P_AW_FAULT_ADDR,
+        S5P_AW_FAULT_ADDR
+};
+
+static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
+        "PAGE FAULT",
+        "AR MULTI-HIT FAULT",
+        "AW MULTI-HIT FAULT",
+        "BUS ERROR",
+        "AR SECURITY PROTECTION FAULT",
+        "AR ACCESS PROTECTION FAULT",
+        "AW SECURITY PROTECTION FAULT",
+        "AW ACCESS PROTECTION FAULT"
+};
+
+static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
+                enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+                unsigned long pgtable_base,
+                unsigned long fault_addr);
+
+/*
+ * If adjacent 2 bits are true, the system MMU is enabled.
+ * The system MMU is disabled, otherwise.
+ */
+static unsigned long sysmmu_states;
+
+static inline void set_sysmmu_active(sysmmu_ips ips)
+{
+        sysmmu_states |= 3 << (ips * 2);
+}
+
+static inline void set_sysmmu_inactive(sysmmu_ips ips)
+{
+        sysmmu_states &= ~(3 << (ips * 2));
+}
+
+static inline int is_sysmmu_active(sysmmu_ips ips)
+{
+        return sysmmu_states & (3 << (ips * 2));
+}
+
+static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
+
+static inline void sysmmu_block(sysmmu_ips ips)
+{
+        __raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
+        dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
+}
+
+static inline void sysmmu_unblock(sysmmu_ips ips)
+{
+        __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
+        dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
+}
+
+static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
+{
+        __raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
+        dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
+}
+
+static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
+{
+        if (unlikely(pgd == 0)) {
+                pgd = (unsigned long)ZERO_PAGE(0);
+                __raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
+        } else {
+                __raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
+        }
+
+        __raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
+
+        dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
+                                                sysmmu_ips_name[ips], pgd);
+        __sysmmu_tlb_invalidate(ips);
+}
+
+void sysmmu_set_fault_handler(sysmmu_ips ips,
+                        int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
+                                        unsigned long pgtable_base,
+                                        unsigned long fault_addr))
+{
+        BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
+        fault_handlers[ips] = handler;
+}
+
+static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
+{
+        /* SYSMMU is in blocked when interrupt occurred. */
+        unsigned long base = 0;
+        sysmmu_ips ips = (sysmmu_ips)dev_id;
+        enum S5P_SYSMMU_INTERRUPT_TYPE itype;
+
+        itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
+                __ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
+
+        BUG_ON(!((itype >= 0) && (itype < 8)));
+
+        dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
+                                                        sysmmu_ips_name[ips]);
+
+        if (fault_handlers[ips]) {
+                unsigned long addr;
+
+                base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
+                addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
+
+                if (fault_handlers[ips](itype, base, addr)) {
+                        __raw_writel(1 << itype,
+                                        sysmmusfrs[ips] + S5P_INT_CLEAR);
+                        dev_notice(dev, "%s from %s is resolved."
+                                        " Retrying translation.\n",
+                                sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
+                } else {
+                        base = 0;
+                }
+        }
+
+        sysmmu_unblock(ips);
+
+        if (!base)
+                dev_notice(dev, "%s from %s is not handled.\n",
+                        sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
+
+        return IRQ_HANDLED;
+}
+
+void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
+{
+        if (is_sysmmu_active(ips)) {
+                sysmmu_block(ips);
+                __sysmmu_set_ptbase(ips, pgd);
+                sysmmu_unblock(ips);
+        } else {
+                dev_dbg(dev, "%s is disabled. "
+                        "Skipping initializing page table base.\n",
+                                                sysmmu_ips_name[ips]);
+        }
+}
+
+void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
+{
+        if (!is_sysmmu_active(ips)) {
+                sysmmu_clk_enable(ips);
+
+                __sysmmu_set_ptbase(ips, pgd);
+
+                __raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
+
+                set_sysmmu_active(ips);
+                dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
+        } else {
+                dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
+        }
+}
+
+void s5p_sysmmu_disable(sysmmu_ips ips)
+{
+        if (is_sysmmu_active(ips)) {
+                __raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
+                set_sysmmu_inactive(ips);
+                sysmmu_clk_disable(ips);
+                dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
+        } else {
+                dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
+        }
+}
+
+void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
+{
+        if (is_sysmmu_active(ips)) {
+                sysmmu_block(ips);
+                __sysmmu_tlb_invalidate(ips);
+                sysmmu_unblock(ips);
+        } else {
+                dev_dbg(dev, "%s is disabled. "
+                        "Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
+        }
+}
+
+static int s5p_sysmmu_probe(struct platform_device *pdev)
+{
+        int i, ret;
+        struct resource *res, *mem;
+
+        dev = &pdev->dev;
+
+        for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
+                int irq;
+
+                sysmmu_clk_init(dev, i);
+                sysmmu_clk_disable(i);
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+                if (!res) {
+                        dev_err(dev, "Failed to get the resource of %s.\n",
+                                                        sysmmu_ips_name[i]);
+                        ret = -ENODEV;
+                        goto err_res;
+                }
+
+                mem = request_mem_region(res->start, resource_size(res),
+                                         pdev->name);
+                if (!mem) {
+                        dev_err(dev, "Failed to request the memory region of %s.\n",
+                                                        sysmmu_ips_name[i]);
+                        ret = -EBUSY;
+                        goto err_res;
+                }
+
+                sysmmusfrs[i] = ioremap(res->start, resource_size(res));
+                if (!sysmmusfrs[i]) {
+                        dev_err(dev, "Failed to ioremap() for %s.\n",
+                                                        sysmmu_ips_name[i]);
+                        ret = -ENXIO;
+                        goto err_reg;
+                }
+
+                irq = platform_get_irq(pdev, i);
+                if (irq <= 0) {
+                        dev_err(dev, "Failed to get the IRQ resource of %s.\n",
+                                                        sysmmu_ips_name[i]);
+                        ret = -ENOENT;
+                        goto err_map;
+                }
+
+                if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
+                                                pdev->name, (void *)i)) {
+                        dev_err(dev, "Failed to request IRQ for %s.\n",
+                                                        sysmmu_ips_name[i]);
+                        ret = -ENOENT;
+                        goto err_map;
+                }
+        }
+
+        return 0;
+
+err_map:
+        iounmap(sysmmusfrs[i]);
+err_reg:
+        release_mem_region(mem->start, resource_size(mem));
+err_res:
+        return ret;
+}
+
+static int s5p_sysmmu_remove(struct platform_device *pdev)
+{
+        return 0;
+}
+int s5p_sysmmu_runtime_suspend(struct device *dev)
+{
+        return 0;
+}
+
+int s5p_sysmmu_runtime_resume(struct device *dev)
+{
+        return 0;
+}
+
+const struct dev_pm_ops s5p_sysmmu_pm_ops = {
+        .runtime_suspend        = s5p_sysmmu_runtime_suspend,
+        .runtime_resume         = s5p_sysmmu_runtime_resume,
+};
+
+static struct platform_driver s5p_sysmmu_driver = {
+        .probe          = s5p_sysmmu_probe,
+        .remove         = s5p_sysmmu_remove,
+        .driver         = {
+                .owner          = THIS_MODULE,
+                .name           = "s5p-sysmmu",
+                .pm             = &s5p_sysmmu_pm_ops,
+        }
+};
+
+static int __init s5p_sysmmu_init(void)
+{
+        return platform_driver_register(&s5p_sysmmu_driver);
+}
+arch_initcall(s5p_sysmmu_init);