4 files changed, 86 insertions, 74 deletions

diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
index 7956fd3bb19..a22758194e6 100644
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -24,8 +24,8 @@
 
 #define S3C_IRQ(x)      ((x) + S3C_IRQ_OFFSET)
 
-#define S3C_VIC0_BASE   S3C_IRQ(0)
-#define S3C_VIC1_BASE   S3C_IRQ(32)
+#define IRQ_VIC0_BASE   S3C_IRQ(0)
+#define IRQ_VIC1_BASE   S3C_IRQ(32)
 
 /* UART interrupts, each UART has 4 intterupts per channel so
  * use the space between the ISA and S3C main interrupts. Note, these
@@ -59,8 +59,8 @@
 
 /* VIC based IRQs */
 
-#define S3C64XX_IRQ_VIC0(x)     (S3C_VIC0_BASE + (x))
-#define S3C64XX_IRQ_VIC1(x)     (S3C_VIC1_BASE + (x))
+#define S3C64XX_IRQ_VIC0(x)     (IRQ_VIC0_BASE + (x))
+#define S3C64XX_IRQ_VIC1(x)     (IRQ_VIC1_BASE + (x))
 
 /* VIC0 */
 
@@ -198,7 +198,11 @@
  * interrupt controllers). */
 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 
+#ifdef CONFIG_SMDK6410_WM1190_EV1
+#define IRQ_BOARD_NR 64
+#else
 #define IRQ_BOARD_NR 16
+#endif
 
 #define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR)
 
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index ff46e7fa957..3ef62741e5d 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -35,14 +35,6 @@
 #define S3C_MEM0_GATE           S3C_CLKREG(0x3C)
 
 /* CLKDIV0 */
-#define S3C6400_CLKDIV0_MFC_MASK        (0xf << 28)
-#define S3C6400_CLKDIV0_MFC_SHIFT       (28)
-#define S3C6400_CLKDIV0_JPEG_MASK       (0xf << 24)
-#define S3C6400_CLKDIV0_JPEG_SHIFT      (24)
-#define S3C6400_CLKDIV0_CAM_MASK        (0xf << 20)
-#define S3C6400_CLKDIV0_CAM_SHIFT       (20)
-#define S3C6400_CLKDIV0_SECURITY_MASK   (0x3 << 18)
-#define S3C6400_CLKDIV0_SECURITY_SHIFT  (18)
 #define S3C6400_CLKDIV0_PCLK_MASK       (0xf << 12)
 #define S3C6400_CLKDIV0_PCLK_SHIFT      (12)
 #define S3C6400_CLKDIV0_HCLK2_MASK      (0x7 << 9)
@@ -51,42 +43,11 @@
 #define S3C6400_CLKDIV0_HCLK_SHIFT      (8)
 #define S3C6400_CLKDIV0_MPLL_MASK       (0x1 << 4)
 #define S3C6400_CLKDIV0_MPLL_SHIFT      (4)
+
 #define S3C6400_CLKDIV0_ARM_MASK        (0x7 << 0)
 #define S3C6410_CLKDIV0_ARM_MASK        (0xf << 0)
 #define S3C6400_CLKDIV0_ARM_SHIFT       (0)
 
-/* CLKDIV1 */
-#define S3C6410_CLKDIV1_FIMC_MASK       (0xf << 24)
-#define S3C6410_CLKDIV1_FIMC_SHIFT      (24)
-#define S3C6400_CLKDIV1_UHOST_MASK      (0xf << 20)
-#define S3C6400_CLKDIV1_UHOST_SHIFT     (20)
-#define S3C6400_CLKDIV1_SCALER_MASK     (0xf << 16)
-#define S3C6400_CLKDIV1_SCALER_SHIFT    (16)
-#define S3C6400_CLKDIV1_LCD_MASK        (0xf << 12)
-#define S3C6400_CLKDIV1_LCD_SHIFT       (12)
-#define S3C6400_CLKDIV1_MMC2_MASK       (0xf << 8)
-#define S3C6400_CLKDIV1_MMC2_SHIFT      (8)
-#define S3C6400_CLKDIV1_MMC1_MASK       (0xf << 4)
-#define S3C6400_CLKDIV1_MMC1_SHIFT      (4)
-#define S3C6400_CLKDIV1_MMC0_MASK       (0xf << 0)
-#define S3C6400_CLKDIV1_MMC0_SHIFT      (0)
-
-/* CLKDIV2 */
-#define S3C6410_CLKDIV2_AUDIO2_MASK     (0xf << 24)
-#define S3C6410_CLKDIV2_AUDIO2_SHIFT    (24)
-#define S3C6400_CLKDIV2_IRDA_MASK       (0xf << 20)
-#define S3C6400_CLKDIV2_IRDA_SHIFT      (20)
-#define S3C6400_CLKDIV2_UART_MASK       (0xf << 16)
-#define S3C6400_CLKDIV2_UART_SHIFT      (16)
-#define S3C6400_CLKDIV2_AUDIO1_MASK     (0xf << 12)
-#define S3C6400_CLKDIV2_AUDIO1_SHIFT    (12)
-#define S3C6400_CLKDIV2_AUDIO0_MASK     (0xf << 8)
-#define S3C6400_CLKDIV2_AUDIO0_SHIFT    (8)
-#define S3C6400_CLKDIV2_SPI1_MASK       (0xf << 4)
-#define S3C6400_CLKDIV2_SPI1_SHIFT      (4)
-#define S3C6400_CLKDIV2_SPI0_MASK       (0xf << 0)
-#define S3C6400_CLKDIV2_SPI0_SHIFT      (0)
-
 /* HCLK GATE Registers */
 #define S3C_CLKCON_HCLK_3DSE    (1<<31)
 #define S3C_CLKCON_HCLK_UHOST   (1<<29)
@@ -192,34 +153,4 @@
 #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT  (2)
 #define S3C6400_CLKSRC_MFC              (1 << 4)
 
-#define S3C6410_CLKSRC_TV27_MASK        (0x1 << 31)
-#define S3C6410_CLKSRC_TV27_SHIFT       (31)
-#define S3C6410_CLKSRC_DAC27_MASK       (0x1 << 30)
-#define S3C6410_CLKSRC_DAC27_SHIFT      (30)
-#define S3C6400_CLKSRC_SCALER_MASK      (0x3 << 28)
-#define S3C6400_CLKSRC_SCALER_SHIFT     (28)
-#define S3C6400_CLKSRC_LCD_MASK         (0x3 << 26)
-#define S3C6400_CLKSRC_LCD_SHIFT        (26)
-#define S3C6400_CLKSRC_IRDA_MASK        (0x3 << 24)
-#define S3C6400_CLKSRC_IRDA_SHIFT       (24)
-#define S3C6400_CLKSRC_MMC2_MASK        (0x3 << 22)
-#define S3C6400_CLKSRC_MMC2_SHIFT       (22)
-#define S3C6400_CLKSRC_MMC1_MASK        (0x3 << 20)
-#define S3C6400_CLKSRC_MMC1_SHIFT       (20)
-#define S3C6400_CLKSRC_MMC0_MASK        (0x3 << 18)
-#define S3C6400_CLKSRC_MMC0_SHIFT       (18)
-#define S3C6400_CLKSRC_SPI1_MASK        (0x3 << 16)
-#define S3C6400_CLKSRC_SPI1_SHIFT       (16)
-#define S3C6400_CLKSRC_SPI0_MASK        (0x3 << 14)
-#define S3C6400_CLKSRC_SPI0_SHIFT       (14)
-#define S3C6400_CLKSRC_UART_MASK        (0x1 << 13)
-#define S3C6400_CLKSRC_UART_SHIFT       (13)
-#define S3C6400_CLKSRC_AUDIO1_MASK      (0x7 << 10)
-#define S3C6400_CLKSRC_AUDIO1_SHIFT     (10)
-#define S3C6400_CLKSRC_AUDIO0_MASK      (0x7 << 7)
-#define S3C6400_CLKSRC_AUDIO0_SHIFT     (7)
-#define S3C6400_CLKSRC_UHOST_MASK       (0x3 << 5)
-#define S3C6400_CLKSRC_UHOST_SHIFT      (5)
-
-
 #endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-srom.h b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h
new file mode 100644
index 00000000000..756731b3629
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h
@@ -0,0 +1,59 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
+ *
+ * Copyright 2009 Andy Green <andy@warmcat.com>
+ *
+ * S3C64XX SROM definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_SROM_H
+#define __PLAT_REGS_SROM_H __FILE__
+
+#define S3C64XX_SROMREG(x)      (S3C_VA_MEM + (x))
+
+#define S3C64XX_SROM_BW         S3C64XX_SROMREG(0)
+#define S3C64XX_SROM_BC0        S3C64XX_SROMREG(4)
+#define S3C64XX_SROM_BC1        S3C64XX_SROMREG(8)
+#define S3C64XX_SROM_BC2        S3C64XX_SROMREG(0xc)
+#define S3C64XX_SROM_BC3        S3C64XX_SROMREG(0x10)
+#define S3C64XX_SROM_BC4        S3C64XX_SROMREG(0x14)
+#define S3C64XX_SROM_BC5        S3C64XX_SROMREG(0x18)
+
+/*
+ * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
+ */
+
+#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT       0
+#define S3C64XX_SROM_BW__WAITENABLE__SHIFT      2
+#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT      3
+#define S3C64XX_SROM_BW__CS_MASK 0xf
+
+#define S3C64XX_SROM_BW__NCS0__SHIFT    0
+#define S3C64XX_SROM_BW__NCS1__SHIFT    4
+#define S3C64XX_SROM_BW__NCS2__SHIFT    8
+#define S3C64XX_SROM_BW__NCS3__SHIFT    0xc
+#define S3C64XX_SROM_BW__NCS4__SHIFT    0x10
+
+/*
+ * applies to same to BCS0 - BCS4
+ */
+
+#define S3C64XX_SROM_BCX__PMC__SHIFT    0
+#define S3C64XX_SROM_BCX__PMC__MASK     3
+#define S3C64XX_SROM_BCX__TACP__SHIFT   4
+#define S3C64XX_SROM_BCX__TACP__MASK    0xf
+#define S3C64XX_SROM_BCX__TCAH__SHIFT   8
+#define S3C64XX_SROM_BCX__TCAH__MASK    0xf
+#define S3C64XX_SROM_BCX__TCOH__SHIFT   12
+#define S3C64XX_SROM_BCX__TCOH__MASK    0xf
+#define S3C64XX_SROM_BCX__TACC__SHIFT   16
+#define S3C64XX_SROM_BCX__TACC__MASK    0x1f
+#define S3C64XX_SROM_BCX__TCOS__SHIFT   24
+#define S3C64XX_SROM_BCX__TCOS__MASK    0xf
+#define S3C64XX_SROM_BCX__TACS__SHIFT   28
+#define S3C64XX_SROM_BCX__TACS__MASK    0xf
+
+#endif /* _PLAT_REGS_SROM_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
new file mode 100644
index 00000000000..524bdae3f62
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h
+ *
+ * Copyright (C) 2009 Samsung Electronics Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __S3C64XX_PLAT_SPI_CLKS_H
+#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
+
+#define S3C64XX_SPI_SRCCLK_PCLK         0
+#define S3C64XX_SPI_SRCCLK_SPIBUS       1
+#define S3C64XX_SPI_SRCCLK_48M          2
+
+#endif /* __S3C64XX_PLAT_SPI_CLKS_H */