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Diffstat (limited to 'arch/arm/plat-s3c24xx/s3c2443-clock.c')
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c39
1 files changed, 26 insertions, 13 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 5a21b15b2a9..95e68190d59 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -297,13 +297,6 @@ static struct clksrc_clk clk_usb_bus_host = {
297 297
298static struct clksrc_clk clksrc_clks[] = { 298static struct clksrc_clk clksrc_clks[] = {
299 { 299 {
300 /* ART baud-rate clock sourced from esysclk via a divisor */
301 .clk = {
302 .name = "uartclk",
303 .parent = &clk_esysclk.clk,
304 },
305 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
306 }, {
307 /* camera interface bus-clock, divided down from esysclk */ 300 /* camera interface bus-clock, divided down from esysclk */
308 .clk = { 301 .clk = {
309 .name = "camif-upll", /* same as 2440 name */ 302 .name = "camif-upll", /* same as 2440 name */
@@ -323,6 +316,15 @@ static struct clksrc_clk clksrc_clks[] = {
323 }, 316 },
324}; 317};
325 318
319static struct clksrc_clk clk_esys_uart = {
320 /* ART baud-rate clock sourced from esysclk via a divisor */
321 .clk = {
322 .name = "uartclk",
323 .parent = &clk_esysclk.clk,
324 },
325 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
326};
327
326static struct clk clk_i2s_ext = { 328static struct clk clk_i2s_ext = {
327 .name = "i2s-ext", 329 .name = "i2s-ext",
328}; 330};
@@ -425,12 +427,6 @@ static struct clk init_clocks[] = {
425 .enable = s3c2443_clkcon_enable_h, 427 .enable = s3c2443_clkcon_enable_h,
426 .ctrlbit = S3C2443_HCLKCON_DMA5, 428 .ctrlbit = S3C2443_HCLKCON_DMA5,
427 }, { 429 }, {
428 .name = "hsmmc",
429 .devname = "s3c-sdhci.1",
430 .parent = &clk_h,
431 .enable = s3c2443_clkcon_enable_h,
432 .ctrlbit = S3C2443_HCLKCON_HSMMC,
433 }, {
434 .name = "gpio", 430 .name = "gpio",
435 .parent = &clk_p, 431 .parent = &clk_p,
436 .enable = s3c2443_clkcon_enable_p, 432 .enable = s3c2443_clkcon_enable_p,
@@ -512,6 +508,14 @@ static struct clk init_clocks[] = {
512 } 508 }
513}; 509};
514 510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
515static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) 519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
516{ 520{
517 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; 521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -577,6 +581,7 @@ static struct clk *clks[] __initdata = {
577 &clk_epll, 581 &clk_epll,
578 &clk_usb_bus, 582 &clk_usb_bus,
579 &clk_armdiv, 583 &clk_armdiv,
584 &hsmmc1_clk,
580}; 585};
581 586
582static struct clksrc_clk *clksrcs[] __initdata = { 587static struct clksrc_clk *clksrcs[] __initdata = {
@@ -589,6 +594,13 @@ static struct clksrc_clk *clksrcs[] __initdata = {
589 &clk_arm, 594 &clk_arm,
590}; 595};
591 596
597static struct clk_lookup s3c2443_clk_lookup[] = {
598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
602};
603
592void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
593 unsigned int *divs, int nr_divs, 605 unsigned int *divs, int nr_divs,
594 int divmask) 606 int divmask)
@@ -618,6 +630,7 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
618 /* See s3c2443/etc notes on disabling clocks at init time */ 630 /* See s3c2443/etc notes on disabling clocks at init time */
619 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 631 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
620 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 632 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
633 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
621 634
622 s3c2443_common_setup_clocks(get_mpll); 635 s3c2443_common_setup_clocks(get_mpll);
623} 636}