aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/include/plat/usb.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/include/plat/usb.h')
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h296
1 files changed, 296 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
new file mode 100644
index 00000000000..17d3c939775
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -0,0 +1,296 @@
1// include/asm-arm/mach-omap/usb.h
2
3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H
5
6#include <linux/usb/musb.h>
7#include <plat/board.h>
8
9#define OMAP3_HS_USB_PORTS 3
10
11enum usbhs_omap_port_mode {
12 OMAP_USBHS_PORT_MODE_UNUSED,
13 OMAP_EHCI_PORT_MODE_PHY,
14 OMAP_EHCI_PORT_MODE_TLL,
15 OMAP_EHCI_PORT_MODE_HSIC,
16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
18 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
19 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
22 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
23 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
26};
27
28struct usbhs_omap_board_data {
29 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
30
31 /* have to be valid if phy_reset is true and portx is in phy mode */
32 int reset_gpio_port[OMAP3_HS_USB_PORTS];
33
34 /* Set this to true for ES2.x silicon */
35 unsigned es2_compatibility:1;
36
37 unsigned phy_reset:1;
38
39 /*
40 * Regulators for USB PHYs.
41 * Each PHY can have a separate regulator.
42 */
43 struct regulator *regulator[OMAP3_HS_USB_PORTS];
44};
45
46struct ehci_hcd_omap_platform_data {
47 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
48 int reset_gpio_port[OMAP3_HS_USB_PORTS];
49 struct regulator *regulator[OMAP3_HS_USB_PORTS];
50 unsigned phy_reset:1;
51};
52
53struct ohci_hcd_omap_platform_data {
54 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
55 unsigned es2_compatibility:1;
56};
57
58struct usbhs_omap_platform_data {
59 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
60
61 struct ehci_hcd_omap_platform_data *ehci_data;
62 struct ohci_hcd_omap_platform_data *ohci_data;
63};
64/*-------------------------------------------------------------------------*/
65
66#define OMAP1_OTG_BASE 0xfffb0400
67#define OMAP1_UDC_BASE 0xfffb4000
68#define OMAP1_OHCI_BASE 0xfffba000
69
70#define OMAP2_OHCI_BASE 0x4805e000
71#define OMAP2_UDC_BASE 0x4805e200
72#define OMAP2_OTG_BASE 0x4805e300
73
74#ifdef CONFIG_ARCH_OMAP1
75
76#define OTG_BASE OMAP1_OTG_BASE
77#define UDC_BASE OMAP1_UDC_BASE
78#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
79
80#else
81
82#define OTG_BASE OMAP2_OTG_BASE
83#define UDC_BASE OMAP2_UDC_BASE
84#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
85
86struct omap_musb_board_data {
87 u8 interface_type;
88 u8 mode;
89 u16 power;
90 unsigned extvbus:1;
91 void (*set_phy_power)(u8 on);
92 void (*clear_irq)(void);
93 void (*set_mode)(u8 mode);
94 void (*reset)(void);
95};
96
97enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
98
99extern void usb_musb_init(struct omap_musb_board_data *board_data);
100
101extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
102
103extern int omap_usbhs_enable(struct device *dev);
104extern void omap_usbhs_disable(struct device *dev);
105
106extern int omap4430_phy_power(struct device *dev, int ID, int on);
107extern int omap4430_phy_set_clk(struct device *dev, int on);
108extern int omap4430_phy_init(struct device *dev);
109extern int omap4430_phy_exit(struct device *dev);
110extern int omap4430_phy_suspend(struct device *dev, int suspend);
111#endif
112
113extern void am35x_musb_reset(void);
114extern void am35x_musb_phy_power(u8 on);
115extern void am35x_musb_clear_irq(void);
116extern void am35x_set_mode(u8 musb_mode);
117
118/*
119 * FIXME correct answer depends on hmc_mode,
120 * as does (on omap1) any nonzero value for config->otg port number
121 */
122#ifdef CONFIG_USB_GADGET_OMAP
123#define is_usb0_device(config) 1
124#else
125#define is_usb0_device(config) 0
126#endif
127
128void omap_otg_init(struct omap_usb_config *config);
129
130#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
131void omap1_usb_init(struct omap_usb_config *pdata);
132#else
133static inline void omap1_usb_init(struct omap_usb_config *pdata)
134{
135}
136#endif
137
138#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
139void omap2_usbfs_init(struct omap_usb_config *pdata);
140#else
141static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
142{
143}
144#endif
145
146/*-------------------------------------------------------------------------*/
147
148/*
149 * OTG and transceiver registers, for OMAPs starting with ARM926
150 */
151#define OTG_REV (OTG_BASE + 0x00)
152#define OTG_SYSCON_1 (OTG_BASE + 0x04)
153# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
154# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
155# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
156# define OTG_IDLE_EN (1 << 15)
157# define HST_IDLE_EN (1 << 14)
158# define DEV_IDLE_EN (1 << 13)
159# define OTG_RESET_DONE (1 << 2)
160# define OTG_SOFT_RESET (1 << 1)
161#define OTG_SYSCON_2 (OTG_BASE + 0x08)
162# define OTG_EN (1 << 31)
163# define USBX_SYNCHRO (1 << 30)
164# define OTG_MST16 (1 << 29)
165# define SRP_GPDATA (1 << 28)
166# define SRP_GPDVBUS (1 << 27)
167# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
168# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
169# define B_ASE_BRST(w) (((w)>>16)&0x07)
170# define SRP_DPW (1 << 14)
171# define SRP_DATA (1 << 13)
172# define SRP_VBUS (1 << 12)
173# define OTG_PADEN (1 << 10)
174# define HMC_PADEN (1 << 9)
175# define UHOST_EN (1 << 8)
176# define HMC_TLLSPEED (1 << 7)
177# define HMC_TLLATTACH (1 << 6)
178# define OTG_HMC(w) (((w)>>0)&0x3f)
179#define OTG_CTRL (OTG_BASE + 0x0c)
180# define OTG_USB2_EN (1 << 29)
181# define OTG_USB2_DP (1 << 28)
182# define OTG_USB2_DM (1 << 27)
183# define OTG_USB1_EN (1 << 26)
184# define OTG_USB1_DP (1 << 25)
185# define OTG_USB1_DM (1 << 24)
186# define OTG_USB0_EN (1 << 23)
187# define OTG_USB0_DP (1 << 22)
188# define OTG_USB0_DM (1 << 21)
189# define OTG_ASESSVLD (1 << 20)
190# define OTG_BSESSEND (1 << 19)
191# define OTG_BSESSVLD (1 << 18)
192# define OTG_VBUSVLD (1 << 17)
193# define OTG_ID (1 << 16)
194# define OTG_DRIVER_SEL (1 << 15)
195# define OTG_A_SETB_HNPEN (1 << 12)
196# define OTG_A_BUSREQ (1 << 11)
197# define OTG_B_HNPEN (1 << 9)
198# define OTG_B_BUSREQ (1 << 8)
199# define OTG_BUSDROP (1 << 7)
200# define OTG_PULLDOWN (1 << 5)
201# define OTG_PULLUP (1 << 4)
202# define OTG_DRV_VBUS (1 << 3)
203# define OTG_PD_VBUS (1 << 2)
204# define OTG_PU_VBUS (1 << 1)
205# define OTG_PU_ID (1 << 0)
206#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
207# define DRIVER_SWITCH (1 << 15)
208# define A_VBUS_ERR (1 << 13)
209# define A_REQ_TMROUT (1 << 12)
210# define A_SRP_DETECT (1 << 11)
211# define B_HNP_FAIL (1 << 10)
212# define B_SRP_TMROUT (1 << 9)
213# define B_SRP_DONE (1 << 8)
214# define B_SRP_STARTED (1 << 7)
215# define OPRT_CHG (1 << 0)
216#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
217 // same bits as in IRQ_EN
218#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
219# define OTGVPD (1 << 14)
220# define OTGVPU (1 << 13)
221# define OTGPUID (1 << 12)
222# define USB2VDR (1 << 10)
223# define USB2PDEN (1 << 9)
224# define USB2PUEN (1 << 8)
225# define USB1VDR (1 << 6)
226# define USB1PDEN (1 << 5)
227# define USB1PUEN (1 << 4)
228# define USB0VDR (1 << 2)
229# define USB0PDEN (1 << 1)
230# define USB0PUEN (1 << 0)
231#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
232#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
233
234/*-------------------------------------------------------------------------*/
235
236/* OMAP1 */
237#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
238# define CONF_USB2_UNI_R (1 << 8)
239# define CONF_USB1_UNI_R (1 << 7)
240# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
241# define CONF_USB0_ISOLATE_R (1 << 3)
242# define CONF_USB_PWRDN_DM_R (1 << 2)
243# define CONF_USB_PWRDN_DP_R (1 << 1)
244
245/* OMAP2 */
246# define USB_UNIDIR 0x0
247# define USB_UNIDIR_TLL 0x1
248# define USB_BIDIR 0x2
249# define USB_BIDIR_TLL 0x3
250# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
251# define USBT2TLL5PI (1 << 17)
252# define USB0PUENACTLOI (1 << 16)
253# define USBSTANDBYCTRL (1 << 15)
254/* AM35x */
255/* USB 2.0 PHY Control */
256#define CONF2_PHY_GPIOMODE (1 << 23)
257#define CONF2_OTGMODE (3 << 14)
258#define CONF2_NO_OVERRIDE (0 << 14)
259#define CONF2_FORCE_HOST (1 << 14)
260#define CONF2_FORCE_DEVICE (2 << 14)
261#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
262#define CONF2_SESENDEN (1 << 13)
263#define CONF2_VBDTCTEN (1 << 12)
264#define CONF2_REFFREQ_24MHZ (2 << 8)
265#define CONF2_REFFREQ_26MHZ (7 << 8)
266#define CONF2_REFFREQ_13MHZ (6 << 8)
267#define CONF2_REFFREQ (0xf << 8)
268#define CONF2_PHYCLKGD (1 << 7)
269#define CONF2_VBUSSENSE (1 << 6)
270#define CONF2_PHY_PLLON (1 << 5)
271#define CONF2_RESET (1 << 4)
272#define CONF2_PHYPWRDN (1 << 3)
273#define CONF2_OTGPWRDN (1 << 2)
274#define CONF2_DATPOL (1 << 1)
275
276#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
277u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
278u32 omap1_usb1_init(unsigned nwires);
279u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
280#else
281static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
282{
283 return 0;
284}
285static inline u32 omap1_usb1_init(unsigned nwires)
286{
287 return 0;
288
289}
290static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
291{
292 return 0;
293}
294#endif
295
296#endif /* __ASM_ARCH_OMAP_USB_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-20 11:39:18 -0500