1 files changed, 116 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
new file mode 100644
index 00000000000..2682043f5a5
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -0,0 +1,116 @@
+/*
+ * Driver for OMAP-UART controller.
+ * Based on drivers/serial/8250.c
+ *
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * Authors:
+ *      Govindraj R     <govindraj.raja@ti.com>
+ *      Thara Gopinath  <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __OMAP_SERIAL_H__
+#define __OMAP_SERIAL_H__
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <plat/mux.h>
+#define DRIVER_NAME     "omap_uart"
+/*
+ * Use tty device name as ttyO, [O -> OMAP]
+ * in bootargs we specify as console=ttyO0 if uart1
+ * is used as console uart.
+ */
+#define OMAP_SERIAL_NAME        "ttyO"
+#define OMAP_MODE13X_SPEED      230400
+/* WER = 0x7F
+ * Enable module level wakeup in WER reg
+ */
+#define OMAP_UART_WER_MOD_WKUP  0X7F
+/* Enable XON/XOFF flow control on output */
+#define OMAP_UART_SW_TX         0x04
+/* Enable XON/XOFF flow control on input */
+#define OMAP_UART_SW_RX         0x04
+#define OMAP_UART_SYSC_RESET    0X07
+#define OMAP_UART_TCR_TRIG      0X0F
+#define OMAP_UART_SW_CLR        0XF0
+#define OMAP_UART_FIFO_CLR      0X06
+#define OMAP_UART_DMA_CH_FREE   -1
+#define RX_TIMEOUT              (3 * HZ)
+#define OMAP_MAX_HSUART_PORTS   4
+#define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
+struct omap_uart_port_info {
+        bool                    dma_enabled;    /* To specify DMA Mode */
+        unsigned int            uartclk;        /* UART clock rate */
+        void __iomem            *membase;       /* ioremap cookie or NULL */
+        resource_size_t         mapbase;        /* resource base */
+        unsigned long           irqflags;       /* request_irq flags */
+        upf_t                   flags;          /* UPF_* flags */
+};
+struct uart_omap_dma {
+        u8                      uart_dma_tx;
+        u8                      uart_dma_rx;
+        int                     rx_dma_channel;
+        int                     tx_dma_channel;
+        dma_addr_t              rx_buf_dma_phys;
+        dma_addr_t              tx_buf_dma_phys;
+        unsigned int            uart_base;
+        /*
+         * Buffer for rx dma.It is not required for tx because the buffer
+         * comes from port structure.
+         */
+        unsigned char           *rx_buf;
+        unsigned int            prev_rx_dma_pos;
+        int                     tx_buf_size;
+        int                     tx_dma_used;
+        int                     rx_dma_used;
+        spinlock_t              tx_lock;
+        spinlock_t              rx_lock;
+        /* timer to poll activity on rx dma */
+        struct timer_list       rx_timer;
+        int                     rx_buf_size;
+        int                     rx_timeout;
+};
+struct uart_omap_port {
+        struct uart_port        port;
+        struct uart_omap_dma    uart_dma;
+        struct platform_device  *pdev;
+        unsigned char           ier;
+        unsigned char           lcr;
+        unsigned char           mcr;
+        unsigned char           fcr;
+        unsigned char           efr;
+        int                     use_dma;
+        /*
+         * Some bits in registers are cleared on a read, so they must
+         * be saved whenever the register is read but the bits will not
+         * be immediately processed.
+         */
+        unsigned int            lsr_break_flag;
+        unsigned char           msr_saved_flags;
+        char                    name[20];
+        unsigned long           port_activity;
+};
+#endif /* __OMAP_SERIAL_H__ */

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h new file mode 100644 index 00000000000..2682043f5a5 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -0,0 +1,116 @@
	1	/*
	2	* Driver for OMAP-UART controller.
	3	* Based on drivers/serial/8250.c
	4	*
	5	* Copyright (C) 2010 Texas Instruments.
	6	*
	7	* Authors:
	8	* Govindraj R <govindraj.raja@ti.com>
	9	* Thara Gopinath <thara@ti.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#ifndef __OMAP_SERIAL_H__
	18	#define __OMAP_SERIAL_H__
	19
	20	#include <linux/serial_core.h>
	21	#include <linux/platform_device.h>
	22
	23	#include <plat/mux.h>
	24
	25	#define DRIVER_NAME "omap_uart"
	26
	27	/*
	28	* Use tty device name as ttyO, [O -> OMAP]
	29	* in bootargs we specify as console=ttyO0 if uart1
	30	* is used as console uart.
	31	*/
	32	#define OMAP_SERIAL_NAME "ttyO"
	33
	34	#define OMAP_MODE13X_SPEED 230400
	35
	36	/* WER = 0x7F
	37	* Enable module level wakeup in WER reg
	38	*/
	39	#define OMAP_UART_WER_MOD_WKUP 0X7F
	40
	41	/* Enable XON/XOFF flow control on output */
	42	#define OMAP_UART_SW_TX 0x04
	43
	44	/* Enable XON/XOFF flow control on input */
	45	#define OMAP_UART_SW_RX 0x04
	46
	47	#define OMAP_UART_SYSC_RESET 0X07
	48	#define OMAP_UART_TCR_TRIG 0X0F
	49	#define OMAP_UART_SW_CLR 0XF0
	50	#define OMAP_UART_FIFO_CLR 0X06
	51
	52	#define OMAP_UART_DMA_CH_FREE -1
	53
	54	#define RX_TIMEOUT (3 * HZ)
	55	#define OMAP_MAX_HSUART_PORTS 4
	56
	57	#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
	58
	59	struct omap_uart_port_info {
	60	bool dma_enabled; /* To specify DMA Mode */
	61	unsigned int uartclk; /* UART clock rate */
	62	void __iomem membase; / ioremap cookie or NULL */
	63	resource_size_t mapbase; /* resource base */
	64	unsigned long irqflags; /* request_irq flags */
	65	upf_t flags; /* UPF_* flags */
	66	};
	67
	68	struct uart_omap_dma {
	69	u8 uart_dma_tx;
	70	u8 uart_dma_rx;
	71	int rx_dma_channel;
	72	int tx_dma_channel;
	73	dma_addr_t rx_buf_dma_phys;
	74	dma_addr_t tx_buf_dma_phys;
	75	unsigned int uart_base;
	76	/*
	77	* Buffer for rx dma.It is not required for tx because the buffer
	78	* comes from port structure.
	79	*/
	80	unsigned char *rx_buf;
	81	unsigned int prev_rx_dma_pos;
	82	int tx_buf_size;
	83	int tx_dma_used;
	84	int rx_dma_used;
	85	spinlock_t tx_lock;
	86	spinlock_t rx_lock;
	87	/* timer to poll activity on rx dma */
	88	struct timer_list rx_timer;
	89	int rx_buf_size;
	90	int rx_timeout;
	91	};
	92
	93	struct uart_omap_port {
	94	struct uart_port port;
	95	struct uart_omap_dma uart_dma;
	96	struct platform_device *pdev;
	97
	98	unsigned char ier;
	99	unsigned char lcr;
	100	unsigned char mcr;
	101	unsigned char fcr;
	102	unsigned char efr;
	103
	104	int use_dma;
	105	/*
	106	* Some bits in registers are cleared on a read, so they must
	107	* be saved whenever the register is read but the bits will not
	108	* be immediately processed.
	109	*/
	110	unsigned int lsr_break_flag;
	111	unsigned char msr_saved_flags;
	112	char name[20];
	113	unsigned long port_activity;
	114	};
	115
	116	#endif /* __OMAP_SERIAL_H__ */