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Diffstat (limited to 'arch/arm/plat-omap/gpio.c')
-rw-r--r--arch/arm/plat-omap/gpio.c413
1 files changed, 98 insertions, 315 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 2b0d9010982..6f53dee98a9 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -21,6 +21,8 @@
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
24 26
25#include <mach/hardware.h> 27#include <mach/hardware.h>
26#include <asm/irq.h> 28#include <asm/irq.h>
@@ -32,7 +34,6 @@
32/* 34/*
33 * OMAP1510 GPIO registers 35 * OMAP1510 GPIO registers
34 */ 36 */
35#define OMAP1510_GPIO_BASE 0xfffce000
36#define OMAP1510_GPIO_DATA_INPUT 0x00 37#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04 38#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08 39#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -46,10 +47,6 @@
46/* 47/*
47 * OMAP1610 specific GPIO registers 48 * OMAP1610 specific GPIO registers
48 */ 49 */
49#define OMAP1610_GPIO1_BASE 0xfffbe400
50#define OMAP1610_GPIO2_BASE 0xfffbec00
51#define OMAP1610_GPIO3_BASE 0xfffbb400
52#define OMAP1610_GPIO4_BASE 0xfffbbc00
53#define OMAP1610_GPIO_REVISION 0x0000 50#define OMAP1610_GPIO_REVISION 0x0000
54#define OMAP1610_GPIO_SYSCONFIG 0x0010 51#define OMAP1610_GPIO_SYSCONFIG 0x0010
55#define OMAP1610_GPIO_SYSSTATUS 0x0014 52#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -71,12 +68,6 @@
71/* 68/*
72 * OMAP7XX specific GPIO registers 69 * OMAP7XX specific GPIO registers
73 */ 70 */
74#define OMAP7XX_GPIO1_BASE 0xfffbc000
75#define OMAP7XX_GPIO2_BASE 0xfffbc800
76#define OMAP7XX_GPIO3_BASE 0xfffbd000
77#define OMAP7XX_GPIO4_BASE 0xfffbd800
78#define OMAP7XX_GPIO5_BASE 0xfffbe000
79#define OMAP7XX_GPIO6_BASE 0xfffbe800
80#define OMAP7XX_GPIO_DATA_INPUT 0x00 71#define OMAP7XX_GPIO_DATA_INPUT 0x00
81#define OMAP7XX_GPIO_DATA_OUTPUT 0x04 72#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82#define OMAP7XX_GPIO_DIR_CONTROL 0x08 73#define OMAP7XX_GPIO_DIR_CONTROL 0x08
@@ -84,25 +75,10 @@
84#define OMAP7XX_GPIO_INT_MASK 0x10 75#define OMAP7XX_GPIO_INT_MASK 0x10
85#define OMAP7XX_GPIO_INT_STATUS 0x14 76#define OMAP7XX_GPIO_INT_STATUS 0x14
86 77
87#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
88
89/* 78/*
90 * omap24xx specific GPIO registers 79 * omap2+ specific GPIO registers
91 */ 80 */
92#define OMAP242X_GPIO1_BASE 0x48018000
93#define OMAP242X_GPIO2_BASE 0x4801a000
94#define OMAP242X_GPIO3_BASE 0x4801c000
95#define OMAP242X_GPIO4_BASE 0x4801e000
96
97#define OMAP243X_GPIO1_BASE 0x4900C000
98#define OMAP243X_GPIO2_BASE 0x4900E000
99#define OMAP243X_GPIO3_BASE 0x49010000
100#define OMAP243X_GPIO4_BASE 0x49012000
101#define OMAP243X_GPIO5_BASE 0x480B6000
102
103#define OMAP24XX_GPIO_REVISION 0x0000 81#define OMAP24XX_GPIO_REVISION 0x0000
104#define OMAP24XX_GPIO_SYSCONFIG 0x0010
105#define OMAP24XX_GPIO_SYSSTATUS 0x0014
106#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 82#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 83#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108#define OMAP24XX_GPIO_IRQENABLE2 0x002c 84#define OMAP24XX_GPIO_IRQENABLE2 0x002c
@@ -126,7 +102,6 @@
126#define OMAP24XX_GPIO_SETDATAOUT 0x0094 102#define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 103
128#define OMAP4_GPIO_REVISION 0x0000 104#define OMAP4_GPIO_REVISION 0x0000
129#define OMAP4_GPIO_SYSCONFIG 0x0010
130#define OMAP4_GPIO_EOI 0x0020 105#define OMAP4_GPIO_EOI 0x0020
131#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 106#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 107#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
@@ -138,7 +113,6 @@
138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 113#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139#define OMAP4_GPIO_IRQWAKEN0 0x0044 114#define OMAP4_GPIO_IRQWAKEN0 0x0044
140#define OMAP4_GPIO_IRQWAKEN1 0x0048 115#define OMAP4_GPIO_IRQWAKEN1 0x0048
141#define OMAP4_GPIO_SYSSTATUS 0x0114
142#define OMAP4_GPIO_IRQENABLE1 0x011c 116#define OMAP4_GPIO_IRQENABLE1 0x011c
143#define OMAP4_GPIO_WAKE_EN 0x0120 117#define OMAP4_GPIO_WAKE_EN 0x0120
144#define OMAP4_GPIO_IRQSTATUS2 0x0128 118#define OMAP4_GPIO_IRQSTATUS2 0x0128
@@ -159,26 +133,6 @@
159#define OMAP4_GPIO_SETWKUENA 0x0184 133#define OMAP4_GPIO_SETWKUENA 0x0184
160#define OMAP4_GPIO_CLEARDATAOUT 0x0190 134#define OMAP4_GPIO_CLEARDATAOUT 0x0190
161#define OMAP4_GPIO_SETDATAOUT 0x0194 135#define OMAP4_GPIO_SETDATAOUT 0x0194
162/*
163 * omap34xx specific GPIO registers
164 */
165
166#define OMAP34XX_GPIO1_BASE 0x48310000
167#define OMAP34XX_GPIO2_BASE 0x49050000
168#define OMAP34XX_GPIO3_BASE 0x49052000
169#define OMAP34XX_GPIO4_BASE 0x49054000
170#define OMAP34XX_GPIO5_BASE 0x49056000
171#define OMAP34XX_GPIO6_BASE 0x49058000
172
173/*
174 * OMAP44XX specific GPIO registers
175 */
176#define OMAP44XX_GPIO1_BASE 0x4a310000
177#define OMAP44XX_GPIO2_BASE 0x48055000
178#define OMAP44XX_GPIO3_BASE 0x48057000
179#define OMAP44XX_GPIO4_BASE 0x48059000
180#define OMAP44XX_GPIO5_BASE 0x4805B000
181#define OMAP44XX_GPIO6_BASE 0x4805D000
182 136
183struct gpio_bank { 137struct gpio_bank {
184 unsigned long pbase; 138 unsigned long pbase;
@@ -203,97 +157,12 @@ struct gpio_bank {
203 struct clk *dbck; 157 struct clk *dbck;
204 u32 mod_usage; 158 u32 mod_usage;
205 u32 dbck_enable_mask; 159 u32 dbck_enable_mask;
160 struct device *dev;
161 bool dbck_flag;
206}; 162};
207 163
208#ifdef CONFIG_ARCH_OMAP16XX
209static struct gpio_bank gpio_bank_1610[5] = {
210 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
211 METHOD_MPUIO },
212 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
213 METHOD_GPIO_1610 },
214 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
215 METHOD_GPIO_1610 },
216 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
217 METHOD_GPIO_1610 },
218 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
219 METHOD_GPIO_1610 },
220};
221#endif
222
223#ifdef CONFIG_ARCH_OMAP15XX
224static struct gpio_bank gpio_bank_1510[2] = {
225 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
226 METHOD_MPUIO },
227 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
228 METHOD_GPIO_1510 }
229};
230#endif
231
232#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
233static struct gpio_bank gpio_bank_7xx[7] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
235 METHOD_MPUIO },
236 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
237 METHOD_GPIO_7XX },
238 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
239 METHOD_GPIO_7XX },
240 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
241 METHOD_GPIO_7XX },
242 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
243 METHOD_GPIO_7XX },
244 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
245 METHOD_GPIO_7XX },
246 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
247 METHOD_GPIO_7XX },
248};
249#endif
250
251#ifdef CONFIG_ARCH_OMAP2
252
253static struct gpio_bank gpio_bank_242x[4] = {
254 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
255 METHOD_GPIO_24XX },
256 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
257 METHOD_GPIO_24XX },
258 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
259 METHOD_GPIO_24XX },
260 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
261 METHOD_GPIO_24XX },
262};
263
264static struct gpio_bank gpio_bank_243x[5] = {
265 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
266 METHOD_GPIO_24XX },
267 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
268 METHOD_GPIO_24XX },
269 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
270 METHOD_GPIO_24XX },
271 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
272 METHOD_GPIO_24XX },
273 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
274 METHOD_GPIO_24XX },
275};
276
277#endif
278
279#ifdef CONFIG_ARCH_OMAP3 164#ifdef CONFIG_ARCH_OMAP3
280static struct gpio_bank gpio_bank_34xx[6] = {
281 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
282 METHOD_GPIO_24XX },
283 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
284 METHOD_GPIO_24XX },
285 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
286 METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
288 METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
290 METHOD_GPIO_24XX },
291 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
292 METHOD_GPIO_24XX },
293};
294
295struct omap3_gpio_regs { 165struct omap3_gpio_regs {
296 u32 sysconfig;
297 u32 irqenable1; 166 u32 irqenable1;
298 u32 irqenable2; 167 u32 irqenable2;
299 u32 wake_en; 168 u32 wake_en;
@@ -309,25 +178,14 @@ struct omap3_gpio_regs {
309static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 178static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
310#endif 179#endif
311 180
312#ifdef CONFIG_ARCH_OMAP4 181/*
313static struct gpio_bank gpio_bank_44xx[6] = { 182 * TODO: Cleanup gpio_bank usage as it is having information
314 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, 183 * related to all instances of the device
315 METHOD_GPIO_44XX }, 184 */
316 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, 185static struct gpio_bank *gpio_bank;
317 METHOD_GPIO_44XX },
318 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
319 METHOD_GPIO_44XX },
320 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
321 METHOD_GPIO_44XX },
322 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
323 METHOD_GPIO_44XX },
324 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
325 METHOD_GPIO_44XX },
326};
327 186
328#endif 187static int bank_width;
329 188
330static struct gpio_bank *gpio_bank;
331/* TODO: Analyze removing gpio_bank_count usage from driver code */ 189/* TODO: Analyze removing gpio_bank_count usage from driver code */
332int gpio_bank_count; 190int gpio_bank_count;
333 191
@@ -634,6 +492,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
634 u32 val; 492 u32 val;
635 u32 l; 493 u32 l;
636 494
495 if (!bank->dbck_flag)
496 return;
497
637 if (debounce < 32) 498 if (debounce < 32)
638 debounce = 0x01; 499 debounce = 0x01;
639 else if (debounce > 7936) 500 else if (debounce > 7936)
@@ -643,7 +504,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
643 504
644 l = 1 << get_gpio_index(gpio); 505 l = 1 << get_gpio_index(gpio);
645 506
646 if (cpu_is_omap44xx()) 507 if (bank->method == METHOD_GPIO_44XX)
647 reg += OMAP4_GPIO_DEBOUNCINGTIME; 508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
648 else 509 else
649 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
@@ -651,7 +512,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
651 __raw_writel(debounce, reg); 512 __raw_writel(debounce, reg);
652 513
653 reg = bank->base; 514 reg = bank->base;
654 if (cpu_is_omap44xx()) 515 if (bank->method == METHOD_GPIO_44XX)
655 reg += OMAP4_GPIO_DEBOUNCENABLE; 516 reg += OMAP4_GPIO_DEBOUNCENABLE;
656 else 517 else
657 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
@@ -660,12 +521,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
660 521
661 if (debounce) { 522 if (debounce) {
662 val |= l; 523 val |= l;
663 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 524 clk_enable(bank->dbck);
664 clk_enable(bank->dbck);
665 } else { 525 } else {
666 val &= ~l; 526 val &= ~l;
667 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 527 clk_disable(bank->dbck);
668 clk_disable(bank->dbck);
669 } 528 }
670 bank->dbck_enable_mask = val; 529 bank->dbck_enable_mask = val;
671 530
@@ -1537,7 +1396,8 @@ static struct platform_device omap_mpuio_device = {
1537 1396
1538static inline void mpuio_init(void) 1397static inline void mpuio_init(void)
1539{ 1398{
1540 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); 1399 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1400 platform_set_drvdata(&omap_mpuio_device, bank);
1541 1401
1542 if (platform_driver_register(&omap_mpuio_driver) == 0) 1402 if (platform_driver_register(&omap_mpuio_driver) == 0)
1543 (void) platform_device_register(&omap_mpuio_device); 1403 (void) platform_device_register(&omap_mpuio_device);
@@ -1642,6 +1502,13 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1642 unsigned long flags; 1502 unsigned long flags;
1643 1503
1644 bank = container_of(chip, struct gpio_bank, chip); 1504 bank = container_of(chip, struct gpio_bank, chip);
1505
1506 if (!bank->dbck) {
1507 bank->dbck = clk_get(bank->dev, "dbclk");
1508 if (IS_ERR(bank->dbck))
1509 dev_err(bank->dev, "Could not get gpio dbck\n");
1510 }
1511
1645 spin_lock_irqsave(&bank->lock, flags); 1512 spin_lock_irqsave(&bank->lock, flags);
1646 _set_gpio_debounce(bank, offset, debounce); 1513 _set_gpio_debounce(bank, offset, debounce);
1647 spin_unlock_irqrestore(&bank->lock, flags); 1514 spin_unlock_irqrestore(&bank->lock, flags);
@@ -1670,24 +1537,6 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1670 1537
1671/*---------------------------------------------------------------------*/ 1538/*---------------------------------------------------------------------*/
1672 1539
1673static int initialized;
1674#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1675static struct clk * gpio_ick;
1676#endif
1677
1678#if defined(CONFIG_ARCH_OMAP2)
1679static struct clk * gpio_fck;
1680#endif
1681
1682#if defined(CONFIG_ARCH_OMAP2430)
1683static struct clk * gpio5_ick;
1684static struct clk * gpio5_fck;
1685#endif
1686
1687#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1688static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1689#endif
1690
1691static void __init omap_gpio_show_rev(struct gpio_bank *bank) 1540static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1692{ 1541{
1693 u32 rev; 1542 u32 rev;
@@ -1710,6 +1559,19 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1710 */ 1559 */
1711static struct lock_class_key gpio_lock_class; 1560static struct lock_class_key gpio_lock_class;
1712 1561
1562static inline int init_gpio_info(struct platform_device *pdev)
1563{
1564 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1565 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1566 GFP_KERNEL);
1567 if (!gpio_bank) {
1568 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1569 return -ENOMEM;
1570 }
1571 return 0;
1572}
1573
1574/* TODO: Cleanup cpu_is_* checks */
1713static void omap_gpio_mod_init(struct gpio_bank *bank, int id) 1575static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1714{ 1576{
1715 if (cpu_class_is_omap2()) { 1577 if (cpu_class_is_omap2()) {
@@ -1773,16 +1635,9 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1773 1635
1774static void __init omap_gpio_chip_init(struct gpio_bank *bank) 1636static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1775{ 1637{
1776 int j, bank_width = 16; 1638 int j;
1777 static int gpio; 1639 static int gpio;
1778 1640
1779 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX)
1780 bank_width = 32; /* 7xx has 32-bit GPIOs */
1781
1782 if ((bank->method == METHOD_GPIO_24XX) ||
1783 (bank->method == METHOD_GPIO_44XX))
1784 bank_width = 32;
1785
1786 bank->mod_usage = 0; 1641 bank->mod_usage = 0;
1787 /* 1642 /*
1788 * REVISIT eventually switch from OMAP-specific gpio structs 1643 * REVISIT eventually switch from OMAP-specific gpio structs
@@ -1826,139 +1681,68 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1826 set_irq_data(bank->irq, bank); 1681 set_irq_data(bank->irq, bank);
1827} 1682}
1828 1683
1829static int __init _omap_gpio_init(void) 1684static int __devinit omap_gpio_probe(struct platform_device *pdev)
1830{ 1685{
1831 int i; 1686 static int gpio_init_done;
1687 struct omap_gpio_platform_data *pdata;
1688 struct resource *res;
1689 int id;
1832 struct gpio_bank *bank; 1690 struct gpio_bank *bank;
1833 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1834 char clk_name[11];
1835 1691
1836 initialized = 1; 1692 if (!pdev->dev.platform_data)
1693 return -EINVAL;
1837 1694
1838#if defined(CONFIG_ARCH_OMAP1) 1695 pdata = pdev->dev.platform_data;
1839 if (cpu_is_omap15xx()) {
1840 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1841 if (IS_ERR(gpio_ick))
1842 printk("Could not get arm_gpio_ck\n");
1843 else
1844 clk_enable(gpio_ick);
1845 }
1846#endif
1847#if defined(CONFIG_ARCH_OMAP2)
1848 if (cpu_class_is_omap2()) {
1849 gpio_ick = clk_get(NULL, "gpios_ick");
1850 if (IS_ERR(gpio_ick))
1851 printk("Could not get gpios_ick\n");
1852 else
1853 clk_enable(gpio_ick);
1854 gpio_fck = clk_get(NULL, "gpios_fck");
1855 if (IS_ERR(gpio_fck))
1856 printk("Could not get gpios_fck\n");
1857 else
1858 clk_enable(gpio_fck);
1859 1696
1860 /* 1697 if (!gpio_init_done) {
1861 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK 1698 int ret;
1862 */
1863#if defined(CONFIG_ARCH_OMAP2430)
1864 if (cpu_is_omap2430()) {
1865 gpio5_ick = clk_get(NULL, "gpio5_ick");
1866 if (IS_ERR(gpio5_ick))
1867 printk("Could not get gpio5_ick\n");
1868 else
1869 clk_enable(gpio5_ick);
1870 gpio5_fck = clk_get(NULL, "gpio5_fck");
1871 if (IS_ERR(gpio5_fck))
1872 printk("Could not get gpio5_fck\n");
1873 else
1874 clk_enable(gpio5_fck);
1875 }
1876#endif
1877 }
1878#endif
1879 1699
1880#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 1700 ret = init_gpio_info(pdev);
1881 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1701 if (ret)
1882 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { 1702 return ret;
1883 sprintf(clk_name, "gpio%d_ick", i + 1);
1884 gpio_iclks[i] = clk_get(NULL, clk_name);
1885 if (IS_ERR(gpio_iclks[i]))
1886 printk(KERN_ERR "Could not get %s\n", clk_name);
1887 else
1888 clk_enable(gpio_iclks[i]);
1889 }
1890 } 1703 }
1891#endif
1892 1704
1705 id = pdev->id;
1706 bank = &gpio_bank[id];
1893 1707
1894#ifdef CONFIG_ARCH_OMAP15XX 1708 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1895 if (cpu_is_omap15xx()) { 1709 if (unlikely(!res)) {
1896 gpio_bank_count = 2; 1710 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1897 gpio_bank = gpio_bank_1510; 1711 return -ENODEV;
1898 bank_size = SZ_2K;
1899 }
1900#endif
1901#if defined(CONFIG_ARCH_OMAP16XX)
1902 if (cpu_is_omap16xx()) {
1903 gpio_bank_count = 5;
1904 gpio_bank = gpio_bank_1610;
1905 bank_size = SZ_2K;
1906 }
1907#endif
1908#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1909 if (cpu_is_omap7xx()) {
1910 gpio_bank_count = 7;
1911 gpio_bank = gpio_bank_7xx;
1912 bank_size = SZ_2K;
1913 }
1914#endif
1915#ifdef CONFIG_ARCH_OMAP2
1916 if (cpu_is_omap242x()) {
1917 gpio_bank_count = 4;
1918 gpio_bank = gpio_bank_242x;
1919 }
1920 if (cpu_is_omap243x()) {
1921 gpio_bank_count = 5;
1922 gpio_bank = gpio_bank_243x;
1923 }
1924#endif
1925#ifdef CONFIG_ARCH_OMAP3
1926 if (cpu_is_omap34xx()) {
1927 gpio_bank_count = OMAP34XX_NR_GPIOS;
1928 gpio_bank = gpio_bank_34xx;
1929 }
1930#endif
1931#ifdef CONFIG_ARCH_OMAP4
1932 if (cpu_is_omap44xx()) {
1933 gpio_bank_count = OMAP34XX_NR_GPIOS;
1934 gpio_bank = gpio_bank_44xx;
1935 } 1712 }
1936#endif
1937 for (i = 0; i < gpio_bank_count; i++) {
1938 1713
1939 bank = &gpio_bank[i]; 1714 bank->irq = res->start;
1940 spin_lock_init(&bank->lock); 1715 bank->virtual_irq_start = pdata->virtual_irq_start;
1716 bank->method = pdata->bank_type;
1717 bank->dev = &pdev->dev;
1718 bank->dbck_flag = pdata->dbck_flag;
1719 bank_width = pdata->bank_width;
1941 1720
1942 /* Static mapping, never released */ 1721 spin_lock_init(&bank->lock);
1943 bank->base = ioremap(bank->pbase, bank_size);
1944 if (!bank->base) {
1945 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1946 continue;
1947 }
1948 1722
1949 omap_gpio_mod_init(bank, i); 1723 /* Static mapping, never released */
1950 omap_gpio_chip_init(bank); 1724 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1725 if (unlikely(!res)) {
1726 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1727 return -ENODEV;
1728 }
1951 1729
1952 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1730 bank->base = ioremap(res->start, resource_size(res));
1953 sprintf(clk_name, "gpio%d_dbck", i + 1); 1731 if (!bank->base) {
1954 bank->dbck = clk_get(NULL, clk_name); 1732 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1955 if (IS_ERR(bank->dbck)) 1733 return -ENOMEM;
1956 printk(KERN_ERR "Could not get %s\n", clk_name);
1957 }
1958 } 1734 }
1959 1735
1736 pm_runtime_enable(bank->dev);
1737 pm_runtime_get_sync(bank->dev);
1738
1739 omap_gpio_mod_init(bank, id);
1740 omap_gpio_chip_init(bank);
1960 omap_gpio_show_rev(bank); 1741 omap_gpio_show_rev(bank);
1961 1742
1743 if (!gpio_init_done)
1744 gpio_init_done = 1;
1745
1962 return 0; 1746 return 0;
1963} 1747}
1964 1748
@@ -2252,8 +2036,6 @@ void omap_gpio_save_context(void)
2252 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 2036 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2253 for (i = 1; i < gpio_bank_count; i++) { 2037 for (i = 1; i < gpio_bank_count; i++) {
2254 struct gpio_bank *bank = &gpio_bank[i]; 2038 struct gpio_bank *bank = &gpio_bank[i];
2255 gpio_context[i].sysconfig =
2256 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2257 gpio_context[i].irqenable1 = 2039 gpio_context[i].irqenable1 =
2258 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 2040 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2259 gpio_context[i].irqenable2 = 2041 gpio_context[i].irqenable2 =
@@ -2284,8 +2066,6 @@ void omap_gpio_restore_context(void)
2284 2066
2285 for (i = 1; i < gpio_bank_count; i++) { 2067 for (i = 1; i < gpio_bank_count; i++) {
2286 struct gpio_bank *bank = &gpio_bank[i]; 2068 struct gpio_bank *bank = &gpio_bank[i];
2287 __raw_writel(gpio_context[i].sysconfig,
2288 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2289 __raw_writel(gpio_context[i].irqenable1, 2069 __raw_writel(gpio_context[i].irqenable1,
2290 bank->base + OMAP24XX_GPIO_IRQENABLE1); 2070 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2291 __raw_writel(gpio_context[i].irqenable2, 2071 __raw_writel(gpio_context[i].irqenable2,
@@ -2310,25 +2090,28 @@ void omap_gpio_restore_context(void)
2310} 2090}
2311#endif 2091#endif
2312 2092
2093static struct platform_driver omap_gpio_driver = {
2094 .probe = omap_gpio_probe,
2095 .driver = {
2096 .name = "omap_gpio",
2097 },
2098};
2099
2313/* 2100/*
2314 * This may get called early from board specific init 2101 * gpio driver register needs to be done before
2315 * for boards that have interrupts routed via FPGA. 2102 * machine_init functions access gpio APIs.
2103 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2316 */ 2104 */
2317int __init omap_gpio_init(void) 2105static int __init omap_gpio_drv_reg(void)
2318{ 2106{
2319 if (!initialized) 2107 return platform_driver_register(&omap_gpio_driver);
2320 return _omap_gpio_init();
2321 else
2322 return 0;
2323} 2108}
2109postcore_initcall(omap_gpio_drv_reg);
2324 2110
2325static int __init omap_gpio_sysinit(void) 2111static int __init omap_gpio_sysinit(void)
2326{ 2112{
2327 int ret = 0; 2113 int ret = 0;
2328 2114
2329 if (!initialized)
2330 ret = _omap_gpio_init();
2331
2332 mpuio_init(); 2115 mpuio_init();
2333 2116
2334#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 2117#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 22:01:42 -0400