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-rw-r--r--arch/arm/plat-nomadik/include/plat/mtu.h54
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
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+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
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1#ifndef __PLAT_MTU_H
2#define __PLAT_MTU_H
3
4/*
5 * Guaranteed runtime conversion range in seconds for
6 * the clocksource and clockevent.
7 */
8#define MTU_MIN_RANGE 4
9
10/* should be set by the platform code */
11extern void __iomem *mtu_base;
12
13/*
14 * The MTU device hosts four different counters, with 4 set of
15 * registers. These are register names.
16 */
17
18#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
19#define MTU_RIS 0x04 /* Raw interrupt status */
20#define MTU_MIS 0x08 /* Masked interrupt status */
21#define MTU_ICR 0x0C /* Interrupt clear register */
22
23/* per-timer registers take 0..3 as argument */
24#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
25#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
26#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
27#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
28
29/* bits for the control register */
30#define MTU_CRn_ENA 0x80
31#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
32#define MTU_CRn_PRESCALE_MASK 0x0c
33#define MTU_CRn_PRESCALE_1 0x00
34#define MTU_CRn_PRESCALE_16 0x04
35#define MTU_CRn_PRESCALE_256 0x08
36#define MTU_CRn_32BITS 0x02
37#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
38
39/* Other registers are usual amba/primecell registers, currently not used */
40#define MTU_ITCR 0xff0
41#define MTU_ITOP 0xff4
42
43#define MTU_PERIPH_ID0 0xfe0
44#define MTU_PERIPH_ID1 0xfe4
45#define MTU_PERIPH_ID2 0xfe8
46#define MTU_PERIPH_ID3 0xfeC
47
48#define MTU_PCELL0 0xff0
49#define MTU_PCELL1 0xff4
50#define MTU_PCELL2 0xff8
51#define MTU_PCELL3 0xffC
52
53#endif /* __PLAT_MTU_H */
54